)]}'
{
  "commit": "6ce84819d2de76b4c747b433e9bc7ec43cefb186",
  "tree": "7fb11c083f4b39a083c180d446ddd31da1851436",
  "parents": [
    "b99c146598839b5b5613bd6921d1846e7aeaf1ae"
  ],
  "author": {
    "name": "Stanislav Mekhanoshin",
    "email": "Stanislav.Mekhanoshin@amd.com",
    "time": "Fri Apr 10 10:50:33 2026 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Apr 10 10:50:33 2026 -0700"
  },
  "message": "[AMDGPU] Always update SETREG MSBs if offset is 0 (#191362)\n\nWe can always update immediate if Offset is zero. The bits\nHW will write are always at the same position if offset is 0.\n\nIn particular it removes redundant mode changes created as seen\nin the hazard-setreg-vgpr-msb-gfx1250.mir.\n\nThis still relies on the wrong behavior that SETREG updates\nMSBs, so it will have to be changed later. Test immediates may be\noff from desired for that reason in this patch.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "bcac1dc35ae539d15115b28337ef3189b1322125",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp",
      "new_id": "d8754babce1c3a46f9512f370a5f9e667d1727c9",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp"
    },
    {
      "type": "modify",
      "old_id": "95c8c67566f5198626491ff6b74294776b1a3ee0",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/AMDGPU/hazard-setreg-vgpr-msb-gfx1250.mir",
      "new_id": "317a7fce56f436cf167be5e0ea8aa6617fd1bdce",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/AMDGPU/hazard-setreg-vgpr-msb-gfx1250.mir"
    },
    {
      "type": "modify",
      "old_id": "6f08fa8df94fb3a34736112c74ba3b020276f845",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir",
      "new_id": "ba3c247b07da475ee6ae9ef9ec1bd822aa178ffe",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/AMDGPU/vgpr-setreg-mode-swar.mir"
    }
  ]
}