)]}'
{
  "commit": "6b6efcd743ee692cd86e1885f7ba2e621c2eaf45",
  "tree": "9f23464fb0d396c633c804da8713833ed45e0c18",
  "parents": [
    "c3b6f14a89f518288dfdafbf711827c9ffb4adc5"
  ],
  "author": {
    "name": "Jim Lin",
    "email": "jim@andestech.com",
    "time": "Wed Feb 11 17:17:12 2026 +0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Feb 11 17:17:12 2026 +0800"
  },
  "message": "[RISCV] Add sp register as implicit/implicit-def register to save/restore call (#180667)\n\nThis is a follow-up PR for\nhttps://github.com/llvm/llvm-project/pull/180133.",
  "tree_diff": [
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "llvm/lib/Target/RISCV/RISCVFrameLowering.cpp",
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      "new_mode": 33188,
      "new_path": "llvm/lib/Target/RISCV/RISCVFrameLowering.cpp"
    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/RISCV/zcmp-cm-popretz.mir",
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      "new_mode": 33188,
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}