[AVR] Remove workarounds for instructions using Z register (NFCI) (#156361)
The generated disassembler can now correctly decode these instructions.
All we need to do is to add `bits<0> z` to their encodings and provide a
decoder method that adds Z register to the instruction.
diff --git a/llvm/lib/Target/AVR/AVRInstrFormats.td b/llvm/lib/Target/AVR/AVRInstrFormats.td
index e1e65b5..eb4daf7 100644
--- a/llvm/lib/Target/AVR/AVRInstrFormats.td
+++ b/llvm/lib/Target/AVR/AVRInstrFormats.td
@@ -79,6 +79,7 @@
//===----------------------------------------------------------------------===//
class FZRd<bits<3> t, dag outs, dag ins, string asmstr, list<dag> pattern>
: AVRInst16<outs, ins, asmstr, pattern> {
+ bits<0> z;
bits<5> rd;
let Inst{15 - 12} = 0b1001;
diff --git a/llvm/lib/Target/AVR/AVRInstrInfo.td b/llvm/lib/Target/AVR/AVRInstrInfo.td
index 958e138..70efda4 100644
--- a/llvm/lib/Target/AVR/AVRInstrInfo.td
+++ b/llvm/lib/Target/AVR/AVRInstrInfo.td
@@ -1230,7 +1230,9 @@
let Defs = [R31R30] in
def SPMZPi : F16<0b1001010111111000, (outs), (ins ZREG:$z), "spm $z+", []>,
- Requires<[HasSPMX]>;
+ Requires<[HasSPMX]> {
+ bits<0> z;
+ }
}
// Read data from IO location operations.
diff --git a/llvm/lib/Target/AVR/CMakeLists.txt b/llvm/lib/Target/AVR/CMakeLists.txt
index 2d5cb7e..a31c545 100644
--- a/llvm/lib/Target/AVR/CMakeLists.txt
+++ b/llvm/lib/Target/AVR/CMakeLists.txt
@@ -6,8 +6,7 @@
tablegen(LLVM AVRGenAsmWriter.inc -gen-asm-writer)
tablegen(LLVM AVRGenCallingConv.inc -gen-callingconv)
tablegen(LLVM AVRGenDAGISel.inc -gen-dag-isel)
-tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler
- -ignore-non-decodable-operands)
+tablegen(LLVM AVRGenDisassemblerTables.inc -gen-disassembler)
tablegen(LLVM AVRGenInstrInfo.inc -gen-instr-info)
tablegen(LLVM AVRGenMCCodeEmitter.inc -gen-emitter)
tablegen(LLVM AVRGenRegisterInfo.inc -gen-register-info)
diff --git a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
index 56b3cf7..d874697 100644
--- a/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
+++ b/llvm/lib/Target/AVR/Disassembler/AVRDisassembler.cpp
@@ -91,6 +91,12 @@
return MCDisassembler::Success;
}
+static DecodeStatus DecodeZREGRegisterClass(MCInst &Inst,
+ const MCDisassembler *Decoder) {
+ Inst.addOperand(MCOperand::createReg(AVR::R31R30));
+ return MCDisassembler::Success;
+}
+
static DecodeStatus decodeFIOARr(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
unsigned addr = 0;
diff --git a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
index 4812191..5adffee 100644
--- a/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
+++ b/llvm/lib/Target/AVR/MCTargetDesc/AVRInstPrinter.cpp
@@ -101,23 +101,6 @@
void AVRInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
raw_ostream &O) {
const MCOperandInfo &MOI = this->MII.get(MI->getOpcode()).operands()[OpNo];
- if (MOI.RegClass == AVR::ZREGRegClassID) {
- // Special case for the Z register, which sometimes doesn't have an operand
- // in the MCInst.
- O << "Z";
- return;
- }
-
- if (OpNo >= MI->size()) {
- // Not all operands are correctly disassembled at the moment. This means
- // that some machine instructions won't have all the necessary operands
- // set.
- // To avoid asserting, print <unknown> instead until the necessary support
- // has been implemented.
- O << "<unknown>";
- return;
- }
-
const MCOperand &Op = MI->getOperand(OpNo);
if (Op.isReg()) {
