)]}'
{
  "commit": "68dfda06dfd20184d06e8ac82cb6eb96fd8f122e",
  "tree": "efef868d6b6ac1af5ce17b176d75e7418ccdbe67",
  "parents": [
    "5a13758207cc0f1e02a0fe0ae492bb98e2d3d070"
  ],
  "author": {
    "name": "Changpeng Fang",
    "email": "changpeng.fang@amd.com",
    "time": "Tue May 12 06:59:10 2026 -0700"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue May 12 06:59:10 2026 -0700"
  },
  "message": "[AMDGPU] Optimize fneg and fsub with packed fp16 ops (#196659)\n\nThe work optimize fneg and fsub when packed half math instructions are supported.\n  On global isel path, for wider vectors of G_FSUB with element type of f16, we should\nsplit them to v2f16 for v_pk_add_f16 to be selected.\n  On SelectionDAG path, we make FNEG legal, and also make sure to split wider vectors\nto v2f16. In this way, we can fold fneg into the source modifiers for packed half ops.",
  "tree_diff": [
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp",
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      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp"
    },
    {
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      "old_id": "4bd0a0bee00ff21f4e11ceb5e575cc12bed95753",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/SIISelLowering.cpp",
      "new_id": "6c88bc7145edac27d16c625484f3b09f6c94299d",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/SIISelLowering.cpp"
    },
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      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll",
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      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-mul.ll"
    },
    {
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      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll",
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      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/AMDGPU/GlobalISel/combine-fma-sub-neg-mul.ll"
    },
    {
      "type": "modify",
      "old_id": "b9702d2befab85f79b9c60733160dbc807ac4c51",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir",
      "new_id": "6c444f26c13d402d696a9fbf677f36ff9f84b2cf",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fsub.mir"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "f788803a3c3585c33c2898c0320c919739bc9da7",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/AMDGPU/packed-fneg-fsub-fp16.ll"
    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll",
      "new_id": "d05ea8951f23ef17fdb37bc0299dc1e0b16495ba",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/AMDGPU/strict_fsub.f16.ll"
    },
    {
      "type": "modify",
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      "old_path": "llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll",
      "new_id": "6c943da2f1dd7f47c4f3d81394465e8eab92fb8b",
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      "new_path": "llvm/test/CodeGen/AMDGPU/wmma-gfx12-w32-f16-f32-matrix-modifiers.ll"
    }
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}