commit | 64d4ade3bb7d0d8cc87a777f4964e68f2f25edf9 | [log] [tgz] |
---|---|---|
author | Momchil Velikov <momchil.velikov@arm.com> | Fri May 10 11:14:26 2024 +0100 |
committer | GitHub <noreply@github.com> | Fri May 10 11:14:26 2024 +0100 |
tree | 1d9ccce4b3f7ffa9a009aa009c27d809feb151f9 | |
parent | b277bf56d7654877a1c4b59dc08bc96b4d75b649 [diff] |
[AArch64] Add intrinsics for 16-bit non-widening FMLA/FMLS (#88553) According to the specification in https://github.com/ARM-software/acle/pull/309 add the following intrinsics void svmla[_single]_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm) void svmla[_single]_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm) void svmls[_single]_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm) void svmls[_single]_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm) void svmla_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16x2_t zm) void svmla_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16x4_t zm) void svmls_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16x2_t zm) void svmls_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16x4_t zm) void svmla_lane_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm, uint64_t imm_idx) void svmla_lane_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm, uint64_t imm_idx) void svmls_lane_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm, uint64_t imm_idx) void svmls_lane_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm, uint64_t imm_idx) as well as the corresponding `_bf16` variants.
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