; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -start-after=codegenprepare -stop-before finalize-isel | FileCheck %s

define <8 x i16> @_Z3fooiPiPs(<8 x i16> %src, <8 x i1> %mask) #0 {
  ; CHECK-LABEL: name: _Z3fooiPiPs
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   liveins: $xmm0, $xmm1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vr128x = COPY $xmm1
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vr128x = COPY $xmm0
  ; CHECK-NEXT:   [[VPSLLWZ128ri:%[0-9]+]]:vr128x = VPSLLWZ128ri [[COPY]], 15
  ; CHECK-NEXT:   [[VPMOVW2MZ128kr:%[0-9]+]]:vk16wm = VPMOVW2MZ128kr killed [[VPSLLWZ128ri]]
  ; CHECK-NEXT:   [[VPEXPANDWZ128rmk:%[0-9]+]]:vr128x = VPEXPANDWZ128rmk [[COPY1]], killed [[VPMOVW2MZ128kr]], $noreg, 1, $noreg, 0, $noreg :: (load unknown-size from `ptr null`, align 1)
  ; CHECK-NEXT:   $xmm0 = COPY [[VPEXPANDWZ128rmk]]
  ; CHECK-NEXT:   RET 0, $xmm0
entry:
  %res = call <8 x i16> @llvm.masked.expandload.v8i16(ptr null, <8 x i1> %mask, <8 x i16> %src)
  ret <8 x i16> %res
}

define <8 x i16> @_Z3foo2iPiPs(<8 x i16> %src, <8 x i1> %mask) #0 {
  ; CHECK-LABEL: name: _Z3foo2iPiPs
  ; CHECK: bb.0.entry:
  ; CHECK-NEXT:   liveins: $xmm0, $xmm1
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vr128x = COPY $xmm1
  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vr128x = COPY $xmm0
  ; CHECK-NEXT:   [[VPSLLWZ128ri:%[0-9]+]]:vr128x = VPSLLWZ128ri [[COPY]], 15
  ; CHECK-NEXT:   [[VPMOVW2MZ128kr:%[0-9]+]]:vk16wm = VPMOVW2MZ128kr killed [[VPSLLWZ128ri]]
  ; CHECK-NEXT:   [[VPEXPANDWZ128rmk:%[0-9]+]]:vr128x = VPEXPANDWZ128rmk [[COPY1]], killed [[VPMOVW2MZ128kr]], $noreg, 1, $noreg, 0, $noreg :: (load unknown-size from `ptr null`, align 16)
  ; CHECK-NEXT:   $xmm0 = COPY [[VPEXPANDWZ128rmk]]
  ; CHECK-NEXT:   RET 0, $xmm0
entry:
  %res = call <8 x i16> @llvm.masked.expandload.v8i16(ptr align 16 null, <8 x i1> %mask, <8 x i16> %src)
  ret <8 x i16> %res
}

; Function Attrs: nocallback nofree nosync nounwind willreturn memory(argmem: write)
declare <8 x i16> @llvm.masked.expandload.v8i16(ptr, <8 x i1>, <8 x i16>)

attributes #0 = { "target-cpu"="icelake-server" }
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(argmem: write) }