commit 61c16142b4d52b0e62db1e39d21093a56cd5f886
author Tim Northover <tnorthover@apple.com> Thu Aug 04 21:39:49 2016 +0000
committer Tim Northover <tnorthover@apple.com> Thu Aug 04 21:39:49 2016 +0000
tree d0d724026b74e6bbbfd471eb469855271677025a
parent 1cfa919b3d796b99a8fe0c3dfeb9999b3f48fd81

GlobalISel: extend add widening to SUB, MUL, OR, AND and XOR.

These are the operations that are trivially identical. Division is omitted for
now because you need to use the correct sign/zero extension.

llvm-svn: 277775

llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp b/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
index 31092a5..01d87d1 100644
--- a/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/MachineLegalizeHelper.cpp
@@ -100,7 +100,12 @@
   switch (MI.getOpcode()) {
   default:
     return UnableToLegalize;
-  case TargetOpcode::G_ADD: {
+  case TargetOpcode::G_ADD:
+  case TargetOpcode::G_AND:
+  case TargetOpcode::G_MUL:
+  case TargetOpcode::G_OR:
+  case TargetOpcode::G_XOR:
+  case TargetOpcode::G_SUB: {
     // Perform operation at larger width (any extension is fine here, high bits
     // don't affect the result) and then truncate the result back to the
     // original type.
@@ -114,7 +119,8 @@
     MIRBuilder.buildAnyExtend(WideTy, Src2Ext, MI.getOperand(2).getReg());
 
     unsigned DstExt = MRI.createGenericVirtualRegister(WideSize);
-    MIRBuilder.buildAdd(WideTy, DstExt, Src1Ext, Src2Ext);
+    MIRBuilder.buildInstr(MI.getOpcode(), WideTy)
+      .addDef(DstExt).addUse(Src1Ext).addUse(Src2Ext);
 
     MIRBuilder.buildTrunc(MI.getType(), MI.getOperand(0).getReg(), DstExt);
     MI.eraseFromParent();