# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-- -mattr=+amx-int8,avx512f -run-pass=fastpretileconfig -o - %s | FileCheck %s

# Test the case which has TILELOADD being mixed in pseudo AMX instruction
...
---
name:            main
alignment:       16
tracksRegLiveness: true
registers:
  - { id: 0, class: gr64_nosp }
  - { id: 1, class: gr64 }
  - { id: 2, class: gr16 }
  - { id: 3, class: gr16 }
  - { id: 4, class: tile }
  - { id: 5, class: tile }
  - { id: 6, class: tile }
  - { id: 7, class: tile }
  - { id: 8, class: gr32 }
  - { id: 9, class: vr512 }
frameInfo:
  maxAlignment:    16
stack:
  - { id: 0, size: 1024, alignment: 16 }
  - { id: 1, size: 64, alignment: 4 }
machineFunctionInfo:
  amxProgModel: ManagedRA
body:             |
  bb.0.entry:
    ; CHECK-LABEL: name: main
    ; CHECK: [[AVX512_512_SET0_:%[0-9]+]]:vr512 = AVX512_512_SET0
    ; CHECK-NEXT: VMOVUPSZmr %stack.2, 1, $noreg, 0, $noreg, [[AVX512_512_SET0_]] :: (store (s512) into %stack.2, align 4)
    ; CHECK-NEXT: MOV8mi %stack.2, 1, $noreg, 0, $noreg, 1 :: (store (s512) into %stack.2, align 4)
    ; CHECK-NEXT: [[MOV32ri64_:%[0-9]+]]:gr64_nosp = MOV32ri64 32
    ; CHECK-NEXT: [[LEA64r:%[0-9]+]]:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg
    ; CHECK-NEXT: [[MOV16ri:%[0-9]+]]:gr16 = MOV16ri 32
    ; CHECK-NEXT: [[MOV16ri1:%[0-9]+]]:gr16 = MOV16ri 8
    ; CHECK-NEXT: PLDTILECFGV %stack.2, 1, $noreg, 0, $noreg, implicit-def $tmm0, implicit-def $tmm1, implicit-def $tmm2, implicit-def $tmm3, implicit-def $tmm4, implicit-def $tmm5, implicit-def $tmm6, implicit-def $tmm7 :: (load (s512) from %stack.2, align 4)
    ; CHECK-NEXT: $tmm0 = TILELOADD [[LEA64r]], 1, [[MOV32ri64_]], 0, $noreg
    ; CHECK-NEXT: [[PTILELOADDV:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri1]], [[MOV16ri]], [[LEA64r]], 1, [[MOV32ri64_]], 0, $noreg
    ; CHECK-NEXT: [[PTILELOADDV1:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri1]], [[MOV16ri]], [[LEA64r]], 1, [[MOV32ri64_]], 0, $noreg
    ; CHECK-NEXT: [[PTILELOADDV2:%[0-9]+]]:tile = PTILELOADDV [[MOV16ri1]], [[MOV16ri]], [[LEA64r]], 1, [[MOV32ri64_]], 0, $noreg
    ; CHECK-NEXT: [[PTDPBSSDV:%[0-9]+]]:tile = PTDPBSSDV [[MOV16ri1]], [[MOV16ri]], [[MOV16ri]], killed [[PTILELOADDV2]], killed [[PTILELOADDV]], killed [[PTILELOADDV1]]
    ; CHECK-NEXT: PTILESTOREDV killed [[MOV16ri1]], killed [[MOV16ri]], killed [[LEA64r]], 1, killed [[MOV32ri64_]], 0, $noreg, killed [[PTDPBSSDV]]
    ; CHECK-NEXT: [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
    ; CHECK-NEXT: $eax = COPY killed [[MOV32r0_]]
    ; CHECK-NEXT: RET 0, killed $eax
    %0:gr64_nosp = MOV32ri64 32
    %1:gr64 = LEA64r %stack.0, 1, $noreg, 0, $noreg
    %2:gr16 = MOV16ri 32
    %3:gr16 = MOV16ri 8
    $tmm0   = TILELOADD %1, 1, %0, 0, $noreg
    %4:tile = PTILELOADDV %3, %2, %1, 1, %0, 0, $noreg
    %5:tile = PTILELOADDV %3, %2, %1, 1, %0, 0, $noreg
    %6:tile = PTILELOADDV %3, %2, %1, 1, %0, 0, $noreg
    %7:tile = PTDPBSSDV %3, %2, %2, killed %6, killed %4, killed %5
    PTILESTOREDV killed %3, killed %2, killed %1, 1, killed %0, 0, $noreg, killed %7
    %8:gr32 = MOV32r0 implicit-def dead $eflags
    $eax = COPY killed %8
    RET 0, killed $eax

...
# GlobalIsel doesn't use all virtual registers and there may be virtual
# registers without a class.
# Note that %3 doesn't have a class: gpr instead of gr64.
---
name:            test_unused
legalized:       true
regBankSelected: true
selected:        true
failedISel:      false
tracksRegLiveness: true
registers:
  - { id: 0, class: gr64, preferred-register: '' }
  - { id: 1, class: gr64_with_sub_8bit, preferred-register: '' }
  - { id: 2, class: gr64, preferred-register: '' }
  - { id: 3, class: gpr, preferred-register: '' }
  - { id: 4, class: gr64, preferred-register: '' }
  - { id: 5, class: gr8, preferred-register: '' }
liveins:
  - { reg: '$rdi', virtual-reg: '' }
  - { reg: '$rsi', virtual-reg: '' }
machineFunctionInfo:
  amxProgModel: ManagedRA
body:             |
  bb.1.entry:
    liveins: $rdi, $rsi

    ; CHECK-LABEL: name: test_unused
    ; CHECK: liveins: $rdi, $rsi
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64_with_sub_8bit = COPY $rsi
    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr8 = COPY [[COPY1]].sub_8bit
    ; CHECK-NEXT: $cl = COPY [[COPY2]]
    ; CHECK-NEXT: [[SHR64rCL:%[0-9]+]]:gr64 = SHR64rCL [[COPY]], implicit-def $eflags, implicit $cl
    ; CHECK-NEXT: [[ADD64ri32_:%[0-9]+]]:gr64 = ADD64ri32 [[SHR64rCL]], 123456789, implicit-def $eflags
    ; CHECK-NEXT: $rax = COPY [[ADD64ri32_]]
    ; CHECK-NEXT: RET 0, implicit $rax
    %0:gr64 = COPY $rdi
    %1:gr64_with_sub_8bit = COPY $rsi
    %5:gr8 = COPY %1.sub_8bit
    $cl = COPY %5
    %2:gr64 = SHR64rCL %0, implicit-def $eflags, implicit $cl
    %4:gr64 = ADD64ri32 %2, 123456789, implicit-def $eflags
    $rax = COPY %4
    RET 0, implicit $rax

...