commit 5f996705e0cadc43771da12dec0670680230ca56
author Hsiangkai Wang <kai.wang@sifive.com> Wed Aug 04 07:57:13 2021 +0800
committer Hsiangkai Wang <kai.wang@sifive.com> Mon Aug 09 17:38:15 2021 +0800
tree 3d1e177cd030c68fbfdcc0e819abd0eff83344e3
parent b5c608c37775dafa5e1a9a07963ab03ee080493d

[RISCV] Half-precision for vget/vset.

Differential Revision: https://reviews.llvm.org/D107433

clang/include/clang/Basic/riscv_vector.td

diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td
index 48c032d..ebe3286 100644
--- a/clang/include/clang/Basic/riscv_vector.td
+++ b/clang/include/clang/Basic/riscv_vector.td
@@ -2086,7 +2086,7 @@
       }
       }] in {
     foreach dst_lmul = ["(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)", "(SFixedLog2LMUL:2)"] in {
-      def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "csilfd", dst_lmul # "v">;
+      def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "csilxfd", dst_lmul # "v">;
       def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "UvUvKz", "csil", dst_lmul # "Uv">;
     }
   }
@@ -2105,7 +2105,7 @@
       }
       }] in {
     foreach dst_lmul = ["(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in {
-      def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "csilfd">;
+      def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "csilxfd">;
       def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "Uv" # dst_lmul #"UvKzUv", "csil">;
     }
   }