[X86] Add tests showing failure to concat matching CVTPS2DQ/CVTTPS2DQ vector ops (#172836)

llvm/test/CodeGen/X86/combine-cvtp2si.ll

diff --git a/llvm/test/CodeGen/X86/combine-cvtp2si.ll b/llvm/test/CodeGen/X86/combine-cvtp2si.ll
new file mode 100644
index 0000000..838271b
--- /dev/null
+++ b/llvm/test/CodeGen/X86/combine-cvtp2si.ll
@@ -0,0 +1,67 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge | FileCheck %s --check-prefixes=AVX,AVX1OR2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX,AVX1OR2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX512
+
+define <8 x i32> @concat_cvtps2dq_v8i32_v4f32(<4 x float> %a0, <4 x float> %a1) {
+; AVX-LABEL: concat_cvtps2dq_v8i32_v4f32:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vcvtps2dq %xmm0, %xmm0
+; AVX-NEXT:    vcvtps2dq %xmm1, %xmm1
+; AVX-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX-NEXT:    retq
+  %v0 = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a0)
+  %v1 = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a1)
+  %res = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  ret <8 x i32> %res
+}
+
+define <16 x i32> @concat_cvtps2dq_v16i32_v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> %a3) {
+; AVX1OR2-LABEL: concat_cvtps2dq_v16i32_v4f32:
+; AVX1OR2:       # %bb.0:
+; AVX1OR2-NEXT:    vcvtps2dq %xmm0, %xmm0
+; AVX1OR2-NEXT:    vcvtps2dq %xmm1, %xmm1
+; AVX1OR2-NEXT:    vcvtps2dq %xmm2, %xmm2
+; AVX1OR2-NEXT:    vcvtps2dq %xmm3, %xmm3
+; AVX1OR2-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1OR2-NEXT:    vinsertf128 $1, %xmm3, %ymm2, %ymm1
+; AVX1OR2-NEXT:    retq
+;
+; AVX512-LABEL: concat_cvtps2dq_v16i32_v4f32:
+; AVX512:       # %bb.0:
+; AVX512-NEXT:    vcvtps2dq %xmm0, %xmm0
+; AVX512-NEXT:    vcvtps2dq %xmm1, %xmm1
+; AVX512-NEXT:    vcvtps2dq %xmm2, %xmm2
+; AVX512-NEXT:    vcvtps2dq %xmm3, %xmm3
+; AVX512-NEXT:    vinsertf128 $1, %xmm3, %ymm2, %ymm2
+; AVX512-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX512-NEXT:    vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
+; AVX512-NEXT:    retq
+  %v0 = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a0)
+  %v1 = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a1)
+  %v2 = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a2)
+  %v3 = call <4 x i32> @llvm.x86.sse2.cvtps2dq(<4 x float> %a3)
+  %r01 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %r23 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %res = shufflevector <8 x i32> %r01, <8 x i32> %r23, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  ret <16 x i32> %res
+}
+
+define <16 x i32> @concat_cvtps2dq_v16i32_v8f32(<8 x float> %a0, <8 x float> %a1) {
+; AVX1OR2-LABEL: concat_cvtps2dq_v16i32_v8f32:
+; AVX1OR2:       # %bb.0:
+; AVX1OR2-NEXT:    vcvtps2dq %ymm0, %ymm0
+; AVX1OR2-NEXT:    vcvtps2dq %ymm1, %ymm1
+; AVX1OR2-NEXT:    retq
+;
+; AVX512-LABEL: concat_cvtps2dq_v16i32_v8f32:
+; AVX512:       # %bb.0:
+; AVX512-NEXT:    vcvtps2dq %ymm0, %ymm0
+; AVX512-NEXT:    vcvtps2dq %ymm1, %ymm1
+; AVX512-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+; AVX512-NEXT:    retq
+  %v0 = call <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float> %a0)
+  %v1 = call <8 x i32> @llvm.x86.avx.cvt.ps2dq.256(<8 x float> %a1)
+  %res = shufflevector <8 x i32> %v0, <8 x i32> %v1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  ret <16 x i32> %res
+}

llvm/test/CodeGen/X86/combine-cvttp2si.ll

diff --git a/llvm/test/CodeGen/X86/combine-cvttp2si.ll b/llvm/test/CodeGen/X86/combine-cvttp2si.ll
new file mode 100644
index 0000000..caa3f5e
--- /dev/null
+++ b/llvm/test/CodeGen/X86/combine-cvttp2si.ll
@@ -0,0 +1,67 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=sandybridge | FileCheck %s --check-prefixes=AVX,AVX1OR2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v3 | FileCheck %s --check-prefixes=AVX,AVX1OR2
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64-v4 | FileCheck %s --check-prefixes=AVX,AVX512
+
+define <8 x i32> @concat_cvttps2dq_v8i32_v4f32(<4 x float> %a0, <4 x float> %a1) {
+; AVX-LABEL: concat_cvttps2dq_v8i32_v4f32:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vcvttps2dq %xmm0, %xmm0
+; AVX-NEXT:    vcvttps2dq %xmm1, %xmm1
+; AVX-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX-NEXT:    retq
+  %v0 = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0)
+  %v1 = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a1)
+  %res = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  ret <8 x i32> %res
+}
+
+define <16 x i32> @concat_cvttps2dq_v16i32_v4f32(<4 x float> %a0, <4 x float> %a1, <4 x float> %a2, <4 x float> %a3) {
+; AVX1OR2-LABEL: concat_cvttps2dq_v16i32_v4f32:
+; AVX1OR2:       # %bb.0:
+; AVX1OR2-NEXT:    vcvttps2dq %xmm0, %xmm0
+; AVX1OR2-NEXT:    vcvttps2dq %xmm1, %xmm1
+; AVX1OR2-NEXT:    vcvttps2dq %xmm2, %xmm2
+; AVX1OR2-NEXT:    vcvttps2dq %xmm3, %xmm3
+; AVX1OR2-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX1OR2-NEXT:    vinsertf128 $1, %xmm3, %ymm2, %ymm1
+; AVX1OR2-NEXT:    retq
+;
+; AVX512-LABEL: concat_cvttps2dq_v16i32_v4f32:
+; AVX512:       # %bb.0:
+; AVX512-NEXT:    vcvttps2dq %xmm0, %xmm0
+; AVX512-NEXT:    vcvttps2dq %xmm1, %xmm1
+; AVX512-NEXT:    vcvttps2dq %xmm2, %xmm2
+; AVX512-NEXT:    vcvttps2dq %xmm3, %xmm3
+; AVX512-NEXT:    vinsertf128 $1, %xmm3, %ymm2, %ymm2
+; AVX512-NEXT:    vinsertf128 $1, %xmm1, %ymm0, %ymm0
+; AVX512-NEXT:    vinsertf64x4 $1, %ymm2, %zmm0, %zmm0
+; AVX512-NEXT:    retq
+  %v0 = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a0)
+  %v1 = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a1)
+  %v2 = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a2)
+  %v3 = call <4 x i32> @llvm.x86.sse2.cvttps2dq(<4 x float> %a3)
+  %r01 = shufflevector <4 x i32> %v0, <4 x i32> %v1, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %r23 = shufflevector <4 x i32> %v2, <4 x i32> %v3, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+  %res = shufflevector <8 x i32> %r01, <8 x i32> %r23, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  ret <16 x i32> %res
+}
+
+define <16 x i32> @concat_cvttps2dq_v16i32_v8f32(<8 x float> %a0, <8 x float> %a1) {
+; AVX1OR2-LABEL: concat_cvttps2dq_v16i32_v8f32:
+; AVX1OR2:       # %bb.0:
+; AVX1OR2-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX1OR2-NEXT:    vcvttps2dq %ymm1, %ymm1
+; AVX1OR2-NEXT:    retq
+;
+; AVX512-LABEL: concat_cvttps2dq_v16i32_v8f32:
+; AVX512:       # %bb.0:
+; AVX512-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX512-NEXT:    vcvttps2dq %ymm1, %ymm1
+; AVX512-NEXT:    vinsertf64x4 $1, %ymm1, %zmm0, %zmm0
+; AVX512-NEXT:    retq
+  %v0 = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a0)
+  %v1 = call <8 x i32> @llvm.x86.avx.cvtt.ps2dq.256(<8 x float> %a1)
+  %res = shufflevector <8 x i32> %v0, <8 x i32> %v1, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
+  ret <16 x i32> %res
+}