# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=si-fix-sgpr-copies -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s

---
name:            global_load_saddr_to_valu
tracksRegLiveness: true
body:             |
  ; GCN-LABEL: name: global_load_saddr_to_valu
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   liveins: $vgpr0_vgpr1
  ; GCN:   [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  ; GCN: bb.1:
  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GCN:   [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
  ; GCN:   [[GLOBAL_LOAD_DWORD:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD [[PHI]], 0, 0, implicit $exec
  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
  ; GCN:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
  ; GCN:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
  ; GCN:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
  ; GCN:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
  ; GCN:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec
  ; GCN:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec
  ; GCN:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
  ; GCN:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; GCN: bb.2:
  ; GCN:   S_ENDPGM 0
  bb.0:
    liveins: $vgpr0_vgpr1
      %0:sreg_64 = COPY $vgpr0_vgpr1

  bb.1:
      %1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
      %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
      %4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %1, %3, 0, 0, implicit $exec
      %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
      S_CMP_LG_U64 %2, 0, implicit-def $scc
      S_CBRANCH_SCC1 %bb.1, implicit $scc

  bb.2:
      S_ENDPGM 0
...

---
name:            global_load_saddr_to_valu_non_zero_vaddr
tracksRegLiveness: true
body:             |
  ; GCN-LABEL: name: global_load_saddr_to_valu_non_zero_vaddr
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   liveins: $vgpr0_vgpr1
  ; GCN:   [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  ; GCN: bb.1:
  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GCN:   [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
  ; GCN:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
  ; GCN:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub0, implicit $exec
  ; GCN:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
  ; GCN:   [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; GCN:   [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[REG_SEQUENCE]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec
  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
  ; GCN:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
  ; GCN:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
  ; GCN:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
  ; GCN:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
  ; GCN:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE1]], 0, implicit $exec
  ; GCN:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec
  ; GCN:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
  ; GCN:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; GCN: bb.2:
  ; GCN:   S_ENDPGM 0
  bb.0:
    liveins: $vgpr0_vgpr1
      %0:sreg_64 = COPY $vgpr0_vgpr1

  bb.1:
      %1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
      %3:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
      %4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %1, %3, 0, 0, implicit $exec
      %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
      S_CMP_LG_U64 %2, 0, implicit-def $scc
      S_CBRANCH_SCC1 %bb.1, implicit $scc

  bb.2:
      S_ENDPGM 0
...


---
name:            global_load_saddr_to_valu_undef_vaddr
tracksRegLiveness: true
body:             |
  ; GCN-LABEL: name: global_load_saddr_to_valu_undef_vaddr
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   liveins: $vgpr0_vgpr1
  ; GCN:   [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  ; GCN: bb.1:
  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GCN:   [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
  ; GCN:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub0, implicit $exec
  ; GCN:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
  ; GCN:   [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; GCN:   [[GLOBAL_LOAD_DWORD_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR [[REG_SEQUENCE]], undef %4:vgpr_32, 0, 0, implicit $exec
  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
  ; GCN:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
  ; GCN:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
  ; GCN:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
  ; GCN:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
  ; GCN:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE1]], 0, implicit $exec
  ; GCN:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec
  ; GCN:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
  ; GCN:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; GCN: bb.2:
  ; GCN:   S_ENDPGM 0
  bb.0:
    liveins: $vgpr0_vgpr1
      %0:sreg_64 = COPY $vgpr0_vgpr1

  bb.1:
      %1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
      %4:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %1, undef %3:vgpr_32, 0, 0, implicit $exec
      %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
      S_CMP_LG_U64 %2, 0, implicit-def $scc
      S_CBRANCH_SCC1 %bb.1, implicit $scc

  bb.2:
      S_ENDPGM 0
...

---
name:            global_store_saddr_to_valu
tracksRegLiveness: true
body:             |
  ; GCN-LABEL: name: global_store_saddr_to_valu
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   liveins: $vgpr0_vgpr1
  ; GCN:   [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  ; GCN: bb.1:
  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GCN:   [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
  ; GCN:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; GCN:   GLOBAL_STORE_DWORD [[PHI]], [[DEF]], 0, 0, implicit $exec
  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
  ; GCN:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
  ; GCN:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
  ; GCN:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
  ; GCN:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
  ; GCN:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec
  ; GCN:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec
  ; GCN:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
  ; GCN:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; GCN: bb.2:
  ; GCN:   S_ENDPGM 0
  bb.0:
    liveins: $vgpr0_vgpr1
      %0:sreg_64 = COPY $vgpr0_vgpr1

  bb.1:
      %1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
      %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
      %4:vgpr_32 = IMPLICIT_DEF
      GLOBAL_STORE_DWORD_SADDR %3, %4, %1, 0, 0, implicit $exec
      %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
      S_CMP_LG_U64 %2, 0, implicit-def $scc
      S_CBRANCH_SCC1 %bb.1, implicit $scc

  bb.2:
      S_ENDPGM 0
...

---
name:            global_addtid_load_saddr_to_valu
tracksRegLiveness: true
body:             |
  ; GCN-LABEL: name: global_addtid_load_saddr_to_valu
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   liveins: $vgpr0_vgpr1
  ; GCN:   [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  ; GCN: bb.1:
  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GCN:   [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %6, %bb.1
  ; GCN:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub0, implicit $exec
  ; GCN:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
  ; GCN:   [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; GCN:   [[GLOBAL_LOAD_DWORD_ADDTID_SADDR:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_DWORD_ADDTID_SADDR [[REG_SEQUENCE]], 0, 0, implicit $exec
  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
  ; GCN:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
  ; GCN:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
  ; GCN:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
  ; GCN:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
  ; GCN:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE1]], 0, implicit $exec
  ; GCN:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec
  ; GCN:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
  ; GCN:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; GCN: bb.2:
  ; GCN:   S_ENDPGM 0
  bb.0:
    liveins: $vgpr0_vgpr1
      %0:sreg_64 = COPY $vgpr0_vgpr1

  bb.1:
      %1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
      %4:vgpr_32 = GLOBAL_LOAD_DWORD_ADDTID_SADDR %1, 0, 0, implicit $exec
      %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
      S_CMP_LG_U64 %2, 0, implicit-def $scc
      S_CBRANCH_SCC1 %bb.1, implicit $scc

  bb.2:
      S_ENDPGM 0
...

---
name:            global_store_addtid_saddr_to_valu
tracksRegLiveness: true
body:             |
  ; GCN-LABEL: name: global_store_addtid_saddr_to_valu
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   liveins: $vgpr0_vgpr1
  ; GCN:   [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  ; GCN: bb.1:
  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GCN:   [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %6, %bb.1
  ; GCN:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; GCN:   [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub0, implicit $exec
  ; GCN:   [[V_READFIRSTLANE_B32_1:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[PHI]].sub1, implicit $exec
  ; GCN:   [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, [[V_READFIRSTLANE_B32_1]], %subreg.sub1
  ; GCN:   GLOBAL_STORE_DWORD_ADDTID_SADDR [[DEF]], [[REG_SEQUENCE]], 0, 0, implicit $exec
  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
  ; GCN:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
  ; GCN:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
  ; GCN:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
  ; GCN:   [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
  ; GCN:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE1]], 0, implicit $exec
  ; GCN:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE1]], implicit $exec
  ; GCN:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
  ; GCN:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; GCN: bb.2:
  ; GCN:   S_ENDPGM 0
  bb.0:
    liveins: $vgpr0_vgpr1
      %0:sreg_64 = COPY $vgpr0_vgpr1

  bb.1:
      %1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
      %4:vgpr_32 = IMPLICIT_DEF
      GLOBAL_STORE_DWORD_ADDTID_SADDR %4, %1, 0, 0, implicit $exec
      %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
      S_CMP_LG_U64 %2, 0, implicit-def $scc
      S_CBRANCH_SCC1 %bb.1, implicit $scc

  bb.2:
      S_ENDPGM 0
...

---
name:            global_atomic_noret_saddr_to_valu
tracksRegLiveness: true
body:             |
  ; GCN-LABEL: name: global_atomic_noret_saddr_to_valu
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   liveins: $vgpr0_vgpr1
  ; GCN:   [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  ; GCN: bb.1:
  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GCN:   [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %6, %bb.1
  ; GCN:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  ; GCN:   GLOBAL_ATOMIC_ADD [[PHI]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec
  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
  ; GCN:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
  ; GCN:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
  ; GCN:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
  ; GCN:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
  ; GCN:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec
  ; GCN:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec
  ; GCN:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
  ; GCN:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; GCN: bb.2:
  ; GCN:   S_ENDPGM 0
  bb.0:
    liveins: $vgpr0_vgpr1
      %0:sreg_64 = COPY $vgpr0_vgpr1

  bb.1:
      %1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
      %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
      GLOBAL_ATOMIC_ADD_SADDR %3, %3, %1, 0, 0, implicit $exec
      %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
      S_CMP_LG_U64 %2, 0, implicit-def $scc
      S_CBRANCH_SCC1 %bb.1, implicit $scc

  bb.2:
      S_ENDPGM 0
...

---
name:            global_atomic_rtn_saddr_to_valu
tracksRegLiveness: true
body:             |
  ; GCN-LABEL: name: global_atomic_rtn_saddr_to_valu
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   liveins: $vgpr0_vgpr1
  ; GCN:   [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr0_vgpr1
  ; GCN: bb.1:
  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GCN:   [[PHI:%[0-9]+]]:vreg_64 = PHI [[COPY]], %bb.0, %7, %bb.1
  ; GCN:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  ; GCN:   [[GLOBAL_ATOMIC_ADD_RTN:%[0-9]+]]:vgpr_32 = GLOBAL_ATOMIC_ADD_RTN [[PHI]], [[V_MOV_B32_e32_]], 0, 0, implicit $exec
  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub0
  ; GCN:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]].sub1
  ; GCN:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY1]], 1, implicit $exec
  ; GCN:   [[V_AND_B32_e64_1:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[COPY2]], 0, implicit $exec
  ; GCN:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_AND_B32_e64_]], %subreg.sub0, [[V_AND_B32_e64_1]], %subreg.sub1
  ; GCN:   [[V_CMP_NE_U64_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U64_e64 [[REG_SEQUENCE]], 0, implicit $exec
  ; GCN:   [[COPY3:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]], implicit $exec
  ; GCN:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U64_e64_]], implicit-def $scc
  ; GCN:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; GCN: bb.2:
  ; GCN:   S_ENDPGM 0
  bb.0:
    liveins: $vgpr0_vgpr1
      %0:sreg_64 = COPY $vgpr0_vgpr1

  bb.1:
      %1:sreg_64 = PHI %0, %bb.0, %2, %bb.1
      %3:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
      %4:vgpr_32 = GLOBAL_ATOMIC_ADD_SADDR_RTN %3, %3, %1, 0, 0, implicit $exec
      %2:sreg_64 = S_AND_B64 %1, 1, implicit-def $scc
      S_CMP_LG_U64 %2, 0, implicit-def $scc
      S_CBRANCH_SCC1 %bb.1, implicit $scc

  bb.2:
      S_ENDPGM 0
...

---
name:            scratch_load_saddr_to_valu
tracksRegLiveness: true
body:             |
  ; GCN-LABEL: name: scratch_load_saddr_to_valu
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   liveins: $vgpr0
  ; GCN:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GCN: bb.1:
  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GCN:   [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %6, %bb.1
  ; GCN:   [[SCRATCH_LOAD_DWORD:%[0-9]+]]:vgpr_32 = SCRATCH_LOAD_DWORD [[PHI]], 0, 0, implicit $exec, implicit $flat_scr
  ; GCN:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[PHI]], 1, implicit $exec
  ; GCN:   [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[V_AND_B32_e64_]], 0, implicit $exec
  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_AND_B32_e64_]], implicit $exec
  ; GCN:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def $scc
  ; GCN:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; GCN: bb.2:
  ; GCN:   S_ENDPGM 0
  bb.0:
    liveins: $vgpr0
      %0:sgpr_32 = COPY $vgpr0

  bb.1:
      %1:sgpr_32 = PHI %0, %bb.0, %2, %bb.1
      %4:vgpr_32 = SCRATCH_LOAD_DWORD_SADDR %1, 0, 0, implicit $exec, implicit $flat_scr
      %2:sgpr_32 = S_AND_B32 %1, 1, implicit-def $scc
      S_CMP_LG_U32 %2, 0, implicit-def $scc
      S_CBRANCH_SCC1 %bb.1, implicit $scc

  bb.2:
      S_ENDPGM 0
...

---
name:            scratch_store_saddr_to_valu
tracksRegLiveness: true
body:             |
  ; GCN-LABEL: name: scratch_store_saddr_to_valu
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   liveins: $vgpr0
  ; GCN:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GCN: bb.1:
  ; GCN:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
  ; GCN:   [[PHI:%[0-9]+]]:vgpr_32 = PHI [[COPY]], %bb.0, %6, %bb.1
  ; GCN:   [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
  ; GCN:   SCRATCH_STORE_DWORD [[DEF]], [[PHI]], 0, 0, implicit $exec, implicit $flat_scr
  ; GCN:   [[V_AND_B32_e64_:%[0-9]+]]:vgpr_32 = V_AND_B32_e64 [[PHI]], 1, implicit $exec
  ; GCN:   [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[V_AND_B32_e64_]], 0, implicit $exec
  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_AND_B32_e64_]], implicit $exec
  ; GCN:   $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def $scc
  ; GCN:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; GCN: bb.2:
  ; GCN:   S_ENDPGM 0
  bb.0:
    liveins: $vgpr0
      %0:sgpr_32 = COPY $vgpr0

  bb.1:
      %1:sgpr_32 = PHI %0, %bb.0, %2, %bb.1
      %4:vgpr_32 = IMPLICIT_DEF
      SCRATCH_STORE_DWORD_SADDR %4, %1, 0, 0, implicit $exec, implicit $flat_scr
      %2:sgpr_32 = S_AND_B32 %1, 1, implicit-def $scc
      S_CMP_LG_U32 %2, 0, implicit-def $scc
      S_CBRANCH_SCC1 %bb.1, implicit $scc

  bb.2:
      S_ENDPGM 0
...