)]}'
{
  "commit": "5dd48c4901c60f2a38aa4e78160cc72eafcbbc5b",
  "tree": "bfbb31ca969fa54c2b2a04592e251b2ac1efa595",
  "parents": [
    "6657d4bd70523e6852f07f64711fb15bdf7b347a"
  ],
  "author": {
    "name": "Matt Arsenault",
    "email": "Matthew.Arsenault@amd.com",
    "time": "Mon Nov 25 19:20:51 2024 -0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Nov 25 19:20:51 2024 -0800"
  },
  "message": "AMDGPU: MC support for v_cvt_scalef32_pk32_f32_[fp|bf]6 of gfx950 (#117590)\n\nCo-authored-by: Pravin Jagtap \u003cPravin.Jagtap@amd.com\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "64e88cf03b429b111b9494184e3dd94dfb64d68f",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/AMDGPU.td",
      "new_id": "15a1bb799804d7f86e63ed667a06a78b0a1d122e",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/AMDGPU.td"
    },
    {
      "type": "modify",
      "old_id": "20f573da0ec82b70b22f60865f9c969e36a3006c",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h",
      "new_id": "1a09f55dfdb28abcaf0354a192ded6b2a35c3235",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/AMDGPUSubtarget.h"
    },
    {
      "type": "modify",
      "old_id": "136fe2e3f90d02c608e79da2feddd70290212908",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp",
      "new_id": "fa5f86b0788cc28ad4e1310405225496d6374431",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp"
    },
    {
      "type": "modify",
      "old_id": "3e20a2ab9e66ca5f3db41af6dc8db6e46c0683ef",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h",
      "new_id": "b19e4b74a394cbf87b22e255c8769dbb38ea4d54",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.h"
    },
    {
      "type": "modify",
      "old_id": "acb703dba6a980a5cde05a24658ee32158c72f61",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/SIInstrInfo.td",
      "new_id": "f20d6526e20b2c7bb034d0ff48d34104d21a1908",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/SIInstrInfo.td"
    },
    {
      "type": "modify",
      "old_id": "e3baeed01841ab890d5ff336b57829109bd64078",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/SIRegisterInfo.td",
      "new_id": "11ca4df6e9f445c96ab4523614a553d6aefe78d6",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/SIRegisterInfo.td"
    },
    {
      "type": "modify",
      "old_id": "cf00910210e0bd8f359e49ce97dc96b39164ef3b",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/VOP3Instructions.td",
      "new_id": "1009f2d9593609344ffae0bd9a53da7a19ca42e5",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/VOP3Instructions.td"
    },
    {
      "type": "modify",
      "old_id": "85cd02aa714175528caf5e23b49b6a2d62adbfc9",
      "old_mode": 33188,
      "old_path": "llvm/test/MC/AMDGPU/gfx950_asm_features.s",
      "new_id": "95d31d2293075f3c2149629dd0f7fc9da594619d",
      "new_mode": 33188,
      "new_path": "llvm/test/MC/AMDGPU/gfx950_asm_features.s"
    },
    {
      "type": "modify",
      "old_id": "89167ae35e2967580472ae0af82e938e3c5815ec",
      "old_mode": 33188,
      "old_path": "llvm/test/MC/AMDGPU/gfx950_err.s",
      "new_id": "6eebd4f7ccd76b6f9c71dfb4affc71a1a4fb4566",
      "new_mode": 33188,
      "new_path": "llvm/test/MC/AMDGPU/gfx950_err.s"
    },
    {
      "type": "modify",
      "old_id": "80b5835fab1084377788ec9b0c3ef617e4ec29fb",
      "old_mode": 33188,
      "old_path": "llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt",
      "new_id": "73fd3edfbad48689a36bcceb048fb5bf78327166",
      "new_mode": 33188,
      "new_path": "llvm/test/MC/Disassembler/AMDGPU/gfx950_dasm_vop3.txt"
    }
  ]
}