; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs | FileCheck %s
; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -verify-machineinstrs -mattr=-isel | FileCheck --check-prefix=CHECK-NO-ISEL %s
target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
target triple = "powerpc64-unknown-linux-gnu"

define i32 @test(i32 %a, i32 %b, i32 %c, i32 %d) {
; CHECK-LABEL: test:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    slwi 5, 6, 16
; CHECK-NEXT:    extsh 6, 6
; CHECK-NEXT:    cmpwi 5, -1
; CHECK-NEXT:    add 5, 6, 3
; CHECK-NEXT:    clrlwi 6, 6, 17
; CHECK-NEXT:    sub 6, 3, 6
; CHECK-NEXT:    sub 3, 4, 3
; CHECK-NEXT:    iselgt 5, 5, 6
; CHECK-NEXT:    extsh 5, 5
; CHECK-NEXT:    add 3, 3, 5
; CHECK-NEXT:    blr
;
; CHECK-NO-ISEL-LABEL: test:
; CHECK-NO-ISEL:       # %bb.0: # %entry
; CHECK-NO-ISEL-NEXT:    slwi 7, 6, 16
; CHECK-NO-ISEL-NEXT:    extsh 5, 6
; CHECK-NO-ISEL-NEXT:    cmpwi 7, -1
; CHECK-NO-ISEL-NEXT:    ble 0, .LBB0_2
; CHECK-NO-ISEL-NEXT:  # %bb.1: # %cond.false
; CHECK-NO-ISEL-NEXT:    add 5, 5, 3
; CHECK-NO-ISEL-NEXT:    b .LBB0_3
; CHECK-NO-ISEL-NEXT:  .LBB0_2: # %cond.true
; CHECK-NO-ISEL-NEXT:    clrlwi 5, 5, 17
; CHECK-NO-ISEL-NEXT:    sub 5, 3, 5
; CHECK-NO-ISEL-NEXT:  .LBB0_3: # %cond.end
; CHECK-NO-ISEL-NEXT:    extsh 5, 5
; CHECK-NO-ISEL-NEXT:    sub 3, 4, 3
; CHECK-NO-ISEL-NEXT:    add 3, 3, 5
; CHECK-NO-ISEL-NEXT:    blr
entry:
  %sext82 = shl i32 %d, 16
  %conv29 = ashr exact i32 %sext82, 16
  %cmp = icmp slt i32 %sext82, 0
  br i1 %cmp, label %cond.true, label %cond.false

cond.true:                                        ; preds = %sw.epilog
  %and33 = and i32 %conv29, 32767
  %sub34 = sub nsw i32 %a, %and33
  br label %cond.end

cond.false:                                       ; preds = %sw.epilog
  %add37 = add nsw i32 %conv29, %a
  br label %cond.end


cond.end:                                         ; preds = %cond.false, %cond.true
  %cond = phi i32 [ %sub34, %cond.true ], [ %add37, %cond.false ]
  %sext83 = shl i32 %cond, 16
  %conv39 = ashr exact i32 %sext83, 16
  %add41 = sub i32 %b, %a
  %sub43 = add i32 %add41, %conv39
  ret i32 %sub43
}