tree 2ac20c1ecab4e23ab177af71d900758e102d16c1
parent 5f866666a6fb8a1a976a286d2f845809a7108f05
author Min-Yih Hsu <min.hsu@sifive.com> 1742250576 -0700
committer GitHub <noreply@github.com> 1742250576 -0700
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[RISCV] Update some of the RVV memory ops in SiFive P400 & P600 sched models (#129575)

This patch updates the latencies as well as occupancies of unit stride,
strided, and indexed load/store instructions in SiFive P400 & P600
scheduling models.