tree 1c2ed623c47c943e671727298a32b75afc34491e
parent 658a931c5bf3968daec1f020c3a403b1019dabd9
author Philip Reames <preames@rivosinc.com> 1756335548 -0700
committer GitHub <noreply@github.com> 1756335548 -0700
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[RISCV] Enable LUi/AUIPC+ADDI/ADDIW reg alloc hint by default (#155693)

This block of code is currently conditional on the fusions being enabled
but as far as I can tell, does no harm to generally enable. The net
effect is the generically compiled code runs slightly better on machines
with this fusion.

The actual motivation is merely to stop confusing myself when I see the
sequence in code; the register allocators choice to sometimes blow two
registers instead of one is just generally weird, and my eyes spot it
when scanning disassembly.

(Note that this is just the regalloc hint; the scheduling changes remain
conditional, and probably should remain so.)