[LoongArch] Document the inline asm `q` constraint
See #141037.
diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
index ad0755e..7fbac14 100644
--- a/llvm/docs/LangRef.rst
+++ b/llvm/docs/LangRef.rst
@@ -5614,6 +5614,8 @@
- ``m``: A memory operand whose address is formed by a base register and
offset that is suitable for use in instructions with the same addressing
mode as st.w and ld.w.
+- ``q``: A general-purpose register except for $r0 and $r1 (for the csrxchg
+ instruction).
- ``I``: A signed 12-bit constant (for arithmetic instructions).
- ``J``: An immediate integer zero.
- ``K``: An unsigned 12-bit constant (for logic instructions).
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 7135b24..e590e54 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -138,6 +138,7 @@
--------------------------------
* Changing the default code model from `small` to `medium` for 64-bit.
+* Added inline asm support for the `q` constraint.
Changes to the MIPS Backend
---------------------------
