)]}'
{
  "commit": "56ce7ede7d290758bc00dd8596f65639d1c3544f",
  "tree": "ece29ae5da497bc9cf32738818ea24efaeb8f937",
  "parents": [
    "03f6faa2c35d48d1a403c31d1587050aa168304b"
  ],
  "author": {
    "name": "Sander de Smalen",
    "email": "sander.desmalen@arm.com",
    "time": "Tue Apr 14 14:56:25 2026 +0100"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Apr 14 14:56:25 2026 +0100"
  },
  "message": "[AArch64] Fix strict weak ordering violation in regalloc hints sort. (#192055)\n\nThis fixes an error with expensive checks after landing #190139.\n\nThe issue was:\n\nError: comparison doesn\u0027t meet irreflexive requirements, assert(!(a \u003c\na)).\n\nbecause it could have previously returned \u0027true\u0027 in the ordering\nfunction if registers A and B were equal.\n\nAlso made NFC change to rename \u0027HandleMatchCmpPredicateHint\u0027 -\u003e\n\u0027HandleDestructivePredicateHint\u0027 (that was missed in the review).",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a5b934b152abb8d3a6fa46cdbb24c2f223e23702",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp",
      "new_id": "f232fa79c7022de8ef1efb47c701d6ff6ea2e972",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp"
    }
  ]
}