| commit | 56cb5cbfcdc09499d366046d6ea2ea6655fc11ef | [log] [tgz] |
|---|---|---|
| author | Philip Reames <preames@rivosinc.com> | Mon Dec 02 13:39:12 2024 -0800 |
| committer | GitHub <noreply@github.com> | Mon Dec 02 13:39:12 2024 -0800 |
| tree | 1392066f02ce99d6ab7137ef956717fb3647dbec | |
| parent | a6ef0debb1d60966b5bcc69f7d58a2b75c9c621d [diff] |
[RISCV] Remove RISCVISD::VNSRL_VL and adjust deinterleave lowering to match (#118391) Instead of directly lowering to vnsrl_vl and having custom pattern matching for that case, we can just lower to a (legal) shift and truncate, and let generic pattern matching produce the vnsrl. The major motivation for this is that I'm going to reuse this logic to handle e.g. deinterleave4 w/ i8 result. The test changes aren't particularly interesting. They're minor code improvements - I think because we do slightly better with the insert_subvector patterns, but that's mostly irrelevant.
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