commit 5229f47f9f5dd14c594aea3caa1c7d11e083bbfe
author Petar Avramovic <Petar.Avramovic@rt-rk.com> Mon Mar 11 10:08:44 2019 +0000
committer Petar Avramovic <Petar.Avramovic@rt-rk.com> Mon Mar 11 10:08:44 2019 +0000
tree 5bed9c08e1965ed35536110a2d8313db32be42b0
parent 0b17e59b5cf411b37e02e492b8d9d97450836477

[MIPS GlobalISel] NarrowScalar G_UMULH

NarrowScalar G_UMULH in LegalizerHelper 
using multiplyRegisters helper function.
NarrowScalar G_UMULH for MIPS32.

Differential Revision: https://reviews.llvm.org/D58825

llvm-svn: 355815

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index a353da2..8405fe2 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -535,6 +535,7 @@
     return Legalized;
   }
   case TargetOpcode::G_MUL:
+  case TargetOpcode::G_UMULH:
     return narrowScalarMul(MI, NarrowTy);
   case TargetOpcode::G_EXTRACT:
     return narrowScalarExtract(MI, TypeIdx, NarrowTy);
@@ -2625,13 +2626,18 @@
 
   unsigned NumDstParts = DstSize / NarrowSize;
   unsigned NumSrcParts = SrcSize / NarrowSize;
+  bool IsMulHigh = MI.getOpcode() == TargetOpcode::G_UMULH;
+  unsigned DstTmpParts = NumDstParts * (IsMulHigh ? 2 : 1);
 
-  SmallVector<unsigned, 2> Src1Parts, Src2Parts, DstRegs;
+  SmallVector<unsigned, 2> Src1Parts, Src2Parts, DstTmpRegs;
   extractParts(Src1, NarrowTy, NumSrcParts, Src1Parts);
   extractParts(Src2, NarrowTy, NumSrcParts, Src2Parts);
-  DstRegs.resize(NumDstParts);
-  multiplyRegisters(DstRegs, Src1Parts, Src2Parts, NarrowTy);
+  DstTmpRegs.resize(DstTmpParts);
+  multiplyRegisters(DstTmpRegs, Src1Parts, Src2Parts, NarrowTy);
 
+  // Take only high half of registers if this is high mul.
+  ArrayRef<unsigned> DstRegs(
+      IsMulHigh ? &DstTmpRegs[DstTmpParts / 2] : &DstTmpRegs[0], NumDstParts);
   MIRBuilder.buildMerge(DstReg, DstRegs);
   MI.eraseFromParent();
   return Legalized;