| commit | 5048a0858beb15bdd203dee89dd4df9b2a72ba5f | [log] [tgz] |
|---|---|---|
| author | Djordje Todorovic <djordje.todorovic@htecgroup.com> | Fri Mar 07 09:21:36 2025 +0100 |
| committer | GitHub <noreply@github.com> | Fri Mar 07 09:21:36 2025 +0100 |
| tree | 27b0c13f3ade106e655b02bed5b38ce4703f3b67 | |
| parent | 749d68bdfe97c6dd29fb9f7e4a7f63854ecef295 [diff] |
[RISCV] Generate MIPS load/store pair instructions (#124717) Introduce RISCVLoadStoreOptimizer MIR Pass that will do the optimization. The load/store pairing pass identifies adjacent load/store instructions operating on consecutive memory locations and merges them into a single paired instruction. This is part of MIPS extensions for the p8700 CPU. Production of ldp/sdp instructions is OFF by default, since it is beneficial for -Os only in the case of p8700 CPU.
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