[AArch64][GlobalISel] Scalarize i128 shufflevector instructions. (#119980)
This, like other operations, scalarizes shuffle vector operations with
types larger than 64bits. ImplicitDef and Freeze are also handled the
same way, to allow them to legalize. The legalization of
fewerElementsVectorShuffle is adjusted to handled scalarization.
diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index 39c09f4..2fc8ef6 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -5424,7 +5424,7 @@
// Further legalization attempts will be needed to do split further.
NarrowTy =
DstTy.changeElementCount(DstTy.getElementCount().divideCoefficientBy(2));
- unsigned NewElts = NarrowTy.getNumElements();
+ unsigned NewElts = NarrowTy.isVector() ? NarrowTy.getNumElements() : 1;
SmallVector<Register> SplitSrc1Regs, SplitSrc2Regs;
extractParts(Src1Reg, NarrowTy, 2, SplitSrc1Regs, MIRBuilder, MRI);
@@ -5535,7 +5535,7 @@
Ops.clear();
}
- MIRBuilder.buildConcatVectors(DstReg, {Lo, Hi});
+ MIRBuilder.buildMergeLikeInstr(DstReg, {Lo, Hi});
MI.eraseFromParent();
return Legalized;
}