llvm/lib/Target/AArch64/AArch64InstrFormats.td

//===- AArch64InstrFormats.td - AArch64 Instruction Formats --*- tblgen -*-===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//

//===----------------------------------------------------------------------===//
//  Describe AArch64 instructions format here
//

// Format specifies the encoding used by the instruction.  This is part of the
// ad-hoc solution used to emit machine instruction encodings by our machine
// code emitter.
class Format<bits<2> val> {
  bits<2> Value = val;
}

def PseudoFrm   : Format<0>;
def NormalFrm   : Format<1>; // Do we need any others?

// Enum describing whether an instruction is
// destructive in its first source operand.
class DestructiveInstTypeEnum<bits<4> val> {
  bits<4> Value = val;
}
def NotDestructive                : DestructiveInstTypeEnum<0>;
// Destructive in its first operand and can be MOVPRFX'd, but has no other
// special properties.
def DestructiveOther              : DestructiveInstTypeEnum<1>;
def DestructiveUnary              : DestructiveInstTypeEnum<2>;
def DestructiveBinaryImm          : DestructiveInstTypeEnum<3>;
def DestructiveBinaryShImmUnpred  : DestructiveInstTypeEnum<4>;
def DestructiveBinary             : DestructiveInstTypeEnum<5>;
def DestructiveBinaryComm         : DestructiveInstTypeEnum<6>;
def DestructiveBinaryCommWithRev  : DestructiveInstTypeEnum<7>;
def DestructiveTernaryCommWithRev : DestructiveInstTypeEnum<8>;
def DestructiveUnaryPassthru      : DestructiveInstTypeEnum<9>;

class FalseLanesEnum<bits<2> val> {
  bits<2> Value = val;
}
def FalseLanesNone  : FalseLanesEnum<0>;
def FalseLanesZero  : FalseLanesEnum<1>;
def FalseLanesUndef : FalseLanesEnum<2>;

// AArch64 Instruction Format
class AArch64Inst<Format f, string cstr> : Instruction {
  field bits<32> Inst; // Instruction encoding.
  // Mask of bits that cause an encoding to be UNPREDICTABLE.
  // If a bit is set, then if the corresponding bit in the
  // target encoding differs from its value in the "Inst" field,
  // the instruction is UNPREDICTABLE (SoftFail in abstract parlance).
  field bits<32> Unpredictable = 0;
  // SoftFail is the generic name for this field, but we alias it so
  // as to make it more obvious what it means in ARM-land.
  field bits<32> SoftFail = Unpredictable;
  let Namespace   = "AArch64";
  Format F        = f;
  bits<2> Form    = F.Value;

  // Defaults
  bit isWhile = 0;
  bit isPTestLike = 0;
  FalseLanesEnum FalseLanes = FalseLanesNone;
  DestructiveInstTypeEnum DestructiveInstType = NotDestructive;
  ElementSizeEnum ElementSize = ElementSizeNone;

  let TSFlags{10}  = isPTestLike;
  let TSFlags{9}   = isWhile;
  let TSFlags{8-7} = FalseLanes.Value;
  let TSFlags{6-3} = DestructiveInstType.Value;
  let TSFlags{2-0} = ElementSize.Value;

  let Pattern     = [];
  let Constraints = cstr;
}

class InstSubst<string Asm, dag Result, bit EmitPriority = 0>
  : InstAlias<Asm, Result, EmitPriority>, Requires<[UseNegativeImmediates]>;

// Pseudo instructions (don't have encoding information)
class Pseudo<dag oops, dag iops, list<dag> pattern, string cstr = "">
    : AArch64Inst<PseudoFrm, cstr> {
  dag OutOperandList = oops;
  dag InOperandList  = iops;
  let Pattern        = pattern;
  let isCodeGenOnly  = 1;
  let isPseudo       = 1;
}

// Real instructions (have encoding information)
class EncodedI<string cstr, list<dag> pattern> : AArch64Inst<NormalFrm, cstr> {
  let Pattern = pattern;
  let Size = 4;
}

// Normal instructions
class I<dag oops, dag iops, string asm, string operands, string cstr,
        list<dag> pattern>
    : EncodedI<cstr, pattern> {
  dag OutOperandList = oops;
  dag InOperandList  = iops;
  let AsmString      = !strconcat(asm, operands);
}

class TriOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$MHS, node:$RHS), res>;
class BinOpFrag<dag res> : PatFrag<(ops node:$LHS, node:$RHS), res>;
class UnOpFrag<dag res>  : PatFrag<(ops node:$LHS), res>;

// Helper fragment for an extract of the high portion of a 128-bit vector.
def extract_high_v16i8 :
   UnOpFrag<(extract_subvector (v16i8 node:$LHS), (i64 8))>;
def extract_high_v8i16 :
   UnOpFrag<(extract_subvector (v8i16 node:$LHS), (i64 4))>;
def extract_high_v4i32 :
   UnOpFrag<(extract_subvector (v4i32 node:$LHS), (i64 2))>;
def extract_high_v2i64 :
   UnOpFrag<(extract_subvector (v2i64 node:$LHS), (i64 1))>;

//===----------------------------------------------------------------------===//
// Asm Operand Classes.
//

// Shifter operand for arithmetic shifted encodings.
def ShifterOperand : AsmOperandClass {
  let Name = "Shifter";
}

// Shifter operand for mov immediate encodings.
def MovImm32ShifterOperand : AsmOperandClass {
  let SuperClasses = [ShifterOperand];
  let Name = "MovImm32Shifter";
  let RenderMethod = "addShifterOperands";
  let DiagnosticType = "InvalidMovImm32Shift";
}
def MovImm64ShifterOperand : AsmOperandClass {
  let SuperClasses = [ShifterOperand];
  let Name = "MovImm64Shifter";
  let RenderMethod = "addShifterOperands";
  let DiagnosticType = "InvalidMovImm64Shift";
}

// Shifter operand for arithmetic register shifted encodings.
class ArithmeticShifterOperand<int width> : AsmOperandClass {
  let SuperClasses = [ShifterOperand];
  let Name = "ArithmeticShifter" # width;
  let PredicateMethod = "isArithmeticShifter<" # width # ">";
  let RenderMethod = "addShifterOperands";
  let DiagnosticType = "AddSubRegShift" # width;
}

def ArithmeticShifterOperand32 : ArithmeticShifterOperand<32>;
def ArithmeticShifterOperand64 : ArithmeticShifterOperand<64>;

// Shifter operand for logical register shifted encodings.
class LogicalShifterOperand<int width> : AsmOperandClass {
  let SuperClasses = [ShifterOperand];
  let Name = "LogicalShifter" # width;
  let PredicateMethod = "isLogicalShifter<" # width # ">";
  let RenderMethod = "addShifterOperands";
  let DiagnosticType = "AddSubRegShift" # width;
}

def LogicalShifterOperand32 : LogicalShifterOperand<32>;
def LogicalShifterOperand64 : LogicalShifterOperand<64>;

// Shifter operand for logical vector 128/64-bit shifted encodings.
def LogicalVecShifterOperand : AsmOperandClass {
  let SuperClasses = [ShifterOperand];
  let Name = "LogicalVecShifter";
  let RenderMethod = "addShifterOperands";
}
def LogicalVecHalfWordShifterOperand : AsmOperandClass {
  let SuperClasses = [LogicalVecShifterOperand];
  let Name = "LogicalVecHalfWordShifter";
  let RenderMethod = "addShifterOperands";
}

// The "MSL" shifter on the vector MOVI instruction.
def MoveVecShifterOperand : AsmOperandClass {
  let SuperClasses = [ShifterOperand];
  let Name = "MoveVecShifter";
  let RenderMethod = "addShifterOperands";
}

// Extend operand for arithmetic encodings.
def ExtendOperand : AsmOperandClass {
  let Name = "Extend";
  let DiagnosticType = "AddSubRegExtendLarge";
}
def ExtendOperand64 : AsmOperandClass {
  let SuperClasses = [ExtendOperand];
  let Name = "Extend64";
  let DiagnosticType = "AddSubRegExtendSmall";
}
// 'extend' that's a lsl of a 64-bit register.
def ExtendOperandLSL64 : AsmOperandClass {
  let SuperClasses = [ExtendOperand];
  let Name = "ExtendLSL64";
  let RenderMethod = "addExtend64Operands";
  let DiagnosticType = "AddSubRegExtendLarge";
}

// 8-bit floating-point immediate encodings.
def FPImmOperand : AsmOperandClass {
  let Name = "FPImm";
  let ParserMethod = "tryParseFPImm<true>";
  let DiagnosticType = "InvalidFPImm";
}

def CondCode : AsmOperandClass {
  let Name = "CondCode";
  let DiagnosticType = "InvalidCondCode";
}

// A 32-bit register pasrsed as 64-bit
def GPR32as64Operand : AsmOperandClass {
  let Name = "GPR32as64";
  let ParserMethod =
      "tryParseGPROperand<false, RegConstraintEqualityTy::EqualsSubReg>";
}
def GPR32as64 : RegisterOperand<GPR32> {
  let ParserMatchClass = GPR32as64Operand;
}

// A 64-bit register pasrsed as 32-bit
def GPR64as32Operand : AsmOperandClass {
  let Name = "GPR64as32";
  let ParserMethod =
      "tryParseGPROperand<false, RegConstraintEqualityTy::EqualsSuperReg>";
}
def GPR64as32 : RegisterOperand<GPR64, "printGPR64as32"> {
  let ParserMatchClass = GPR64as32Operand;
}

// 8-bit immediate for AdvSIMD where 64-bit values of the form:
// aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
// are encoded as the eight bit value 'abcdefgh'.
def SIMDImmType10Operand : AsmOperandClass { let Name = "SIMDImmType10"; }

class UImmScaledMemoryIndexed<int Width, int Scale> : AsmOperandClass {
  let Name = "UImm" # Width # "s" # Scale;
  let DiagnosticType = "InvalidMemoryIndexed" # Scale # "UImm" # Width;
  let RenderMethod = "addImmScaledOperands<" # Scale # ">";
  let PredicateMethod = "isUImmScaled<" # Width # ", " # Scale # ">";
}

class SImmScaledMemoryIndexed<int Width, int Scale> : AsmOperandClass {
  let Name = "SImm" # Width # "s" # Scale;
  let DiagnosticType = "InvalidMemoryIndexed" # Scale # "SImm" # Width;
  let RenderMethod = "addImmScaledOperands<" # Scale # ">";
  let PredicateMethod = "isSImmScaled<" # Width # ", " # Scale # ">";
}

//===----------------------------------------------------------------------===//
// Operand Definitions.
//

// ADR[P] instruction labels.
def AdrpOperand : AsmOperandClass {
  let Name = "AdrpLabel";
  let ParserMethod = "tryParseAdrpLabel";
  let DiagnosticType = "InvalidLabel";
}
def adrplabel : Operand<i64> {
  let EncoderMethod = "getAdrLabelOpValue";
  let PrintMethod = "printAdrpLabel";
  let ParserMatchClass = AdrpOperand;
  let OperandType = "OPERAND_PCREL";
}

def AdrOperand : AsmOperandClass {
  let Name = "AdrLabel";
  let ParserMethod = "tryParseAdrLabel";
  let DiagnosticType = "InvalidLabel";
}
def adrlabel : Operand<i64> {
  let EncoderMethod = "getAdrLabelOpValue";
  let ParserMatchClass = AdrOperand;
}

class SImmOperand<int width> : AsmOperandClass {
  let Name = "SImm" # width;
  let DiagnosticType = "InvalidMemoryIndexedSImm" # width;
  let RenderMethod = "addImmOperands";
  let PredicateMethod = "isSImm<" # width # ">";
}


class AsmImmRange<int Low, int High> : AsmOperandClass {
  let Name = "Imm" # Low # "_" # High;
  let DiagnosticType = "InvalidImm" # Low # "_" # High;
  let RenderMethod = "addImmOperands";
  let PredicateMethod = "isImmInRange<" # Low # "," # High # ">";
}

// Authenticated loads for v8.3 can have scaled 10-bit immediate offsets.
def SImm10s8Operand : SImmScaledMemoryIndexed<10, 8>;
def simm10Scaled : Operand<i64> {
  let ParserMatchClass = SImm10s8Operand;
  let DecoderMethod = "DecodeSImm<10>";
  let PrintMethod = "printImmScale<8>";
}

def simm9s16 : Operand<i64> {
  let ParserMatchClass = SImmScaledMemoryIndexed<9, 16>;
  let DecoderMethod = "DecodeSImm<9>";
  let PrintMethod = "printImmScale<16>";
}

// uimm6 predicate - True if the immediate is in the range [0, 63].
def UImm6Operand : AsmOperandClass {
  let Name = "UImm6";
  let DiagnosticType = "InvalidImm0_63";
}

def uimm6 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
  let ParserMatchClass = UImm6Operand;
}

def uimm16 : Operand<i16>, ImmLeaf<i16, [{return Imm >= 0 && Imm < 65536;}]>{
  let ParserMatchClass = AsmImmRange<0, 65535>;
}

def SImm9Operand : SImmOperand<9>;
def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> {
  let ParserMatchClass = SImm9Operand;
  let DecoderMethod = "DecodeSImm<9>";
}

def SImm8Operand : SImmOperand<8>;
def simm8 : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -128 && Imm < 128; }]> {
  let ParserMatchClass = SImm8Operand;
  let DecoderMethod = "DecodeSImm<8>";
}

def SImm6Operand : SImmOperand<6>;
def simm6_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -32 && Imm < 32; }]> {
  let ParserMatchClass = SImm6Operand;
  let DecoderMethod = "DecodeSImm<6>";
}

def SImm5Operand : SImmOperand<5>;
def simm5_64b : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -16 && Imm < 16; }]> {
  let ParserMatchClass = SImm5Operand;
  let DecoderMethod = "DecodeSImm<5>";
}

def simm5_32b : Operand<i32>, ImmLeaf<i32, [{ return Imm >= -16 && Imm < 16; }]> {
  let ParserMatchClass = SImm5Operand;
  let DecoderMethod = "DecodeSImm<5>";
}

def simm5_8b : Operand<i32>, ImmLeaf<i32, [{ return (int8_t)Imm >= -16 && (int8_t)Imm < 16; }]> {
  let ParserMatchClass = SImm5Operand;
  let DecoderMethod = "DecodeSImm<5>";
  let PrintMethod = "printSImm<8>";
}

def simm5_16b : Operand<i32>, ImmLeaf<i32, [{ return (int16_t)Imm >= -16 && (int16_t)Imm < 16; }]> {
  let ParserMatchClass = SImm5Operand;
  let DecoderMethod = "DecodeSImm<5>";
  let PrintMethod = "printSImm<16>";
}

// simm7sN predicate - True if the immediate is a multiple of N in the range
// [-64 * N, 63 * N].

def SImm7s4Operand : SImmScaledMemoryIndexed<7, 4>;
def SImm7s8Operand : SImmScaledMemoryIndexed<7, 8>;
def SImm7s16Operand : SImmScaledMemoryIndexed<7, 16>;

def simm7s4 : Operand<i32> {
  let ParserMatchClass = SImm7s4Operand;
  let PrintMethod = "printImmScale<4>";
}

def simm7s8 : Operand<i32> {
  let ParserMatchClass = SImm7s8Operand;
  let PrintMethod = "printImmScale<8>";
}

def simm7s16 : Operand<i32> {
  let ParserMatchClass = SImm7s16Operand;
  let PrintMethod = "printImmScale<16>";
}

def am_sve_fi : ComplexPattern<i64, 2, "SelectAddrModeFrameIndexSVE", []>;

def am_indexed7s8   : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S8", []>;
def am_indexed7s16  : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S16", []>;
def am_indexed7s32  : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S32", []>;
def am_indexed7s64  : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S64", []>;
def am_indexed7s128 : ComplexPattern<i64, 2, "SelectAddrModeIndexed7S128", []>;

def am_indexedu6s128 : ComplexPattern<i64, 2, "SelectAddrModeIndexedU6S128", []>;
def am_indexeds9s128 : ComplexPattern<i64, 2, "SelectAddrModeIndexedS9S128", []>;

def UImmS1XForm : SDNodeXForm<imm, [{
  return CurDAG->getTargetConstant(N->getZExtValue(), SDLoc(N), MVT::i64);
}]>;
def UImmS2XForm : SDNodeXForm<imm, [{
  return CurDAG->getTargetConstant(N->getZExtValue() / 2, SDLoc(N), MVT::i64);
}]>;
def UImmS4XForm : SDNodeXForm<imm, [{
  return CurDAG->getTargetConstant(N->getZExtValue() / 4, SDLoc(N), MVT::i64);
}]>;
def UImmS8XForm : SDNodeXForm<imm, [{
  return CurDAG->getTargetConstant(N->getZExtValue() / 8, SDLoc(N), MVT::i64);
}]>;

// uimm5sN predicate - True if the immediate is a multiple of N in the range
// [0 * N, 32 * N].
def UImm5s2Operand : UImmScaledMemoryIndexed<5, 2>;
def UImm5s4Operand : UImmScaledMemoryIndexed<5, 4>;
def UImm5s8Operand : UImmScaledMemoryIndexed<5, 8>;

def uimm5s2 : Operand<i64>, ImmLeaf<i64,
                [{ return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); }],
                UImmS2XForm> {
  let ParserMatchClass = UImm5s2Operand;
  let PrintMethod = "printImmScale<2>";
}
def uimm5s4 : Operand<i64>, ImmLeaf<i64,
                [{ return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); }],
                UImmS4XForm> {
  let ParserMatchClass = UImm5s4Operand;
  let PrintMethod = "printImmScale<4>";
}
def uimm5s8 : Operand<i64>, ImmLeaf<i64,
                [{ return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); }],
                UImmS8XForm> {
  let ParserMatchClass = UImm5s8Operand;
  let PrintMethod = "printImmScale<8>";
}

// tuimm5sN predicate - similiar to uimm5sN, but use TImmLeaf (TargetConstant)
// instead of ImmLeaf (Constant)
def tuimm5s2 : Operand<i64>, TImmLeaf<i64,
                [{ return Imm >= 0 && Imm < (32*2) && ((Imm % 2) == 0); }],
                UImmS2XForm> {
  let ParserMatchClass = UImm5s2Operand;
  let PrintMethod = "printImmScale<2>";
}
def tuimm5s4 : Operand<i64>, TImmLeaf<i64,
                [{ return Imm >= 0 && Imm < (32*4) && ((Imm % 4) == 0); }],
                UImmS4XForm> {
  let ParserMatchClass = UImm5s4Operand;
  let PrintMethod = "printImmScale<4>";
}
def tuimm5s8 : Operand<i64>, TImmLeaf<i64,
                [{ return Imm >= 0 && Imm < (32*8) && ((Imm % 8) == 0); }],
                UImmS8XForm> {
  let ParserMatchClass = UImm5s8Operand;
  let PrintMethod = "printImmScale<8>";
}

// uimm6sN predicate - True if the immediate is a multiple of N in the range
// [0 * N, 64 * N].
def UImm6s1Operand : UImmScaledMemoryIndexed<6, 1>;
def UImm6s2Operand : UImmScaledMemoryIndexed<6, 2>;
def UImm6s4Operand : UImmScaledMemoryIndexed<6, 4>;
def UImm6s8Operand : UImmScaledMemoryIndexed<6, 8>;
def UImm6s16Operand : UImmScaledMemoryIndexed<6, 16>;

def uimm6s1 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
  let ParserMatchClass = UImm6s1Operand;
}
def uimm6s2 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >= 0 && Imm < (64*2) && ((Imm % 2) == 0); }]> {
  let PrintMethod = "printImmScale<2>";
  let ParserMatchClass = UImm6s2Operand;
}
def uimm6s4 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >= 0 && Imm < (64*4) && ((Imm % 4) == 0); }]> {
  let PrintMethod = "printImmScale<4>";
  let ParserMatchClass = UImm6s4Operand;
}
def uimm6s8 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >= 0 && Imm < (64*8) && ((Imm % 8) == 0); }]> {
  let PrintMethod = "printImmScale<8>";
  let ParserMatchClass = UImm6s8Operand;
}
def uimm6s16 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >= 0 && Imm < (64*16) && ((Imm % 16) == 0); }]> {
  let PrintMethod = "printImmScale<16>";
  let ParserMatchClass = UImm6s16Operand;
}

def SImmS2XForm : SDNodeXForm<imm, [{
  return CurDAG->getTargetConstant(N->getSExtValue() / 2, SDLoc(N), MVT::i64);
}]>;
def SImmS3XForm : SDNodeXForm<imm, [{
  return CurDAG->getTargetConstant(N->getSExtValue() / 3, SDLoc(N), MVT::i64);
}]>;
def SImmS4XForm : SDNodeXForm<imm, [{
  return CurDAG->getTargetConstant(N->getSExtValue() / 4, SDLoc(N), MVT::i64);
}]>;
def SImmS16XForm : SDNodeXForm<imm, [{
  return CurDAG->getTargetConstant(N->getSExtValue() / 16, SDLoc(N), MVT::i64);
}]>;
def SImmS32XForm : SDNodeXForm<imm, [{
  return CurDAG->getTargetConstant(N->getSExtValue() / 32, SDLoc(N), MVT::i64);
}]>;

// simm6sN predicate - True if the immediate is a multiple of N in the range
// [-32 * N, 31 * N].
def SImm6s1Operand : SImmScaledMemoryIndexed<6, 1>;
def simm6s1 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -32 && Imm < 32; }]> {
  let ParserMatchClass = SImm6s1Operand;
  let DecoderMethod = "DecodeSImm<6>";
}

// simm4sN predicate - True if the immediate is a multiple of N in the range
// [ -8* N, 7 * N].
def SImm4s1Operand  : SImmScaledMemoryIndexed<4, 1>;
def SImm4s2Operand  : SImmScaledMemoryIndexed<4, 2>;
def SImm4s3Operand  : SImmScaledMemoryIndexed<4, 3>;
def SImm4s4Operand  : SImmScaledMemoryIndexed<4, 4>;
def SImm4s16Operand : SImmScaledMemoryIndexed<4, 16>;
def SImm4s32Operand : SImmScaledMemoryIndexed<4, 32>;

def simm4s1 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >=-8  && Imm <= 7; }]> {
  let ParserMatchClass = SImm4s1Operand;
  let DecoderMethod = "DecodeSImm<4>";
}

def simm4s2 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >=-16  && Imm <= 14 && (Imm % 2) == 0x0; }], SImmS2XForm> {
  let PrintMethod = "printImmScale<2>";
  let ParserMatchClass = SImm4s2Operand;
  let DecoderMethod = "DecodeSImm<4>";
}

def simm4s3 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >=-24  && Imm <= 21 && (Imm % 3) == 0x0; }], SImmS3XForm> {
  let PrintMethod = "printImmScale<3>";
  let ParserMatchClass = SImm4s3Operand;
  let DecoderMethod = "DecodeSImm<4>";
}

def simm4s4 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >=-32  && Imm <= 28 && (Imm % 4) == 0x0; }], SImmS4XForm> {
  let PrintMethod = "printImmScale<4>";
  let ParserMatchClass = SImm4s4Operand;
  let DecoderMethod = "DecodeSImm<4>";
}
def simm4s16 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >=-128  && Imm <= 112 && (Imm % 16) == 0x0; }], SImmS16XForm> {
  let PrintMethod = "printImmScale<16>";
  let ParserMatchClass = SImm4s16Operand;
  let DecoderMethod = "DecodeSImm<4>";
}
def simm4s32 : Operand<i64>, ImmLeaf<i64,
[{ return Imm >=-256  && Imm <= 224 && (Imm % 32) == 0x0; }], SImmS32XForm> {
  let PrintMethod = "printImmScale<32>";
  let ParserMatchClass = SImm4s32Operand;
  let DecoderMethod = "DecodeSImm<4>";
}

def Imm1_8Operand : AsmImmRange<1, 8>;
def Imm1_16Operand : AsmImmRange<1, 16>;
def Imm1_32Operand : AsmImmRange<1, 32>;
def Imm1_64Operand : AsmImmRange<1, 64>;

class BranchTarget<int N> : AsmOperandClass {
  let Name = "BranchTarget" # N;
  let DiagnosticType = "InvalidLabel";
  let PredicateMethod = "isBranchTarget<" # N # ">";
}

class PCRelLabel<int N> : BranchTarget<N> {
  let Name = "PCRelLabel" # N;
}

def BranchTarget14Operand : BranchTarget<14>;
def BranchTarget26Operand : BranchTarget<26>;
def PCRelLabel19Operand   : PCRelLabel<19>;

def MovWSymbolG3AsmOperand : AsmOperandClass {
  let Name = "MovWSymbolG3";
  let RenderMethod = "addImmOperands";
}

def movw_symbol_g3 : Operand<i32> {
  let ParserMatchClass = MovWSymbolG3AsmOperand;
}

def MovWSymbolG2AsmOperand : AsmOperandClass {
  let Name = "MovWSymbolG2";
  let RenderMethod = "addImmOperands";
}

def movw_symbol_g2 : Operand<i32> {
  let ParserMatchClass = MovWSymbolG2AsmOperand;
}

def MovWSymbolG1AsmOperand : AsmOperandClass {
  let Name = "MovWSymbolG1";
  let RenderMethod = "addImmOperands";
}

def movw_symbol_g1 : Operand<i32> {
  let ParserMatchClass = MovWSymbolG1AsmOperand;
}

def MovWSymbolG0AsmOperand : AsmOperandClass {
  let Name = "MovWSymbolG0";
  let RenderMethod = "addImmOperands";
}

def movw_symbol_g0 : Operand<i32> {
  let ParserMatchClass = MovWSymbolG0AsmOperand;
}

class fixedpoint_i32<ValueType FloatVT>
  : Operand<FloatVT>,
    ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm, ld]> {
  let EncoderMethod = "getFixedPointScaleOpValue";
  let DecoderMethod = "DecodeFixedPointScaleImm32";
  let ParserMatchClass = Imm1_32Operand;
}

class fixedpoint_i64<ValueType FloatVT>
  : Operand<FloatVT>,
    ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm, ld]> {
  let EncoderMethod = "getFixedPointScaleOpValue";
  let DecoderMethod = "DecodeFixedPointScaleImm64";
  let ParserMatchClass = Imm1_64Operand;
}

def fixedpoint_f16_i32 : fixedpoint_i32<f16>;
def fixedpoint_f32_i32 : fixedpoint_i32<f32>;
def fixedpoint_f64_i32 : fixedpoint_i32<f64>;

def fixedpoint_f16_i64 : fixedpoint_i64<f16>;
def fixedpoint_f32_i64 : fixedpoint_i64<f32>;
def fixedpoint_f64_i64 : fixedpoint_i64<f64>;

def vecshiftR8 : Operand<i32>, ImmLeaf<i32, [{
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
}]> {
  let EncoderMethod = "getVecShiftR8OpValue";
  let DecoderMethod = "DecodeVecShiftR8Imm";
  let ParserMatchClass = Imm1_8Operand;
}
def vecshiftR16 : Operand<i32>, ImmLeaf<i32, [{
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
}]> {
  let EncoderMethod = "getVecShiftR16OpValue";
  let DecoderMethod = "DecodeVecShiftR16Imm";
  let ParserMatchClass = Imm1_16Operand;
}
def vecshiftR16Narrow : Operand<i32>, ImmLeaf<i32, [{
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
}]> {
  let EncoderMethod = "getVecShiftR16OpValue";
  let DecoderMethod = "DecodeVecShiftR16ImmNarrow";
  let ParserMatchClass = Imm1_8Operand;
}
def vecshiftR32 : Operand<i32>, ImmLeaf<i32, [{
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
}]> {
  let EncoderMethod = "getVecShiftR32OpValue";
  let DecoderMethod = "DecodeVecShiftR32Imm";
  let ParserMatchClass = Imm1_32Operand;
}
def vecshiftR32Narrow : Operand<i32>, ImmLeaf<i32, [{
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
}]> {
  let EncoderMethod = "getVecShiftR32OpValue";
  let DecoderMethod = "DecodeVecShiftR32ImmNarrow";
  let ParserMatchClass = Imm1_16Operand;
}
def vecshiftR64 : Operand<i32>, ImmLeaf<i32, [{
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
}]> {
  let EncoderMethod = "getVecShiftR64OpValue";
  let DecoderMethod = "DecodeVecShiftR64Imm";
  let ParserMatchClass = Imm1_64Operand;
}
def vecshiftR64Narrow : Operand<i32>, ImmLeaf<i32, [{
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
}]> {
  let EncoderMethod = "getVecShiftR64OpValue";
  let DecoderMethod = "DecodeVecShiftR64ImmNarrow";
  let ParserMatchClass = Imm1_32Operand;
}

// Same as vecshiftR#N, but use TargetConstant (TimmLeaf) instead of Constant
// (ImmLeaf)
def tvecshiftR8 : Operand<i32>, TImmLeaf<i32, [{
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 9);
}]> {
  let EncoderMethod = "getVecShiftR8OpValue";
  let DecoderMethod = "DecodeVecShiftR8Imm";
  let ParserMatchClass = Imm1_8Operand;
}
def tvecshiftR16 : Operand<i32>, TImmLeaf<i32, [{
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 17);
}]> {
  let EncoderMethod = "getVecShiftR16OpValue";
  let DecoderMethod = "DecodeVecShiftR16Imm";
  let ParserMatchClass = Imm1_16Operand;
}
def tvecshiftR32 : Operand<i32>, TImmLeaf<i32, [{
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 33);
}]> {
  let EncoderMethod = "getVecShiftR32OpValue";
  let DecoderMethod = "DecodeVecShiftR32Imm";
  let ParserMatchClass = Imm1_32Operand;
}
def tvecshiftR64 : Operand<i32>, TImmLeaf<i32, [{
  return (((uint32_t)Imm) > 0) && (((uint32_t)Imm) < 65);
}]> {
  let EncoderMethod = "getVecShiftR64OpValue";
  let DecoderMethod = "DecodeVecShiftR64Imm";
  let ParserMatchClass = Imm1_64Operand;
}

def Imm0_0Operand : AsmImmRange<0, 0>;
def Imm0_1Operand : AsmImmRange<0, 1>;
def Imm0_3Operand : AsmImmRange<0, 3>;
def Imm0_7Operand : AsmImmRange<0, 7>;
def Imm0_15Operand : AsmImmRange<0, 15>;
def Imm0_31Operand : AsmImmRange<0, 31>;
def Imm0_63Operand : AsmImmRange<0, 63>;

def vecshiftL8 : Operand<i32>, ImmLeaf<i32, [{
  return (((uint32_t)Imm) < 8);
}]> {
  let EncoderMethod = "getVecShiftL8OpValue";
  let DecoderMethod = "DecodeVecShiftL8Imm";
  let ParserMatchClass = Imm0_7Operand;
}
def vecshiftL16 : Operand<i32>, ImmLeaf<i32, [{
  return (((uint32_t)Imm) < 16);
}]> {
  let EncoderMethod = "getVecShiftL16OpValue";
  let DecoderMethod = "DecodeVecShiftL16Imm";
  let ParserMatchClass = Imm0_15Operand;
}
def vecshiftL32 : Operand<i32>, ImmLeaf<i32, [{
  return (((uint32_t)Imm) < 32);
}]> {
  let EncoderMethod = "getVecShiftL32OpValue";
  let DecoderMethod = "DecodeVecShiftL32Imm";
  let ParserMatchClass = Imm0_31Operand;
}
def vecshiftL64 : Operand<i32>, ImmLeaf<i32, [{
  return (((uint32_t)Imm) < 64);
}]> {
  let EncoderMethod = "getVecShiftL64OpValue";
  let DecoderMethod = "DecodeVecShiftL64Imm";
  let ParserMatchClass = Imm0_63Operand;
}

// Same as vecshiftL#N, but use TargetConstant (TimmLeaf) instead of Constant
// (ImmLeaf)
def tvecshiftL8 : Operand<i32>, TImmLeaf<i32, [{
  return (((uint32_t)Imm) < 8);
}]> {
  let EncoderMethod = "getVecShiftL8OpValue";
  let DecoderMethod = "DecodeVecShiftL8Imm";
  let ParserMatchClass = Imm0_7Operand;
}
def tvecshiftL16 : Operand<i32>, TImmLeaf<i32, [{
  return (((uint32_t)Imm) < 16);
}]> {
  let EncoderMethod = "getVecShiftL16OpValue";
  let DecoderMethod = "DecodeVecShiftL16Imm";
  let ParserMatchClass = Imm0_15Operand;
}
def tvecshiftL32 : Operand<i32>, TImmLeaf<i32, [{
  return (((uint32_t)Imm) < 32);
}]> {
  let EncoderMethod = "getVecShiftL32OpValue";
  let DecoderMethod = "DecodeVecShiftL32Imm";
  let ParserMatchClass = Imm0_31Operand;
}
def tvecshiftL64 : Operand<i32>, TImmLeaf<i32, [{
  return (((uint32_t)Imm) < 64);
}]> {
  let EncoderMethod = "getVecShiftL64OpValue";
  let DecoderMethod = "DecodeVecShiftL64Imm";
  let ParserMatchClass = Imm0_63Operand;
}

// Crazy immediate formats used by 32-bit and 64-bit logical immediate
// instructions for splatting repeating bit patterns across the immediate.
def logical_imm32_XFORM : SDNodeXForm<imm, [{
  uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 32);
  return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
}]>;
def logical_imm64_XFORM : SDNodeXForm<imm, [{
  uint64_t enc = AArch64_AM::encodeLogicalImmediate(N->getZExtValue(), 64);
  return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
}]>;

def gi_logical_imm32_XFORM : GICustomOperandRenderer<"renderLogicalImm32">,
  GISDNodeXFormEquiv<logical_imm32_XFORM>;
def gi_logical_imm64_XFORM : GICustomOperandRenderer<"renderLogicalImm64">,
  GISDNodeXFormEquiv<logical_imm64_XFORM>;

let DiagnosticType = "LogicalSecondSource" in {
  def LogicalImm32Operand : AsmOperandClass {
    let Name = "LogicalImm32";
    let PredicateMethod = "isLogicalImm<int32_t>";
    let RenderMethod = "addLogicalImmOperands<int32_t>";
  }
  def LogicalImm64Operand : AsmOperandClass {
    let Name = "LogicalImm64";
    let PredicateMethod = "isLogicalImm<int64_t>";
    let RenderMethod = "addLogicalImmOperands<int64_t>";
  }
  def LogicalImm32NotOperand : AsmOperandClass {
    let Name = "LogicalImm32Not";
    let PredicateMethod = "isLogicalImm<int32_t>";
    let RenderMethod = "addLogicalImmNotOperands<int32_t>";
  }
  def LogicalImm64NotOperand : AsmOperandClass {
    let Name = "LogicalImm64Not";
    let PredicateMethod = "isLogicalImm<int64_t>";
    let RenderMethod = "addLogicalImmNotOperands<int64_t>";
  }
}
def logical_imm32 : Operand<i32>, IntImmLeaf<i32, [{
  return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 32);
}], logical_imm32_XFORM> {
  let PrintMethod = "printLogicalImm<int32_t>";
  let ParserMatchClass = LogicalImm32Operand;
}
def logical_imm64 : Operand<i64>, IntImmLeaf<i64, [{
  return AArch64_AM::isLogicalImmediate(Imm.getZExtValue(), 64);
}], logical_imm64_XFORM> {
  let PrintMethod = "printLogicalImm<int64_t>";
  let ParserMatchClass = LogicalImm64Operand;
}
def logical_imm32_not : Operand<i32> {
  let ParserMatchClass = LogicalImm32NotOperand;
}
def logical_imm64_not : Operand<i64> {
  let ParserMatchClass = LogicalImm64NotOperand;
}

// immXX_0_65535 predicates - True if the immediate is in the range [0,65535].
let ParserMatchClass = AsmImmRange<0, 65535>, PrintMethod = "printImmHex" in {
def timm32_0_65535 : Operand<i32>, TImmLeaf<i32, [{
  return ((uint32_t)Imm) < 65536;
}]>;

def timm64_0_65535 : Operand<i64>, TImmLeaf<i64, [{
  return ((uint64_t)Imm) < 65536;
}]>;
}

// imm0_255 predicate - True if the immediate is in the range [0,255].
def Imm0_255Operand : AsmImmRange<0,255>;

def imm0_255 : Operand<i32>, ImmLeaf<i32, [{
  return ((uint32_t)Imm) < 256;
}]> {
  let ParserMatchClass = Imm0_255Operand;
  let PrintMethod = "printImm";
}

// imm0_127 predicate - True if the immediate is in the range [0,127]
def Imm0_127Operand : AsmImmRange<0, 127>;
def imm0_127 : Operand<i32>, ImmLeaf<i32, [{
  return ((uint32_t)Imm) < 128;
}]> {
  let ParserMatchClass = Imm0_127Operand;
  let PrintMethod = "printImm";
}

def imm0_127_64b : Operand<i64>, ImmLeaf<i64, [{
  return ((uint64_t)Imm) < 128;
}]> {
  let ParserMatchClass = Imm0_127Operand;
  let PrintMethod = "printImm";
}

// NOTE: These imm0_N operands have to be of type i64 because i64 is the size
// for all shift-amounts.

// imm0_63 predicate - True if the immediate is in the range [0,63]
def imm0_63 : Operand<i64>, ImmLeaf<i64, [{
  return ((uint64_t)Imm) < 64;
}]> {
  let ParserMatchClass = Imm0_63Operand;
}

def timm0_63 : Operand<i64>, TImmLeaf<i64, [{
  return ((uint64_t)Imm) < 64;
}]> {
  let ParserMatchClass = Imm0_63Operand;
}

// imm0_31 predicate - True if the immediate is in the range [0,31]
def imm0_31 : Operand<i64>, ImmLeaf<i64, [{
  return ((uint64_t)Imm) < 32;
}]> {
  let ParserMatchClass = Imm0_31Operand;
}

// timm0_31 predicate - same ass imm0_31, but use TargetConstant (TimmLeaf)
// instead of Constant (ImmLeaf)
def timm0_31 : Operand<i64>, TImmLeaf<i64, [{
  return ((uint64_t)Imm) < 32;
}]> {
  let ParserMatchClass = Imm0_31Operand;
}

// True if the 32-bit immediate is in the range [0,31]
def imm32_0_31 : Operand<i32>, ImmLeaf<i32, [{
  return ((uint64_t)Imm) < 32;
}]> {
  let ParserMatchClass = Imm0_31Operand;
}

// imm0_1 predicate - True if the immediate is in the range [0,1]
def imm0_1 : Operand<i64>, ImmLeaf<i64, [{
  return ((uint64_t)Imm) < 2;
}]> {
  let ParserMatchClass = Imm0_1Operand;
}

// timm0_1 - as above, but use TargetConstant (TImmLeaf)
def timm0_1 : Operand<i64>, TImmLeaf<i64, [{
  return ((uint64_t)Imm) < 2;
}]> {
  let ParserMatchClass = Imm0_1Operand;
}

// imm0_15 predicate - True if the immediate is in the range [0,15]
def imm0_15 : Operand<i64>, ImmLeaf<i64, [{
  return ((uint64_t)Imm) < 16;
}]> {
  let ParserMatchClass = Imm0_15Operand;
}

// imm0_7 predicate - True if the immediate is in the range [0,7]
def imm0_7 : Operand<i64>, ImmLeaf<i64, [{
  return ((uint64_t)Imm) < 8;
}]> {
  let ParserMatchClass = Imm0_7Operand;
}

// imm0_3 predicate - True if the immediate is in the range [0,3]
def imm0_3 : Operand<i64>, ImmLeaf<i64, [{
  return ((uint64_t)Imm) < 4;
}]> {
  let ParserMatchClass = Imm0_3Operand;
}

// timm32_0_7 predicate - True if the 32-bit immediate is in the range [0,7]
def timm32_0_7 : Operand<i32>, TImmLeaf<i32, [{
  return ((uint32_t)Imm) < 8;
}]> {
  let ParserMatchClass = Imm0_7Operand;
}

// imm32_0_15 predicate - True if the 32-bit immediate is in the range [0,15]
def imm32_0_15 : Operand<i32>, ImmLeaf<i32, [{
  return ((uint32_t)Imm) < 16;
}]> {
  let ParserMatchClass = Imm0_15Operand;
}

// An arithmetic shifter operand:
//  {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr
//  {5-0} - imm6
class arith_shift<ValueType Ty, int width> : Operand<Ty> {
  let PrintMethod = "printShifter";
  let ParserMatchClass = !cast<AsmOperandClass>(
                         "ArithmeticShifterOperand" # width);
}

def arith_shift32 : arith_shift<i32, 32>;
def arith_shift64 : arith_shift<i64, 64>;

class arith_shifted_reg<ValueType Ty, RegisterClass regclass, int width>
    : Operand<Ty>,
      ComplexPattern<Ty, 2, "SelectArithShiftedRegister", []> {
  let PrintMethod = "printShiftedRegister";
  let MIOperandInfo = (ops regclass, !cast<Operand>("arith_shift" # width));
}

def arith_shifted_reg32 : arith_shifted_reg<i32, GPR32, 32>;
def arith_shifted_reg64 : arith_shifted_reg<i64, GPR64, 64>;

def gi_arith_shifted_reg32 :
  GIComplexOperandMatcher<s32, "selectArithShiftedRegister">,
  GIComplexPatternEquiv<arith_shifted_reg32>;

def gi_arith_shifted_reg64 :
  GIComplexOperandMatcher<s64, "selectArithShiftedRegister">,
  GIComplexPatternEquiv<arith_shifted_reg64>;

// An arithmetic shifter operand:
//  {7-6} - shift type: 00 = lsl, 01 = lsr, 10 = asr, 11 = ror
//  {5-0} - imm6
class logical_shift<int width> : Operand<i32> {
  let PrintMethod = "printShifter";
  let ParserMatchClass = !cast<AsmOperandClass>(
                         "LogicalShifterOperand" # width);
}

def logical_shift32 : logical_shift<32>;
def logical_shift64 : logical_shift<64>;

class logical_shifted_reg<ValueType Ty, RegisterClass regclass, Operand shiftop>
    : Operand<Ty>,
      ComplexPattern<Ty, 2, "SelectLogicalShiftedRegister", []> {
  let PrintMethod = "printShiftedRegister";
  let MIOperandInfo = (ops regclass, shiftop);
}

def logical_shifted_reg32 : logical_shifted_reg<i32, GPR32, logical_shift32>;
def logical_shifted_reg64 : logical_shifted_reg<i64, GPR64, logical_shift64>;

def gi_logical_shifted_reg32 :
  GIComplexOperandMatcher<s32, "selectLogicalShiftedRegister">,
  GIComplexPatternEquiv<logical_shifted_reg32>;

def gi_logical_shifted_reg64 :
  GIComplexOperandMatcher<s64, "selectLogicalShiftedRegister">,
  GIComplexPatternEquiv<logical_shifted_reg64>;

// A logical vector shifter operand:
//  {7-6} - shift type: 00 = lsl
//  {5-0} - imm6: #0, #8, #16, or #24
def logical_vec_shift : Operand<i32> {
  let PrintMethod = "printShifter";
  let EncoderMethod = "getVecShifterOpValue";
  let ParserMatchClass = LogicalVecShifterOperand;
}

// A logical vector half-word shifter operand:
//  {7-6} - shift type: 00 = lsl
//  {5-0} - imm6: #0 or #8
def logical_vec_hw_shift : Operand<i32> {
  let PrintMethod = "printShifter";
  let EncoderMethod = "getVecShifterOpValue";
  let ParserMatchClass = LogicalVecHalfWordShifterOperand;
}

// A vector move shifter operand:
//  {0} - imm1: #8 or #16
def move_vec_shift : Operand<i32> {
  let PrintMethod = "printShifter";
  let EncoderMethod = "getMoveVecShifterOpValue";
  let ParserMatchClass = MoveVecShifterOperand;
}

let DiagnosticType = "AddSubSecondSource" in {
  def AddSubImmOperand : AsmOperandClass {
    let Name = "AddSubImm";
    let ParserMethod = "tryParseImmWithOptionalShift";
    let RenderMethod = "addImmWithOptionalShiftOperands<12>";
  }
  def AddSubImmNegOperand : AsmOperandClass {
    let Name = "AddSubImmNeg";
    let ParserMethod = "tryParseImmWithOptionalShift";
    let RenderMethod = "addImmNegWithOptionalShiftOperands<12>";
  }
}
// An ADD/SUB immediate shifter operand:
//  second operand:
//  {7-6} - shift type: 00 = lsl
//  {5-0} - imm6: #0 or #12
class addsub_shifted_imm<ValueType Ty>
    : Operand<Ty>, ComplexPattern<Ty, 2, "SelectArithImmed", [imm]> {
  let PrintMethod = "printAddSubImm";
  let EncoderMethod = "getAddSubImmOpValue";
  let ParserMatchClass = AddSubImmOperand;
  let MIOperandInfo = (ops i32imm, i32imm);
}

class addsub_shifted_imm_neg<ValueType Ty>
    : Operand<Ty> {
  let EncoderMethod = "getAddSubImmOpValue";
  let ParserMatchClass = AddSubImmNegOperand;
  let MIOperandInfo = (ops i32imm, i32imm);
}

def addsub_shifted_imm32 : addsub_shifted_imm<i32>;
def addsub_shifted_imm64 : addsub_shifted_imm<i64>;
def addsub_shifted_imm32_neg : addsub_shifted_imm_neg<i32>;
def addsub_shifted_imm64_neg : addsub_shifted_imm_neg<i64>;

def gi_addsub_shifted_imm32 :
    GIComplexOperandMatcher<s32, "selectArithImmed">,
    GIComplexPatternEquiv<addsub_shifted_imm32>;

def gi_addsub_shifted_imm64 :
    GIComplexOperandMatcher<s64, "selectArithImmed">,
    GIComplexPatternEquiv<addsub_shifted_imm64>;

class neg_addsub_shifted_imm<ValueType Ty>
    : Operand<Ty>, ComplexPattern<Ty, 2, "SelectNegArithImmed", [imm]> {
  let PrintMethod = "printAddSubImm";
  let EncoderMethod = "getAddSubImmOpValue";
  let ParserMatchClass = AddSubImmOperand;
  let MIOperandInfo = (ops i32imm, i32imm);
}

def neg_addsub_shifted_imm32 : neg_addsub_shifted_imm<i32>;
def neg_addsub_shifted_imm64 : neg_addsub_shifted_imm<i64>;

def gi_neg_addsub_shifted_imm32 :
    GIComplexOperandMatcher<s32, "selectNegArithImmed">,
    GIComplexPatternEquiv<neg_addsub_shifted_imm32>;

def gi_neg_addsub_shifted_imm64 :
    GIComplexOperandMatcher<s64, "selectNegArithImmed">,
    GIComplexPatternEquiv<neg_addsub_shifted_imm64>;

// An extend operand:
//  {5-3} - extend type
//  {2-0} - imm3
def arith_extend : Operand<i32> {
  let PrintMethod = "printArithExtend";
  let ParserMatchClass = ExtendOperand;
}
def arith_extend64 : Operand<i32> {
  let PrintMethod = "printArithExtend";
  let ParserMatchClass = ExtendOperand64;
}

// 'extend' that's a lsl of a 64-bit register.
def arith_extendlsl64 : Operand<i32> {
  let PrintMethod = "printArithExtend";
  let ParserMatchClass = ExtendOperandLSL64;
}

class arith_extended_reg32<ValueType Ty> : Operand<Ty>,
                    ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
  let PrintMethod = "printExtendedRegister";
  let MIOperandInfo = (ops GPR32, arith_extend);
}

class arith_extended_reg32to64<ValueType Ty> : Operand<Ty>,
                    ComplexPattern<Ty, 2, "SelectArithExtendedRegister", []> {
  let PrintMethod = "printExtendedRegister";
  let MIOperandInfo = (ops GPR32, arith_extend64);
}

def arith_extended_reg32_i32 : arith_extended_reg32<i32>;
def gi_arith_extended_reg32_i32 :
    GIComplexOperandMatcher<s32, "selectArithExtendedRegister">,
    GIComplexPatternEquiv<arith_extended_reg32_i32>;

def arith_extended_reg32_i64 : arith_extended_reg32<i64>;
def gi_arith_extended_reg32_i64 :
    GIComplexOperandMatcher<s64, "selectArithExtendedRegister">,
    GIComplexPatternEquiv<arith_extended_reg32_i64>;

def arith_extended_reg32to64_i64 : arith_extended_reg32to64<i64>;
def gi_arith_extended_reg32to64_i64 :
    GIComplexOperandMatcher<s64, "selectArithExtendedRegister">,
    GIComplexPatternEquiv<arith_extended_reg32to64_i64>;

// Floating-point immediate.

def fpimm16XForm : SDNodeXForm<fpimm, [{
      APFloat InVal = N->getValueAPF();
      uint32_t enc = AArch64_AM::getFP16Imm(InVal);
      return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
    }]>;

def fpimm32XForm : SDNodeXForm<fpimm, [{
      APFloat InVal = N->getValueAPF();
      uint32_t enc = AArch64_AM::getFP32Imm(InVal);
      return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
    }]>;

def fpimm64XForm : SDNodeXForm<fpimm, [{
      APFloat InVal = N->getValueAPF();
      uint32_t enc = AArch64_AM::getFP64Imm(InVal);
      return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
    }]>;

def fpimm16 : Operand<f16>,
              FPImmLeaf<f16, [{
      return AArch64_AM::getFP16Imm(Imm) != -1;
    }], fpimm16XForm> {
  let ParserMatchClass = FPImmOperand;
  let PrintMethod = "printFPImmOperand";
}

def fpimm32 : Operand<f32>,
              FPImmLeaf<f32, [{
      return AArch64_AM::getFP32Imm(Imm) != -1;
    }], fpimm32XForm> {
  let ParserMatchClass = FPImmOperand;
  let PrintMethod = "printFPImmOperand";
}
def fpimm64 : Operand<f64>,
              FPImmLeaf<f64, [{
      return AArch64_AM::getFP64Imm(Imm) != -1;
    }], fpimm64XForm> {
  let ParserMatchClass = FPImmOperand;
  let PrintMethod = "printFPImmOperand";
}

def fpimm8 : Operand<i32> {
  let ParserMatchClass = FPImmOperand;
  let PrintMethod = "printFPImmOperand";
}

def fpimm0 : FPImmLeaf<fAny, [{
  return Imm.isExactlyValue(+0.0);
}]>;

def fpimm_half : FPImmLeaf<fAny, [{
  return Imm.isExactlyValue(+0.5);
}]>;

def fpimm_one : FPImmLeaf<fAny, [{
  return Imm.isExactlyValue(+1.0);
}]>;

def fpimm_two : FPImmLeaf<fAny, [{
  return Imm.isExactlyValue(+2.0);
}]>;

def gi_fpimm16 : GICustomOperandRenderer<"renderFPImm16">,
  GISDNodeXFormEquiv<fpimm16XForm>;
def gi_fpimm32 : GICustomOperandRenderer<"renderFPImm32">,
  GISDNodeXFormEquiv<fpimm32XForm>;
def gi_fpimm64 : GICustomOperandRenderer<"renderFPImm64">,
  GISDNodeXFormEquiv<fpimm64XForm>;

// Vector lane operands
class AsmVectorIndex<int Min, int Max, string NamePrefix=""> : AsmOperandClass {
  let Name = NamePrefix # "IndexRange" # Min # "_" # Max;
  let DiagnosticType = "Invalid" # Name;
  let PredicateMethod = "isVectorIndex<" # Min # ", " # Max #  ">";
  let RenderMethod = "addVectorIndexOperands";
}

class AsmVectorIndexOpnd<ValueType ty, AsmOperandClass mc>
    : Operand<ty> {
  let ParserMatchClass = mc;
  let PrintMethod = "printVectorIndex";
}

multiclass VectorIndex<ValueType ty, AsmOperandClass mc, code pred> {
  def "" : AsmVectorIndexOpnd<ty, mc>, ImmLeaf<ty, pred>;
  def _timm : AsmVectorIndexOpnd<ty, mc>, TImmLeaf<ty, pred>;
}

def VectorIndex0Operand : AsmVectorIndex<0, 0>;
def VectorIndex1Operand : AsmVectorIndex<1, 1>;
def VectorIndexBOperand : AsmVectorIndex<0, 15>;
def VectorIndexHOperand : AsmVectorIndex<0, 7>;
def VectorIndexSOperand : AsmVectorIndex<0, 3>;
def VectorIndexDOperand : AsmVectorIndex<0, 1>;

defm VectorIndex0 : VectorIndex<i64, VectorIndex0Operand,
                                [{ return ((uint64_t)Imm) == 0; }]>;
defm VectorIndex1 : VectorIndex<i64, VectorIndex1Operand,
                                [{ return ((uint64_t)Imm) == 1; }]>;
defm VectorIndexB : VectorIndex<i64, VectorIndexBOperand,
                                [{ return ((uint64_t)Imm) < 16; }]>;
defm VectorIndexH : VectorIndex<i64, VectorIndexHOperand,
                                [{ return ((uint64_t)Imm) < 8; }]>;
defm VectorIndexS : VectorIndex<i64, VectorIndexSOperand,
                                [{ return ((uint64_t)Imm) < 4; }]>;
defm VectorIndexD : VectorIndex<i64, VectorIndexDOperand,
                                [{ return ((uint64_t)Imm) < 2; }]>;

defm VectorIndex132b : VectorIndex<i32, VectorIndex1Operand,
                                   [{ return ((uint64_t)Imm) == 1; }]>;
defm VectorIndexB32b : VectorIndex<i32, VectorIndexBOperand,
                                   [{ return ((uint64_t)Imm) < 16; }]>;
defm VectorIndexH32b : VectorIndex<i32, VectorIndexHOperand,
                                   [{ return ((uint64_t)Imm) < 8; }]>;
defm VectorIndexS32b : VectorIndex<i32, VectorIndexSOperand,
                                   [{ return ((uint64_t)Imm) < 4; }]>;
defm VectorIndexD32b : VectorIndex<i32, VectorIndexDOperand,
                                   [{ return ((uint64_t)Imm) < 2; }]>;

def SVEVectorIndexExtDupBOperand : AsmVectorIndex<0, 63, "SVE">;
def SVEVectorIndexExtDupHOperand : AsmVectorIndex<0, 31, "SVE">;
def SVEVectorIndexExtDupSOperand : AsmVectorIndex<0, 15, "SVE">;
def SVEVectorIndexExtDupDOperand : AsmVectorIndex<0, 7, "SVE">;
def SVEVectorIndexExtDupQOperand : AsmVectorIndex<0, 3, "SVE">;

defm sve_elm_idx_extdup_b
  : VectorIndex<i64, SVEVectorIndexExtDupBOperand,
                [{ return ((uint64_t)Imm) < 64; }]>;
defm sve_elm_idx_extdup_h
  : VectorIndex<i64, SVEVectorIndexExtDupHOperand,
                [{ return ((uint64_t)Imm) < 32; }]>;
defm sve_elm_idx_extdup_s
  : VectorIndex<i64, SVEVectorIndexExtDupSOperand,
                [{ return ((uint64_t)Imm) < 16; }]>;
defm sve_elm_idx_extdup_d
  : VectorIndex<i64, SVEVectorIndexExtDupDOperand,
                [{ return ((uint64_t)Imm) < 8; }]>;
defm sve_elm_idx_extdup_q
  : VectorIndex<i64, SVEVectorIndexExtDupQOperand,
                [{ return ((uint64_t)Imm) < 4; }]>;

def sme_elm_idx0_0 : Operand<i64>, ImmLeaf<i64, [{
  return ((uint64_t)Imm) == 0;
}]> {
  let ParserMatchClass = Imm0_0Operand;
  let PrintMethod = "printMatrixIndex";
}
def sme_elm_idx0_1 : Operand<i64>, ImmLeaf<i64, [{
  return ((uint64_t)Imm) <= 1;
}]> {
  let ParserMatchClass = Imm0_1Operand;
  let PrintMethod = "printMatrixIndex";
}
def sme_elm_idx0_3 : Operand<i64>, ImmLeaf<i64, [{
  return ((uint64_t)Imm) <= 3;
}]> {
  let ParserMatchClass = Imm0_3Operand;
  let PrintMethod = "printMatrixIndex";
}
def sme_elm_idx0_7 : Operand<i64>, ImmLeaf<i64, [{
  return ((uint64_t)Imm) <= 7;
}]> {
  let ParserMatchClass = Imm0_7Operand;
  let PrintMethod = "printMatrixIndex";
}
def sme_elm_idx0_15 : Operand<i64>, ImmLeaf<i64, [{
  return ((uint64_t)Imm) <= 15;
}]> {
  let ParserMatchClass = Imm0_15Operand;
  let PrintMethod = "printMatrixIndex";
}

// 8-bit immediate for AdvSIMD where 64-bit values of the form:
// aaaaaaaa bbbbbbbb cccccccc dddddddd eeeeeeee ffffffff gggggggg hhhhhhhh
// are encoded as the eight bit value 'abcdefgh'.
def simdimmtype10 : Operand<i32>,
                    FPImmLeaf<f64, [{
      return AArch64_AM::isAdvSIMDModImmType10(
                 Imm.bitcastToAPInt().getZExtValue());
    }], SDNodeXForm<fpimm, [{
      APFloat InVal = N->getValueAPF();
      uint32_t enc = AArch64_AM::encodeAdvSIMDModImmType10(N->getValueAPF()
                                                           .bitcastToAPInt()
                                                           .getZExtValue());
      return CurDAG->getTargetConstant(enc, SDLoc(N), MVT::i32);
    }]>> {
  let ParserMatchClass = SIMDImmType10Operand;
  let PrintMethod = "printSIMDType10Operand";
}


//---
// System management
//---

// Base encoding for system instruction operands.
let mayLoad = 0, mayStore = 0, hasSideEffects = 1 in
class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands,
                  list<dag> pattern = []>
    : I<oops, iops, asm, operands, "", pattern> {
  let Inst{31-22} = 0b1101010100;
  let Inst{21}    = L;
}

// System instructions which do not have an Rt register.
class SimpleSystemI<bit L, dag iops, string asm, string operands,
                    list<dag> pattern = []>
    : BaseSystemI<L, (outs), iops, asm, operands, pattern> {
  let Inst{4-0} = 0b11111;
}

// System instructions which have an Rt register.
class RtSystemI<bit L, dag oops, dag iops, string asm, string operands,
                list<dag> pattern = []>
    : BaseSystemI<L, oops, iops, asm, operands, pattern>,
      Sched<[WriteSys]> {
  bits<5> Rt;
  let Inst{4-0} = Rt;
}

// System instructions for transactional memory extension
class TMBaseSystemI<bit L, bits<4> CRm, bits<3> op2, dag oops, dag iops,
                    string asm, string operands, list<dag> pattern>
    : BaseSystemI<L, oops, iops, asm, operands, pattern>,
      Sched<[WriteSys]> {
  let Inst{20-12} = 0b000110011;
  let Inst{11-8} = CRm;
  let Inst{7-5} = op2;
  let DecoderMethod = "";

  let mayLoad = 1;
  let mayStore = 1;
}

// System instructions for transactional memory - single input operand
class TMSystemI<bits<4> CRm, string asm, list<dag> pattern>
    : TMBaseSystemI<0b1, CRm, 0b011,
                    (outs GPR64:$Rt), (ins), asm, "\t$Rt", pattern> {
  bits<5> Rt;
  let Inst{4-0} = Rt;
}

// System instructions that pass a register argument
// This class assumes the register is for input rather than output.
class RegInputSystemI<bits<4> CRm, bits<3> Op2, string asm,
                      list<dag> pattern = []>
    : RtSystemI<0, (outs), (ins GPR64:$Rt), asm, "\t$Rt", pattern> {
  let Inst{20-12} = 0b000110001;
  let Inst{11-8} = CRm;
  let Inst{7-5} = Op2;
}

// System instructions for transactional memory - no operand
class TMSystemINoOperand<bits<4> CRm, string asm, list<dag> pattern>
    : TMBaseSystemI<0b0, CRm, 0b011, (outs), (ins), asm, "", pattern> {
  let Inst{4-0} = 0b11111;
}

// System instructions for exit from transactions
class TMSystemException<bits<3> op1, string asm, list<dag> pattern>
    : I<(outs), (ins timm64_0_65535:$imm), asm, "\t$imm", "", pattern>,
      Sched<[WriteSys]> {
  bits<16> imm;
  let Inst{31-24} = 0b11010100;
  let Inst{23-21} = op1;
  let Inst{20-5}  = imm;
  let Inst{4-0}   = 0b00000;
}

// Hint instructions that take both a CRm and a 3-bit immediate.
// NOTE: ideally, this would have mayStore = 0, mayLoad = 0, but we cannot
// model patterns with sufficiently fine granularity
let mayStore = 1, mayLoad = 1, hasSideEffects = 1 in
  class HintI<string mnemonic>
      : SimpleSystemI<0, (ins imm0_127:$imm), mnemonic#"\t$imm", "",
                      [(int_aarch64_hint imm0_127:$imm)]>,
        Sched<[WriteHint]> {
    bits <7> imm;
    let Inst{20-12} = 0b000110010;
    let Inst{11-5} = imm;
  }

// System instructions taking a single literal operand which encodes into
// CRm. op2 differentiates the opcodes.
def BarrierAsmOperand : AsmOperandClass {
  let Name = "Barrier";
  let ParserMethod = "tryParseBarrierOperand";
}
def barrier_op : Operand<i32> {
  let PrintMethod = "printBarrierOption";
  let ParserMatchClass = BarrierAsmOperand;
}
def BarriernXSAsmOperand : AsmOperandClass {
  let Name = "BarriernXS";
  let ParserMethod = "tryParseBarriernXSOperand";
}
def barrier_nxs_op : Operand<i32> {
  let PrintMethod = "printBarriernXSOption";
  let ParserMatchClass = BarriernXSAsmOperand;
}
class CRmSystemI<Operand crmtype, bits<3> opc, string asm,
                 list<dag> pattern = []>
    : SimpleSystemI<0, (ins crmtype:$CRm), asm, "\t$CRm", pattern>,
      Sched<[WriteBarrier]> {
  bits<4> CRm;
  let Inst{20-12} = 0b000110011;
  let Inst{11-8} = CRm;
  let Inst{7-5} = opc;
}

class SystemNoOperands<bits<3> op2, string asm, list<dag> pattern = []>
    : SimpleSystemI<0, (ins), asm, "", pattern>,
      Sched<[]> {
  bits<4> CRm;
  let CRm = 0b0011;
  let Inst{31-12} = 0b11010101000000110010;
  let Inst{11-8} = CRm;
  let Inst{7-5} = op2;
  let Inst{4-0} = 0b11111;
}

// MRS/MSR system instructions. These have different operand classes because
// a different subset of registers can be accessed through each instruction.
def MRSSystemRegisterOperand : AsmOperandClass {
  let Name = "MRSSystemRegister";
  let ParserMethod = "tryParseSysReg";
  let DiagnosticType = "MRS";
}
// concatenation of op0, op1, CRn, CRm, op2. 16-bit immediate.
def mrs_sysreg_op : Operand<i32> {
  let ParserMatchClass = MRSSystemRegisterOperand;
  let DecoderMethod = "DecodeMRSSystemRegister";
  let PrintMethod = "printMRSSystemRegister";
}

def MSRSystemRegisterOperand : AsmOperandClass {
  let Name = "MSRSystemRegister";
  let ParserMethod = "tryParseSysReg";
  let DiagnosticType = "MSR";
}
def msr_sysreg_op : Operand<i32> {
  let ParserMatchClass = MSRSystemRegisterOperand;
  let DecoderMethod = "DecodeMSRSystemRegister";
  let PrintMethod = "printMSRSystemRegister";
}

def PSBHintOperand : AsmOperandClass {
  let Name = "PSBHint";
  let ParserMethod = "tryParsePSBHint";
}
def psbhint_op : Operand<i32> {
  let ParserMatchClass = PSBHintOperand;
  let PrintMethod = "printPSBHintOp";
  let MCOperandPredicate = [{
    // Check, if operand is valid, to fix exhaustive aliasing in disassembly.
    // "psb" is an alias to "hint" only for certain values of CRm:Op2 fields.
    if (!MCOp.isImm())
      return false;
    return AArch64PSBHint::lookupPSBByEncoding(MCOp.getImm()) != nullptr;
  }];
}

def BTIHintOperand : AsmOperandClass {
  let Name = "BTIHint";
  let ParserMethod = "tryParseBTIHint";
}
def btihint_op : Operand<i32> {
  let ParserMatchClass = BTIHintOperand;
  let PrintMethod = "printBTIHintOp";
  let MCOperandPredicate = [{
    // "bti" is an alias to "hint" only for certain values of CRm:Op2 fields.
    if (!MCOp.isImm())
      return false;
    return AArch64BTIHint::lookupBTIByEncoding(MCOp.getImm() ^ 32) != nullptr;
  }];
}

class MRSI : RtSystemI<1, (outs GPR64:$Rt), (ins mrs_sysreg_op:$systemreg),
                       "mrs", "\t$Rt, $systemreg"> {
  bits<16> systemreg;
  let Inst{20-5} = systemreg;
  let DecoderNamespace = "Fallback";
  // The MRS is set as a NZCV setting instruction. Not all MRS instructions
  // require doing this. The alternative was to explicitly model each one, but
  // it feels like it is unnecessary because it seems there are no negative
  // consequences setting these flags for all.
  let Defs = [NZCV];
}

// FIXME: Some of these def NZCV, others don't. Best way to model that?
// Explicitly modeling each of the system register as a register class
// would do it, but feels like overkill at this point.
class MSRI : RtSystemI<0, (outs), (ins msr_sysreg_op:$systemreg, GPR64:$Rt),
                       "msr", "\t$systemreg, $Rt"> {
  bits<16> systemreg;
  let Inst{20-5} = systemreg;
  let DecoderNamespace = "Fallback";
}

def SystemPStateFieldWithImm0_15Operand : AsmOperandClass {
  let Name = "SystemPStateFieldWithImm0_15";
  let ParserMethod = "tryParseSysReg";
}
def pstatefield4_op : Operand<i32> {
  let ParserMatchClass = SystemPStateFieldWithImm0_15Operand;
  let PrintMethod = "printSystemPStateField";
}

// Instructions to modify PSTATE, no input reg
let Defs = [NZCV] in
class PstateWriteSimple<dag iops, string asm, string operands>
  : SimpleSystemI<0, iops, asm, operands> {

  let Inst{20-19} = 0b00;
  let Inst{15-12} = 0b0100;
}

class MSRpstateImm0_15
  : PstateWriteSimple<(ins pstatefield4_op:$pstatefield, imm0_15:$imm), "msr",
                  "\t$pstatefield, $imm">,
    Sched<[WriteSys]> {

  bits<6> pstatefield;
  bits<4> imm;
  let Inst{18-16} = pstatefield{5-3};
  let Inst{11-8} = imm;
  let Inst{7-5} = pstatefield{2-0};

  let DecoderMethod = "DecodeSystemPStateInstruction";
  // MSRpstateI aliases with MSRI. When the MSRpstateI decoder method returns
  // Fail the decoder should attempt to decode the instruction as MSRI.
  let hasCompleteDecoder = 0;
}

def SystemPStateFieldWithImm0_1Operand : AsmOperandClass {
  let Name = "SystemPStateFieldWithImm0_1";
  let ParserMethod = "tryParseSysReg";
}
def pstatefield1_op : Operand<i32> {
  let ParserMatchClass = SystemPStateFieldWithImm0_1Operand;
  let PrintMethod = "printSystemPStateField";
}

class MSRpstateImm0_1
  : PstateWriteSimple<(ins pstatefield1_op:$pstatefield, imm0_1:$imm), "msr",
                 "\t$pstatefield, $imm">,
    Sched<[WriteSys]> {

  bits<6> pstatefield;
  bit imm;
  let Inst{18-16} = pstatefield{5-3};
  let Inst{11-9} = 0b000;
  let Inst{8} = imm;
  let Inst{7-5} = pstatefield{2-0};

  let DecoderMethod = "DecodeSystemPStateInstruction";
  // MSRpstateI aliases with MSRI. When the MSRpstateI decoder method returns
  // Fail the decoder should attempt to decode the instruction as MSRI.
  let hasCompleteDecoder = 0;
}

// SYS and SYSL generic system instructions.
def SysCRAsmOperand : AsmOperandClass {
  let Name = "SysCR";
  let ParserMethod = "tryParseSysCROperand";
}

def sys_cr_op : Operand<i32> {
  let PrintMethod = "printSysCROperand";
  let ParserMatchClass = SysCRAsmOperand;
}

class SystemXtI<bit L, string asm>
  : RtSystemI<L, (outs),
       (ins imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2, GPR64:$Rt),
       asm, "\t$op1, $Cn, $Cm, $op2, $Rt"> {
  bits<3> op1;
  bits<4> Cn;
  bits<4> Cm;
  bits<3> op2;
  let Inst{20-19} = 0b01;
  let Inst{18-16} = op1;
  let Inst{15-12} = Cn;
  let Inst{11-8}  = Cm;
  let Inst{7-5}   = op2;
}

class SystemLXtI<bit L, string asm>
  : RtSystemI<L, (outs),
       (ins GPR64:$Rt, imm0_7:$op1, sys_cr_op:$Cn, sys_cr_op:$Cm, imm0_7:$op2),
       asm, "\t$Rt, $op1, $Cn, $Cm, $op2"> {
  bits<3> op1;
  bits<4> Cn;
  bits<4> Cm;
  bits<3> op2;
  let Inst{20-19} = 0b01;
  let Inst{18-16} = op1;
  let Inst{15-12} = Cn;
  let Inst{11-8}  = Cm;
  let Inst{7-5}   = op2;
}


// Branch (register) instructions:
//
//  case opc of
//    0001 blr
//    0000 br
//    0101 dret
//    0100 eret
//    0010 ret
//    otherwise UNDEFINED
class BaseBranchReg<bits<4> opc, dag oops, dag iops, string asm,
                    string operands, list<dag> pattern>
    : I<oops, iops, asm, operands, "", pattern>, Sched<[WriteBrReg]> {
  let Inst{31-25} = 0b1101011;
  let Inst{24-21} = opc;
  let Inst{20-16} = 0b11111;
  let Inst{15-10} = 0b000000;
  let Inst{4-0}   = 0b00000;
}

class BranchReg<bits<4> opc, string asm, list<dag> pattern>
    : BaseBranchReg<opc, (outs), (ins GPR64:$Rn), asm, "\t$Rn", pattern> {
  bits<5> Rn;
  let Inst{9-5} = Rn;
}

let mayLoad = 0, mayStore = 0, hasSideEffects = 1, isReturn = 1 in
class SpecialReturn<bits<4> opc, string asm>
    : BaseBranchReg<opc, (outs), (ins), asm, "", []> {
  let Inst{9-5} = 0b11111;
}

let mayLoad = 1 in
class RCPCLoad<bits<2> sz, string asm, RegisterClass RC>
  : I<(outs RC:$Rt), (ins GPR64sp0:$Rn), asm, "\t$Rt, [$Rn]", "", []>,
  Sched<[]> {
  bits<5> Rn;
  bits<5> Rt;
  let Inst{31-30} = sz;
  let Inst{29-10} = 0b11100010111111110000;
  let Inst{9-5} = Rn;
  let Inst{4-0} = Rt;
}

class AuthBase<bits<1> M, dag oops, dag iops, string asm, string operands,
               list<dag> pattern>
  : I<oops, iops, asm, operands, "", pattern>, Sched<[]> {
  let isAuthenticated = 1;
  let Inst{31-25} = 0b1101011;
  let Inst{20-11} = 0b1111100001;
  let Inst{10} = M;
  let Inst{4-0} = 0b11111;
}

class AuthBranchTwoOperands<bits<1> op, bits<1> M, string asm>
  : AuthBase<M, (outs), (ins GPR64:$Rn, GPR64sp:$Rm), asm, "\t$Rn, $Rm", []> {
  bits<5> Rn;
  bits<5> Rm;
  let Inst{24-22} = 0b100;
  let Inst{21} = op;
  let Inst{9-5} = Rn;
  let Inst{4-0} = Rm;
}

class AuthOneOperand<bits<3> opc, bits<1> M, string asm>
  : AuthBase<M, (outs), (ins GPR64:$Rn), asm, "\t$Rn", []> {
  bits<5> Rn;
  let Inst{24} = 0;
  let Inst{23-21} = opc;
  let Inst{9-5} = Rn;
}

let Uses = [LR,SP] in
class AuthReturn<bits<3> op, bits<1> M, string asm>
  : AuthBase<M, (outs), (ins), asm, "", []> {
  let Inst{24} = 0;
  let Inst{23-21} = op;
  let Inst{9-0} = 0b1111111111;
}

let mayLoad = 1 in
class BaseAuthLoad<bit M, bit W, dag oops, dag iops, string asm,
                   string operands, string cstr>
  : I<oops, iops, asm, operands, cstr, []>, Sched<[]> {
  bits<10> offset;
  bits<5> Rn;
  bits<5> Rt;
  let isAuthenticated = 1;
  let Inst{31-24} = 0b11111000;
  let Inst{23} = M;
  let Inst{22} = offset{9};
  let Inst{21} = 1;
  let Inst{20-12} = offset{8-0};
  let Inst{11} = W;
  let Inst{10} = 1;
  let Inst{9-5} = Rn;
  let Inst{4-0} = Rt;

  let DecoderMethod = "DecodeAuthLoadInstruction";
}

multiclass AuthLoad<bit M, string asm, Operand opr> {
  def indexed   : BaseAuthLoad<M, 0, (outs GPR64:$Rt),
                               (ins GPR64sp:$Rn, opr:$offset),
                               asm, "\t$Rt, [$Rn, $offset]", "">;
  def writeback : BaseAuthLoad<M, 1, (outs GPR64sp:$wback, GPR64:$Rt),
                               (ins GPR64sp:$Rn, opr:$offset),
                               asm, "\t$Rt, [$Rn, $offset]!",
                               "$Rn = $wback,@earlyclobber $wback">;

  def : InstAlias<asm # "\t$Rt, [$Rn]",
                  (!cast<Instruction>(NAME # "indexed") GPR64:$Rt, GPR64sp:$Rn, 0)>;

  def : InstAlias<asm # "\t$Rt, [$wback]!",
                  (!cast<Instruction>(NAME # "writeback") GPR64sp:$wback, GPR64:$Rt, 0), 0>;
}

//---
// Conditional branch instruction.
//---

// Condition code.
// 4-bit immediate. Pretty-printed as <cc>
def ccode : Operand<i32> {
  let PrintMethod = "printCondCode";
  let ParserMatchClass = CondCode;
}
def inv_ccode : Operand<i32> {
  // AL and NV are invalid in the aliases which use inv_ccode
  let PrintMethod = "printInverseCondCode";
  let ParserMatchClass = CondCode;
  let MCOperandPredicate = [{
    return MCOp.isImm() &&
           MCOp.getImm() != AArch64CC::AL &&
           MCOp.getImm() != AArch64CC::NV;
  }];
}

// Conditional branch target. 19-bit immediate. The low two bits of the target
// offset are implied zero and so are not part of the immediate.
def am_brcond : Operand<OtherVT> {
  let EncoderMethod = "getCondBranchTargetOpValue";
  let DecoderMethod = "DecodePCRelLabel19";
  let PrintMethod = "printAlignedLabel";
  let ParserMatchClass = PCRelLabel19Operand;
  let OperandType = "OPERAND_PCREL";
}

class BranchCond : I<(outs), (ins ccode:$cond, am_brcond:$target),
                     "b", ".$cond\t$target", "",
                     [(AArch64brcond bb:$target, imm:$cond, NZCV)]>,
                   Sched<[WriteBr]> {
  let isBranch = 1;
  let isTerminator = 1;
  let Uses = [NZCV];

  bits<4> cond;
  bits<19> target;
  let Inst{31-24} = 0b01010100;
  let Inst{23-5} = target;
  let Inst{4} = 0;
  let Inst{3-0} = cond;
}

//---
// Compare-and-branch instructions.
//---
class BaseCmpBranch<RegisterClass regtype, bit op, string asm, SDNode node>
    : I<(outs), (ins regtype:$Rt, am_brcond:$target),
         asm, "\t$Rt, $target", "",
         [(node regtype:$Rt, bb:$target)]>,
      Sched<[WriteBr]> {
  let isBranch = 1;
  let isTerminator = 1;

  bits<5> Rt;
  bits<19> target;
  let Inst{30-25} = 0b011010;
  let Inst{24}    = op;
  let Inst{23-5}  = target;
  let Inst{4-0}   = Rt;
}

multiclass CmpBranch<bit op, string asm, SDNode node> {
  def W : BaseCmpBranch<GPR32, op, asm, node> {
    let Inst{31} = 0;
  }
  def X : BaseCmpBranch<GPR64, op, asm, node> {
    let Inst{31} = 1;
  }
}

//---
// Test-bit-and-branch instructions.
//---
// Test-and-branch target. 14-bit sign-extended immediate. The low two bits of
// the target offset are implied zero and so are not part of the immediate.
def am_tbrcond : Operand<OtherVT> {
  let EncoderMethod = "getTestBranchTargetOpValue";
  let PrintMethod = "printAlignedLabel";
  let ParserMatchClass = BranchTarget14Operand;
  let OperandType = "OPERAND_PCREL";
}

// AsmOperand classes to emit (or not) special diagnostics
def TBZImm0_31Operand : AsmOperandClass {
  let Name = "TBZImm0_31";
  let PredicateMethod = "isImmInRange<0,31>";
  let RenderMethod = "addImmOperands";
}
def TBZImm32_63Operand : AsmOperandClass {
  let Name = "Imm32_63";
  let PredicateMethod = "isImmInRange<32,63>";
  let DiagnosticType = "InvalidImm0_63";
  let RenderMethod = "addImmOperands";
}

class tbz_imm0_31<AsmOperandClass matcher> : Operand<i64>, ImmLeaf<i64, [{
  return (((uint32_t)Imm) < 32);
}]> {
  let ParserMatchClass = matcher;
}

def tbz_imm0_31_diag : tbz_imm0_31<Imm0_31Operand>;
def tbz_imm0_31_nodiag : tbz_imm0_31<TBZImm0_31Operand>;

def tbz_imm32_63 : Operand<i64>, ImmLeaf<i64, [{
  return (((uint32_t)Imm) > 31) && (((uint32_t)Imm) < 64);
}]> {
  let ParserMatchClass = TBZImm32_63Operand;
}

class BaseTestBranch<RegisterClass regtype, Operand immtype,
                     bit op, string asm, SDNode node>
    : I<(outs), (ins regtype:$Rt, immtype:$bit_off, am_tbrcond:$target),
       asm, "\t$Rt, $bit_off, $target", "",
       [(node regtype:$Rt, immtype:$bit_off, bb:$target)]>,
      Sched<[WriteBr]> {
  let isBranch = 1;
  let isTerminator = 1;

  bits<5> Rt;
  bits<6> bit_off;
  bits<14> target;

  let Inst{30-25} = 0b011011;
  let Inst{24}    = op;
  let Inst{23-19} = bit_off{4-0};
  let Inst{18-5}  = target;
  let Inst{4-0}   = Rt;

  let DecoderMethod = "DecodeTestAndBranch";
}

multiclass TestBranch<bit op, string asm, SDNode node> {
  def W : BaseTestBranch<GPR32, tbz_imm0_31_diag, op, asm, node> {
    let Inst{31} = 0;
  }

  def X : BaseTestBranch<GPR64, tbz_imm32_63, op, asm, node> {
    let Inst{31} = 1;
  }

  // Alias X-reg with 0-31 imm to W-Reg.
  def : InstAlias<asm # "\t$Rd, $imm, $target",
                  (!cast<Instruction>(NAME#"W") GPR32as64:$Rd,
                  tbz_imm0_31_nodiag:$imm, am_tbrcond:$target), 0>;
  def : Pat<(node GPR64:$Rn, tbz_imm0_31_diag:$imm, bb:$target),
            (!cast<Instruction>(NAME#"W") (EXTRACT_SUBREG GPR64:$Rn, sub_32),
            tbz_imm0_31_diag:$imm, bb:$target)>;
}

//---
// Unconditional branch (immediate) instructions.
//---
def am_b_target : Operand<OtherVT> {
  let EncoderMethod = "getBranchTargetOpValue";
  let PrintMethod = "printAlignedLabel";
  let ParserMatchClass = BranchTarget26Operand;
  let OperandType = "OPERAND_PCREL";
}
def am_bl_target : Operand<i64> {
  let EncoderMethod = "getBranchTargetOpValue";
  let PrintMethod = "printAlignedLabel";
  let ParserMatchClass = BranchTarget26Operand;
  let OperandType = "OPERAND_PCREL";
}

class BImm<bit op, dag iops, string asm, list<dag> pattern>
    : I<(outs), iops, asm, "\t$addr", "", pattern>, Sched<[WriteBr]> {
  bits<26> addr;
  let Inst{31}    = op;
  let Inst{30-26} = 0b00101;
  let Inst{25-0}  = addr;

  let DecoderMethod = "DecodeUnconditionalBranch";
}

class BranchImm<bit op, string asm, list<dag> pattern>
    : BImm<op, (ins am_b_target:$addr), asm, pattern>;
class CallImm<bit op, string asm, list<dag> pattern>
    : BImm<op, (ins am_bl_target:$addr), asm, pattern>;

//---
// Basic one-operand data processing instructions.
//---

let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
class BaseOneOperandData<bits<3> opc, RegisterClass regtype, string asm,
                         SDPatternOperator node>
  : I<(outs regtype:$Rd), (ins regtype:$Rn), asm, "\t$Rd, $Rn", "",
      [(set regtype:$Rd, (node regtype:$Rn))]>,
    Sched<[WriteI, ReadI]> {
  bits<5> Rd;
  bits<5> Rn;

  let Inst{30-13} = 0b101101011000000000;
  let Inst{12-10} = opc;
  let Inst{9-5}   = Rn;
  let Inst{4-0}   = Rd;
}

let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
multiclass OneOperandData<bits<3> opc, string asm,
                          SDPatternOperator node = null_frag> {
  def Wr : BaseOneOperandData<opc, GPR32, asm, node> {
    let Inst{31} = 0;
  }

  def Xr : BaseOneOperandData<opc, GPR64, asm, node> {
    let Inst{31} = 1;
  }
}

class OneWRegData<bits<3> opc, string asm, SDPatternOperator node>
    : BaseOneOperandData<opc, GPR32, asm, node> {
  let Inst{31} = 0;
}

class OneXRegData<bits<3> opc, string asm, SDPatternOperator node>
    : BaseOneOperandData<opc, GPR64, asm, node> {
  let Inst{31} = 1;
}

class SignAuthOneData<bits<3> opcode_prefix, bits<2> opcode, string asm,
                      SDPatternOperator op>
  : I<(outs GPR64:$dst), (ins GPR64:$Rd, GPR64sp:$Rn), asm, "\t$Rd, $Rn",
      "$dst = $Rd", [(set GPR64:$dst, (op GPR64:$Rd, opcode, GPR64sp:$Rn))]>,
    Sched<[WriteI, ReadI]> {
  bits<5> Rd;
  bits<5> Rn;
  let Inst{31-15} = 0b11011010110000010;
  let Inst{14-12} = opcode_prefix;
  let Inst{11-10} = opcode;
  let Inst{9-5} = Rn;
  let Inst{4-0} = Rd;
}

class SignAuthZero<bits<3> opcode_prefix, bits<2> opcode, string asm,
                   SDPatternOperator op>
  : I<(outs GPR64:$dst), (ins GPR64:$Rd), asm, "\t$Rd", "$dst = $Rd",
      [(set GPR64:$dst, (op GPR64:$Rd, opcode, (i64 0)))]>,
    Sched<[]> {
  bits<5> Rd;
  let Inst{31-15} = 0b11011010110000010;
  let Inst{14-12} = opcode_prefix;
  let Inst{11-10} = opcode;
  let Inst{9-5} = 0b11111;
  let Inst{4-0} = Rd;
}

class SignAuthTwoOperand<bits<4> opc, string asm,
                         SDPatternOperator OpNode>
  : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64sp:$Rm),
      asm, "\t$Rd, $Rn, $Rm", "",
      [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64sp:$Rm))]>,
    Sched<[WriteI, ReadI, ReadI]> {
  bits<5> Rd;
  bits<5> Rn;
  bits<5> Rm;
  let Inst{31-21} = 0b10011010110;
  let Inst{20-16} = Rm;
  let Inst{15-14} = 0b00;
  let Inst{13-10} = opc;
  let Inst{9-5}   = Rn;
  let Inst{4-0}   = Rd;
}

class ClearAuth<bits<1> data, string asm>
  : I<(outs GPR64:$Rd), (ins GPR64:$Rn), asm, "\t$Rd", "$Rd = $Rn", []>, Sched<[]> {
  bits<5> Rd;
  let Inst{31-11} = 0b110110101100000101000;
  let Inst{10} = data;
  let Inst{9-5} = 0b11111;
  let Inst{4-0} = Rd;
}

// Base class for the Armv8.4-A 8 and 16-bit flag manipulation instructions
class BaseFlagManipulation<bit sf, bit sz, dag iops, string asm, string ops>
    : I<(outs), iops, asm, ops, "", []>,
      Sched<[WriteI, ReadI, ReadI]> {
  let Uses = [NZCV];
  let Defs = [NZCV];
  bits<5> Rn;
  let Inst{31}    = sf;
  let Inst{30-15} = 0b0111010000000000;
  let Inst{14}    = sz;
  let Inst{13-10} = 0b0010;
  let Inst{9-5}   = Rn;
  let Inst{4-0}   = 0b01101;
}

class FlagRotate<dag iops, string asm, string ops>
    : BaseFlagManipulation<0b1, 0b0, iops, asm, ops> {
  bits<6> imm;
  bits<4> mask;
  let Inst{20-15} = imm;
  let Inst{13-10} = 0b0001;
  let Inst{4}     = 0b0;
  let Inst{3-0}   = mask;
}

//---
// Basic two-operand data processing instructions.
//---
class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
                          list<dag> pattern>
    : I<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
        asm, "\t$Rd, $Rn, $Rm", "", pattern>,
      Sched<[WriteI, ReadI, ReadI]> {
  let Uses = [NZCV];
  bits<5> Rd;
  bits<5> Rn;
  bits<5> Rm;
  let Inst{30}    = isSub;
  let Inst{28-21} = 0b11010000;
  let Inst{20-16} = Rm;
  let Inst{15-10} = 0;
  let Inst{9-5}   = Rn;
  let Inst{4-0}   = Rd;
}

class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
                      SDNode OpNode>
    : BaseBaseAddSubCarry<isSub, regtype, asm,
        [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV))]>;

class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
                              SDNode OpNode>
    : BaseBaseAddSubCarry<isSub, regtype, asm,
        [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm, NZCV)),
         (implicit NZCV)]> {
  let Defs = [NZCV];
}

multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
                       SDNode OpNode, SDNode OpNode_setflags> {
  def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
    let Inst{31} = 0;
    let Inst{29} = 0;
  }
  def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
    let Inst{31} = 1;
    let Inst{29} = 0;
  }

  // Sets flags.
  def SWr : BaseAddSubCarrySetFlags<isSub, GPR32, asm_setflags,
                                    OpNode_setflags> {
    let Inst{31} = 0;
    let Inst{29} = 1;
  }
  def SXr : BaseAddSubCarrySetFlags<isSub, GPR64, asm_setflags,
                                    OpNode_setflags> {
    let Inst{31} = 1;
    let Inst{29} = 1;
  }
}

class BaseTwoOperand<bits<4> opc, RegisterClass regtype, string asm,
                     SDPatternOperator OpNode,
                     RegisterClass in1regtype = regtype,
                     RegisterClass in2regtype = regtype>
  : I<(outs regtype:$Rd), (ins in1regtype:$Rn, in2regtype:$Rm),
      asm, "\t$Rd, $Rn, $Rm", "",
      [(set regtype:$Rd, (OpNode in1regtype:$Rn, in2regtype:$Rm))]> {
  bits<5> Rd;
  bits<5> Rn;
  bits<5> Rm;
  let Inst{30-21} = 0b0011010110;
  let Inst{20-16} = Rm;
  let Inst{15-14} = 0b00;
  let Inst{13-10} = opc;
  let Inst{9-5}   = Rn;
  let Inst{4-0}   = Rd;
}

class BaseDiv<bit isSigned, RegisterClass regtype, string asm,
              SDPatternOperator OpNode>
    : BaseTwoOperand<{0,0,1,?}, regtype, asm, OpNode> {
  let Inst{10}    = isSigned;
}

multiclass Div<bit isSigned, string asm, SDPatternOperator OpNode> {
  def Wr : BaseDiv<isSigned, GPR32, asm, OpNode>,
           Sched<[WriteID32, ReadID, ReadID]> {
    let Inst{31} = 0;
  }
  def Xr : BaseDiv<isSigned, GPR64, asm, OpNode>,
           Sched<[WriteID64, ReadID, ReadID]> {
    let Inst{31} = 1;
  }
}

class BaseShift<bits<2> shift_type, RegisterClass regtype, string asm,
                SDPatternOperator OpNode = null_frag>
  : BaseTwoOperand<{1,0,?,?}, regtype, asm, OpNode>,
    Sched<[WriteIS, ReadI]> {
  let Inst{11-10} = shift_type;
}

multiclass Shift<bits<2> shift_type, string asm, SDNode OpNode> {
  def Wr : BaseShift<shift_type, GPR32, asm> {
    let Inst{31} = 0;
  }

  def Xr : BaseShift<shift_type, GPR64, asm, OpNode> {
    let Inst{31} = 1;
  }

  def : Pat<(i32 (OpNode GPR32:$Rn, i64:$Rm)),
            (!cast<Instruction>(NAME # "Wr") GPR32:$Rn,
                                             (EXTRACT_SUBREG i64:$Rm, sub_32))>;

  def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (zext GPR32:$Rm)))),
            (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;

  def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (anyext GPR32:$Rm)))),
            (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;

  def : Pat<(i32 (OpNode GPR32:$Rn, (i64 (sext GPR32:$Rm)))),
            (!cast<Instruction>(NAME # "Wr") GPR32:$Rn, GPR32:$Rm)>;

  def : Pat<(i64 (OpNode GPR64:$Rn, (i64 (sext GPR32:$Rm)))),
            (!cast<Instruction>(NAME # "Xr") GPR64:$Rn,
                (SUBREG_TO_REG (i32 0), GPR32:$Rm, sub_32))>;

  def : Pat<(i64 (OpNode GPR64:$Rn, (i64 (zext GPR32:$Rm)))),
            (!cast<Instruction>(NAME # "Xr") GPR64:$Rn,
                (SUBREG_TO_REG (i32 0), GPR32:$Rm, sub_32))>;
}

class ShiftAlias<string asm, Instruction inst, RegisterClass regtype>
    : InstAlias<asm#"\t$dst, $src1, $src2",
                (inst regtype:$dst, regtype:$src1, regtype:$src2), 0>;

class BaseMulAccum<bit isSub, bits<3> opc, RegisterClass multype,
                       RegisterClass addtype, string asm,
                       list<dag> pattern>
  : I<(outs addtype:$Rd), (ins multype:$Rn, multype:$Rm, addtype:$Ra),
      asm, "\t$Rd, $Rn, $Rm, $Ra", "", pattern> {
  bits<5> Rd;
  bits<5> Rn;
  bits<5> Rm;
  bits<5> Ra;
  let Inst{30-24} = 0b0011011;
  let Inst{23-21} = opc;
  let Inst{20-16} = Rm;
  let Inst{15}    = isSub;
  let Inst{14-10} = Ra;
  let Inst{9-5}   = Rn;
  let Inst{4-0}   = Rd;
}

multiclass MulAccum<bit isSub, string asm> {
  // MADD/MSUB generation is decided by MachineCombiner.cpp
  def Wrrr : BaseMulAccum<isSub, 0b000, GPR32, GPR32, asm, []>,
      Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
    let Inst{31} = 0;
  }

  def Xrrr : BaseMulAccum<isSub, 0b000, GPR64, GPR64, asm, []>,
      Sched<[WriteIM64, ReadIM, ReadIM, ReadIMA]> {
    let Inst{31} = 1;
  }
}

class WideMulAccum<bit isSub, bits<3> opc, string asm,
                   SDNode AccNode, SDNode ExtNode>
  : BaseMulAccum<isSub, opc, GPR32, GPR64, asm,
    [(set GPR64:$Rd, (AccNode GPR64:$Ra,
                            (mul (ExtNode GPR32:$Rn), (ExtNode GPR32:$Rm))))]>,
    Sched<[WriteIM32, ReadIM, ReadIM, ReadIMA]> {
  let Inst{31} = 1;
}

class MulHi<bits<3> opc, string asm, SDNode OpNode>
  : I<(outs GPR64:$Rd), (ins GPR64:$Rn, GPR64:$Rm),
      asm, "\t$Rd, $Rn, $Rm", "",
      [(set GPR64:$Rd, (OpNode GPR64:$Rn, GPR64:$Rm))]>,
    Sched<[WriteIM64, ReadIM, ReadIM]> {
  bits<5> Rd;
  bits<5> Rn;
  bits<5> Rm;
  let Inst{31-24} = 0b10011011;
  let Inst{23-21} = opc;
  let Inst{20-16} = Rm;
  let Inst{15}    = 0;
  let Inst{9-5}   = Rn;
  let Inst{4-0}   = Rd;

  // The Ra field of SMULH and UMULH is unused: it should be assembled as 31
  // (i.e. all bits 1) but is ignored by the processor.
  let PostEncoderMethod = "fixMulHigh";
}

class MulAccumWAlias<string asm, Instruction inst>
    : InstAlias<asm#"\t$dst, $src1, $src2",
                (inst GPR32:$dst, GPR32:$src1, GPR32:$src2, WZR)>;
class MulAccumXAlias<string asm, Instruction inst>
    : InstAlias<asm#"\t$dst, $src1, $src2",
                (inst GPR64:$dst, GPR64:$src1, GPR64:$src2, XZR)>;
class WideMulAccumAlias<string asm, Instruction inst>
    : InstAlias<asm#"\t$dst, $src1, $src2",
                (inst GPR64:$dst, GPR32:$src1, GPR32:$src2, XZR)>;

class BaseCRC32<bit sf, bits<2> sz, bit C, RegisterClass StreamReg,
              SDPatternOperator OpNode, string asm>
  : I<(outs GPR32:$Rd), (ins GPR32:$Rn, StreamReg:$Rm),
      asm, "\t$Rd, $Rn, $Rm", "",
      [(set GPR32:$Rd, (OpNode GPR32:$Rn, StreamReg:$Rm))]>,
    Sched<[WriteISReg, ReadI, ReadISReg]> {
  bits<5> Rd;
  bits<5> Rn;
  bits<5> Rm;

  let Inst{31} = sf;
  let Inst{30-21} = 0b0011010110;
  let Inst{20-16} = Rm;
  let Inst{15-13} = 0b010;
  let Inst{12} = C;
  let Inst{11-10} = sz;
  let Inst{9-5} = Rn;
  let Inst{4-0} = Rd;
  let Predicates = [HasCRC];
}

//---
// Address generation.
//---

class ADRI<bit page, string asm, Operand adr, list<dag> pattern>
    : I<(outs GPR64:$Xd), (ins adr:$label), asm, "\t$Xd, $label", "",
        pattern>,
      Sched<[WriteI]> {
  bits<5>  Xd;
  bits<21> label;
  let Inst{31}    = page;
  let Inst{30-29} = label{1-0};
  let Inst{28-24} = 0b10000;
  let Inst{23-5}  = label{20-2};
  let Inst{4-0}   = Xd;

  let DecoderMethod = "DecodeAdrInstruction";
}

//---
// Move immediate.
//---

def movimm32_imm : Operand<i32> {
  let ParserMatchClass = AsmImmRange<0, 65535>;
  let EncoderMethod = "getMoveWideImmOpValue";
  let PrintMethod = "printImm";
}
def movimm32_shift : Operand<i32> {
  let PrintMethod = "printShifter";
  let ParserMatchClass = MovImm32ShifterOperand;
}
def movimm64_shift : Operand<i32> {
  let PrintMethod = "printShifter";
  let ParserMatchClass = MovImm64ShifterOperand;
}

let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
class BaseMoveImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
                        string asm>
  : I<(outs regtype:$Rd), (ins movimm32_imm:$imm, shifter:$shift),
       asm, "\t$Rd, $imm$shift", "", []>,
    Sched<[WriteImm]> {
  bits<5> Rd;
  bits<16> imm;
  bits<6> shift;
  let Inst{30-29} = opc;
  let Inst{28-23} = 0b100101;
  let Inst{22-21} = shift{5-4};
  let Inst{20-5}  = imm;
  let Inst{4-0}   = Rd;

  let DecoderMethod = "DecodeMoveImmInstruction";
}

multiclass MoveImmediate<bits<2> opc, string asm> {
  def Wi : BaseMoveImmediate<opc, GPR32, movimm32_shift, asm> {
    let Inst{31} = 0;
  }

  def Xi : BaseMoveImmediate<opc, GPR64, movimm64_shift, asm> {
    let Inst{31} = 1;
  }
}

let mayLoad = 0, mayStore = 0, hasSideEffects = 0 in
class BaseInsertImmediate<bits<2> opc, RegisterClass regtype, Operand shifter,
                          string asm>
  : I<(outs regtype:$Rd),
      (ins regtype:$src, movimm32_imm:$imm, shifter:$shift),
       asm, "\t$Rd, $imm$shift", "$src = $Rd", []>,
    Sched<[WriteI, ReadI]> {
  bits<5> Rd;
  bits<16> imm;
  bits<6> shift;
  let Inst{30-29} = opc;
  let Inst{28-23} = 0b100101;
  let Inst{22-21} = shift{5-4};
  let Inst{20-5}  = imm;
  let Inst{4-0}   = Rd;

  let DecoderMethod = "DecodeMoveImmInstruction";
}

multiclass InsertImmediate<bits<2> opc, string asm> {
  def Wi : BaseInsertImmediate<opc, GPR32, movimm32_shift, asm> {
    let Inst{31} = 0;
  }

  def Xi : BaseInsertImmediate<opc, GPR64, movimm64_shift, asm> {
    let Inst{31} = 1;
  }
}

//---
// Add/Subtract
//---

class BaseAddSubImm<bit isSub, bit setFlags, RegisterClass dstRegtype,
                    string asm_inst, string asm_ops,
                    dag inputs, dag pattern>
    : I<(outs dstRegtype:$Rd), inputs, asm_inst, asm_ops, "", [pattern]>,
      Sched<[WriteI, ReadI]> {
  bits<5>  Rd;
  bits<5>  Rn;
  let Inst{30}    = isSub;
  let Inst{29}    = setFlags;
  let Inst{28-24} = 0b10001;
  let Inst{9-5}   = Rn;
  let Inst{4-0}   = Rd;
}

class AddSubImmShift<bit isSub, bit setFlags, RegisterClass dstRegtype,
                     RegisterClass srcRegtype, addsub_shifted_imm immtype,
                     string asm_inst, SDPatternOperator OpNode>
    : BaseAddSubImm<isSub, setFlags, dstRegtype, asm_inst, "\t$Rd, $Rn, $imm",
                    (ins srcRegtype:$Rn, immtype:$imm),
                    (set dstRegtype:$Rd, (OpNode srcRegtype:$Rn, immtype:$imm))> {
  bits<14> imm;
  let Inst{23-22} = imm{13-12}; // '00' => lsl #0, '01' => lsl #12
  let Inst{21-10} = imm{11-0};
  let DecoderMethod = "DecodeAddSubImmShift";
}

class BaseAddSubRegPseudo<RegisterClass regtype,
                          SDPatternOperator OpNode>
    : Pseudo<(outs regtype:$Rd), (ins regtype:$Rn, regtype:$Rm),
             [(set regtype:$Rd, (OpNode regtype:$Rn, regtype:$Rm))]>,
      Sched<[WriteI, ReadI, ReadI]>;

class BaseAddSubSReg<bit isSub, bit setFlags, RegisterClass regtype,
                     arith_shifted_reg shifted_regtype, string asm,
                     SDPatternOperator OpNode>
    : I<(outs regtype:$Rd), (ins regtype:$Rn, shifted_regtype:$Rm),
        asm, "\t$Rd, $Rn, $Rm", "",
        [(set regtype:$Rd, (OpNode regtype:$Rn, shifted_regtype:$Rm))]>,
      Sched<[WriteISReg, ReadI, ReadISReg