| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -run-pass=peephole-opt %s -o - -verify-machineinstrs | FileCheck %s |
| |
| # The and -> ands transform is sensitive to scheduling; make sure we don't |
| # transform cases which aren't legal. |
| |
| --- | |
| target triple = "armv7-unknown-unknown" |
| define i32 @foo_transform(i32 %in) { |
| ret i32 undef |
| } |
| define i32 @foo_notransform(i32 %in) { |
| ret i32 undef |
| } |
| |
| ... |
| --- |
| name: foo_transform |
| tracksRegLiveness: true |
| body: | |
| bb.0 (%ir-block.0): |
| liveins: $r0 |
| |
| ; CHECK-LABEL: name: foo_transform |
| ; CHECK: liveins: $r0 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r0 |
| ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 4, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: [[ANDri:%[0-9]+]]:gpr = ANDri [[COPY]], 1, 14 /* CC::al */, $noreg, def $cpsr |
| ; CHECK: [[MOVCCi16_:%[0-9]+]]:gpr = MOVCCi16 [[MOVi]], 5, 0 /* CC::eq */, $cpsr |
| ; CHECK: $r0 = COPY killed [[MOVCCi16_]] |
| ; CHECK: $r1 = COPY killed [[ANDri]] |
| ; CHECK: BX_RET 14 /* CC::al */, $noreg, implicit $r0, implicit $r1 |
| %1:gpr = COPY $r0 |
| %2:gpr = MOVi 4, 14, $noreg, $noreg |
| %4:gpr = ANDri %1:gpr, 1, 14, $noreg, $noreg |
| TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr |
| %3:gpr = MOVCCi16 %2, 5, 0, $cpsr |
| $r0 = COPY killed %3 |
| $r1 = COPY killed %4 |
| BX_RET 14, $noreg, implicit $r0, implicit $r1 |
| ... |
| name: foo_notransform |
| tracksRegLiveness: true |
| body: | |
| bb.0 (%ir-block.0): |
| liveins: $r0 |
| |
| %1:gpr = COPY $r0 |
| %2:gpr = MOVi 4, 14, $noreg, $noreg |
| TSTri %1:gpr, 1, 14, $noreg, implicit-def $cpsr |
| %3:gpr = MOVCCi16 %2, 5, 0, $cpsr |
| %4:gpr = ANDri %1:gpr, 1, 14, $noreg, $noreg |
| $r0 = COPY killed %3 |
| $r1 = COPY killed %4 |
| BX_RET 14, $noreg, implicit $r0, implicit $r1 |
| |