| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mattr=+sve < %s | FileCheck %s -check-prefixes=CHECK,SVE1 |
| ; RUN: llc -mattr=+sve2 < %s | FileCheck %s -check-prefixes=CHECK,SVE2 |
| |
| target triple = "aarch64-unknown-linux-gnu" |
| |
| ; |
| ; ADD |
| ; |
| |
| define <vscale x 16 x i8> @add_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { |
| ; CHECK-LABEL: add_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: add z0.b, z0.b, z1.b |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.add.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %b) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @add_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { |
| ; CHECK-LABEL: add_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: add z0.h, z0.h, z1.h |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.add.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %b) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @add_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { |
| ; CHECK-LABEL: add_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: add z0.s, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @add_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { |
| ; CHECK-LABEL: add_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: add z0.d, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.add.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %b) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; ADD (immediate) |
| ; |
| |
| define <vscale x 16 x i8> @add_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: add_imm_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: add z0.b, z0.b, #3 // =0x3 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 16 x i8> undef, i8 3, i32 0 |
| %imm.splat = shufflevector <vscale x 16 x i8> %imm, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.add.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %imm.splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @add_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: add_imm_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: add z0.h, z0.h, #4 // =0x4 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 8 x i16> undef, i16 4, i32 0 |
| %imm.splat = shufflevector <vscale x 8 x i16> %imm, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.add.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %imm.splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @add_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: add_imm_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: add z0.s, z0.s, #5 // =0x5 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 4 x i32> undef, i32 5, i32 0 |
| %imm.splat = shufflevector <vscale x 4 x i32> %imm, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %imm.splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @add_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: add_imm_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: add z0.d, z0.d, #6 // =0x6 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 2 x i64> undef, i64 6, i32 0 |
| %imm.splat = shufflevector <vscale x 2 x i64> %imm, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.add.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %imm.splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; MLA |
| ; |
| |
| define <vscale x 16 x i8> @mla_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) { |
| ; CHECK-LABEL: mla_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mla z0.b, p0/m, z1.b, z2.b |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.mla.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %b, |
| <vscale x 16 x i8> %c) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @mla_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) { |
| ; CHECK-LABEL: mla_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mla z0.h, p0/m, z1.h, z2.h |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mla.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %b, |
| <vscale x 8 x i16> %c) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @mla_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) { |
| ; CHECK-LABEL: mla_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mla z0.s, p0/m, z1.s, z2.s |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b, |
| <vscale x 4 x i32> %c) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @mla_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) { |
| ; CHECK-LABEL: mla_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mla z0.d, p0/m, z1.d, z2.d |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mla.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %b, |
| <vscale x 2 x i64> %c) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; MLS |
| ; |
| |
| define <vscale x 16 x i8> @mls_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b, <vscale x 16 x i8> %c) { |
| ; CHECK-LABEL: mls_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mls z0.b, p0/m, z1.b, z2.b |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.mls.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %b, |
| <vscale x 16 x i8> %c) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @mls_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b, <vscale x 8 x i16> %c) { |
| ; CHECK-LABEL: mls_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mls z0.h, p0/m, z1.h, z2.h |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mls.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %b, |
| <vscale x 8 x i16> %c) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @mls_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b, <vscale x 4 x i32> %c) { |
| ; CHECK-LABEL: mls_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mls z0.s, p0/m, z1.s, z2.s |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mls.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b, |
| <vscale x 4 x i32> %c) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @mls_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b, <vscale x 2 x i64> %c) { |
| ; CHECK-LABEL: mls_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mls z0.d, p0/m, z1.d, z2.d |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mls.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %b, |
| <vscale x 2 x i64> %c) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; MUL |
| ; |
| |
| define <vscale x 16 x i8> @mul_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { |
| ; SVE1-LABEL: mul_i8: |
| ; SVE1: // %bb.0: |
| ; SVE1-NEXT: mul z0.b, p0/m, z0.b, z1.b |
| ; SVE1-NEXT: ret |
| ; |
| ; SVE2-LABEL: mul_i8: |
| ; SVE2: // %bb.0: |
| ; SVE2-NEXT: mul z0.b, z0.b, z1.b |
| ; SVE2-NEXT: ret |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %b) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @mul_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { |
| ; SVE1-LABEL: mul_i16: |
| ; SVE1: // %bb.0: |
| ; SVE1-NEXT: mul z0.h, p0/m, z0.h, z1.h |
| ; SVE1-NEXT: ret |
| ; |
| ; SVE2-LABEL: mul_i16: |
| ; SVE2: // %bb.0: |
| ; SVE2-NEXT: mul z0.h, z0.h, z1.h |
| ; SVE2-NEXT: ret |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %b) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @mul_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { |
| ; SVE1-LABEL: mul_i32: |
| ; SVE1: // %bb.0: |
| ; SVE1-NEXT: mul z0.s, p0/m, z0.s, z1.s |
| ; SVE1-NEXT: ret |
| ; |
| ; SVE2-LABEL: mul_i32: |
| ; SVE2: // %bb.0: |
| ; SVE2-NEXT: mul z0.s, z0.s, z1.s |
| ; SVE2-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @mul_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { |
| ; SVE1-LABEL: mul_i64: |
| ; SVE1: // %bb.0: |
| ; SVE1-NEXT: mul z0.d, p0/m, z0.d, z1.d |
| ; SVE1-NEXT: ret |
| ; |
| ; SVE2-LABEL: mul_i64: |
| ; SVE2: // %bb.0: |
| ; SVE2-NEXT: mul z0.d, z0.d, z1.d |
| ; SVE2-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %b) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; MUL (immediate) |
| ; |
| |
| define <vscale x 16 x i8> @mul_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: mul_imm_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mul z0.b, z0.b, #3 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 16 x i8> undef, i8 3, i32 0 |
| %imm.splat = shufflevector <vscale x 16 x i8> %imm, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %imm.splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @mul_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: mul_imm_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mul z0.h, z0.h, #4 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 8 x i16> undef, i16 4, i32 0 |
| %imm.splat = shufflevector <vscale x 8 x i16> %imm, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.mul.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %imm.splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @mul_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: mul_imm_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mul z0.s, z0.s, #5 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 4 x i32> undef, i32 5, i32 0 |
| %imm.splat = shufflevector <vscale x 4 x i32> %imm, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %imm.splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @mul_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: mul_imm_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mul z0.d, z0.d, #6 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 2 x i64> undef, i64 6, i32 0 |
| %imm.splat = shufflevector <vscale x 2 x i64> %imm, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.mul.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %imm.splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; SABD |
| ; |
| |
| define <vscale x 16 x i8> @sabd_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { |
| ; CHECK-LABEL: sabd_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.b |
| ; CHECK-NEXT: sabd z0.b, p0/m, z0.b, z1.b |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sabd.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %b) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @sabd_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { |
| ; CHECK-LABEL: sabd_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.h |
| ; CHECK-NEXT: sabd z0.h, p0/m, z0.h, z1.h |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sabd.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %b) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @sabd_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { |
| ; CHECK-LABEL: sabd_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.s |
| ; CHECK-NEXT: sabd z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sabd.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @sabd_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { |
| ; CHECK-LABEL: sabd_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.d |
| ; CHECK-NEXT: sabd z0.d, p0/m, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sabd.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %b) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; SDIV |
| ; |
| |
| define <vscale x 4 x i32> @sdiv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { |
| ; CHECK-LABEL: sdiv_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sdiv z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @sdiv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { |
| ; CHECK-LABEL: sdiv_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sdiv z0.d, p0/m, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %b) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; SDIVR |
| ; |
| |
| define <vscale x 4 x i32> @sdivr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { |
| ; CHECK-LABEL: sdivr_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sdivr z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %b, |
| <vscale x 4 x i32> %a) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @sdivr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { |
| ; CHECK-LABEL: sdivr_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sdivr z0.d, p0/m, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %b, |
| <vscale x 2 x i64> %a) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; SMAX |
| ; |
| |
| define <vscale x 16 x i8> @smax_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { |
| ; CHECK-LABEL: smax_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smax z0.b, p0/m, z0.b, z1.b |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.smax.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %b) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @smax_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { |
| ; CHECK-LABEL: smax_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smax.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %b) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @smax_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { |
| ; CHECK-LABEL: smax_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smax.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @smax_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { |
| ; CHECK-LABEL: smax_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smax.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %b) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; SMAX (immediate) |
| ; |
| |
| define <vscale x 16 x i8> @smax_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: smax_imm_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smax z0.b, z0.b, #3 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 16 x i8> undef, i8 3, i32 0 |
| %imm.splat = shufflevector <vscale x 16 x i8> %imm, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.smax.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %imm.splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @smax_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: smax_imm_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smax z0.h, z0.h, #4 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 8 x i16> undef, i16 4, i32 0 |
| %imm.splat = shufflevector <vscale x 8 x i16> %imm, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smax.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %imm.splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @smax_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: smax_imm_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smax z0.s, z0.s, #5 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 4 x i32> undef, i32 5, i32 0 |
| %imm.splat = shufflevector <vscale x 4 x i32> %imm, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smax.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %imm.splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @smax_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: smax_imm_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smax z0.d, z0.d, #6 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 2 x i64> undef, i64 6, i32 0 |
| %imm.splat = shufflevector <vscale x 2 x i64> %imm, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smax.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %imm.splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; SMIN |
| ; |
| |
| define <vscale x 16 x i8> @smin_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { |
| ; CHECK-LABEL: smin_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smin z0.b, p0/m, z0.b, z1.b |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.smin.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %b) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @smin_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { |
| ; CHECK-LABEL: smin_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smin.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %b) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @smin_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { |
| ; CHECK-LABEL: smin_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smin.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @smin_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { |
| ; CHECK-LABEL: smin_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smin.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %b) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; SMIN (immediate) |
| ; |
| |
| define <vscale x 16 x i8> @smin_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: smin_imm_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smin z0.b, z0.b, #3 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 16 x i8> undef, i8 3, i32 0 |
| %imm.splat = shufflevector <vscale x 16 x i8> %imm, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.smin.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %imm.splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @smin_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: smin_imm_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smin z0.h, z0.h, #4 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 8 x i16> undef, i16 4, i32 0 |
| %imm.splat = shufflevector <vscale x 8 x i16> %imm, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smin.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %imm.splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @smin_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: smin_imm_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smin z0.s, z0.s, #5 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 4 x i32> undef, i32 5, i32 0 |
| %imm.splat = shufflevector <vscale x 4 x i32> %imm, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smin.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %imm.splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @smin_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: smin_imm_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smin z0.d, z0.d, #6 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 2 x i64> undef, i64 6, i32 0 |
| %imm.splat = shufflevector <vscale x 2 x i64> %imm, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smin.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %imm.splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; SMULH |
| ; |
| |
| define <vscale x 16 x i8> @smulh_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { |
| ; SVE1-LABEL: smulh_i8: |
| ; SVE1: // %bb.0: |
| ; SVE1-NEXT: smulh z0.b, p0/m, z0.b, z1.b |
| ; SVE1-NEXT: ret |
| ; |
| ; SVE2-LABEL: smulh_i8: |
| ; SVE2: // %bb.0: |
| ; SVE2-NEXT: smulh z0.b, z0.b, z1.b |
| ; SVE2-NEXT: ret |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.smulh.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %b) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @smulh_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { |
| ; SVE1-LABEL: smulh_i16: |
| ; SVE1: // %bb.0: |
| ; SVE1-NEXT: smulh z0.h, p0/m, z0.h, z1.h |
| ; SVE1-NEXT: ret |
| ; |
| ; SVE2-LABEL: smulh_i16: |
| ; SVE2: // %bb.0: |
| ; SVE2-NEXT: smulh z0.h, z0.h, z1.h |
| ; SVE2-NEXT: ret |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smulh.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %b) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @smulh_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { |
| ; SVE1-LABEL: smulh_i32: |
| ; SVE1: // %bb.0: |
| ; SVE1-NEXT: smulh z0.s, p0/m, z0.s, z1.s |
| ; SVE1-NEXT: ret |
| ; |
| ; SVE2-LABEL: smulh_i32: |
| ; SVE2: // %bb.0: |
| ; SVE2-NEXT: smulh z0.s, z0.s, z1.s |
| ; SVE2-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smulh.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @smulh_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { |
| ; SVE1-LABEL: smulh_i64: |
| ; SVE1: // %bb.0: |
| ; SVE1-NEXT: smulh z0.d, p0/m, z0.d, z1.d |
| ; SVE1-NEXT: ret |
| ; |
| ; SVE2-LABEL: smulh_i64: |
| ; SVE2: // %bb.0: |
| ; SVE2-NEXT: smulh z0.d, z0.d, z1.d |
| ; SVE2-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smulh.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %b) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; SUB |
| ; |
| |
| define <vscale x 16 x i8> @sub_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { |
| ; CHECK-LABEL: sub_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.b, z0.b, z1.b |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %b) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @sub_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { |
| ; CHECK-LABEL: sub_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.h, z0.h, z1.h |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %b) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @sub_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { |
| ; CHECK-LABEL: sub_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.s, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @sub_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { |
| ; CHECK-LABEL: sub_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.d, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %b) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; SUB (immediate) |
| ; |
| |
| define <vscale x 16 x i8> @sub_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: sub_imm_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.b, z0.b, #3 // =0x3 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 16 x i8> undef, i8 3, i32 0 |
| %imm.splat = shufflevector <vscale x 16 x i8> %imm, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %imm.splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @sub_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: sub_imm_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.h, z0.h, #4 // =0x4 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 8 x i16> undef, i16 4, i32 0 |
| %imm.splat = shufflevector <vscale x 8 x i16> %imm, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %imm.splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @sub_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: sub_imm_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.s, z0.s, #5 // =0x5 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 4 x i32> undef, i32 5, i32 0 |
| %imm.splat = shufflevector <vscale x 4 x i32> %imm, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %imm.splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @sub_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: sub_imm_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.d, z0.d, #6 // =0x6 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 2 x i64> undef, i64 6, i32 0 |
| %imm.splat = shufflevector <vscale x 2 x i64> %imm, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %imm.splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; SUBR |
| ; |
| |
| define <vscale x 16 x i8> @subr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { |
| ; CHECK-LABEL: subr_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.b, z1.b, z0.b |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %b, |
| <vscale x 16 x i8> %a) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @subr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { |
| ; CHECK-LABEL: subr_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.h, z1.h, z0.h |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %b, |
| <vscale x 8 x i16> %a) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @subr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { |
| ; CHECK-LABEL: subr_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.s, z1.s, z0.s |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %b, |
| <vscale x 4 x i32> %a) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @subr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { |
| ; CHECK-LABEL: subr_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.d, z1.d, z0.d |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %b, |
| <vscale x 2 x i64> %a) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; SUBR (immediate) |
| ; |
| |
| define <vscale x 16 x i8> @subr_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: subr_imm_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: subr z0.b, z0.b, #3 // =0x3 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 16 x i8> undef, i8 3, i32 0 |
| %imm.splat = shufflevector <vscale x 16 x i8> %imm, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %imm.splat, |
| <vscale x 16 x i8> %a) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @subr_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: subr_imm_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: subr z0.h, z0.h, #4 // =0x4 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 8 x i16> undef, i16 4, i32 0 |
| %imm.splat = shufflevector <vscale x 8 x i16> %imm, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %imm.splat, |
| <vscale x 8 x i16> %a) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @subr_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: subr_imm_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: subr z0.s, z0.s, #5 // =0x5 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 4 x i32> undef, i32 5, i32 0 |
| %imm.splat = shufflevector <vscale x 4 x i32> %imm, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %imm.splat, |
| <vscale x 4 x i32> %a) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @subr_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: subr_imm_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: subr z0.d, z0.d, #6 // =0x6 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 2 x i64> undef, i64 6, i32 0 |
| %imm.splat = shufflevector <vscale x 2 x i64> %imm, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %imm.splat, |
| <vscale x 2 x i64> %a) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; UABD |
| ; |
| |
| define <vscale x 16 x i8> @uabd_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { |
| ; CHECK-LABEL: uabd_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.b |
| ; CHECK-NEXT: uabd z0.b, p0/m, z0.b, z1.b |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uabd.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %b) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @uabd_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { |
| ; CHECK-LABEL: uabd_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.h |
| ; CHECK-NEXT: uabd z0.h, p0/m, z0.h, z1.h |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uabd.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %b) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @uabd_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { |
| ; CHECK-LABEL: uabd_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.s |
| ; CHECK-NEXT: uabd z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uabd.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @uabd_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { |
| ; CHECK-LABEL: uabd_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.d |
| ; CHECK-NEXT: uabd z0.d, p0/m, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uabd.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %b) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; UDIV |
| ; |
| |
| define <vscale x 4 x i32> @udiv_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { |
| ; CHECK-LABEL: udiv_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: udiv z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @udiv_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { |
| ; CHECK-LABEL: udiv_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: udiv z0.d, p0/m, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.udiv.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %b) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; UDIVR |
| ; |
| |
| define <vscale x 4 x i32> @udivr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { |
| ; CHECK-LABEL: udivr_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: udivr z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %b, |
| <vscale x 4 x i32> %a) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @udivr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { |
| ; CHECK-LABEL: udivr_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: udivr z0.d, p0/m, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.udiv.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %b, |
| <vscale x 2 x i64> %a) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; UMAX |
| ; |
| |
| define <vscale x 16 x i8> @umax_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { |
| ; CHECK-LABEL: umax_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umax z0.b, p0/m, z0.b, z1.b |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.umax.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %b) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @umax_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { |
| ; CHECK-LABEL: umax_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umax.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %b) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @umax_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { |
| ; CHECK-LABEL: umax_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umax.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @umax_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { |
| ; CHECK-LABEL: umax_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umax.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %b) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; UMAX (immediate) |
| ; |
| |
| define <vscale x 16 x i8> @umax_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: umax_imm_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umax z0.b, z0.b, #3 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 16 x i8> undef, i8 3, i32 0 |
| %imm.splat = shufflevector <vscale x 16 x i8> %imm, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.umax.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %imm.splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @umax_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: umax_imm_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umax z0.h, z0.h, #4 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 8 x i16> undef, i16 4, i32 0 |
| %imm.splat = shufflevector <vscale x 8 x i16> %imm, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umax.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %imm.splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @umax_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: umax_imm_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umax z0.s, z0.s, #5 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 4 x i32> undef, i32 5, i32 0 |
| %imm.splat = shufflevector <vscale x 4 x i32> %imm, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umax.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %imm.splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @umax_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: umax_imm_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umax z0.d, z0.d, #6 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 2 x i64> undef, i64 6, i32 0 |
| %imm.splat = shufflevector <vscale x 2 x i64> %imm, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umax.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %imm.splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; UMIN |
| ; |
| |
| define <vscale x 16 x i8> @umin_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { |
| ; CHECK-LABEL: umin_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umin z0.b, p0/m, z0.b, z1.b |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.umin.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %b) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @umin_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { |
| ; CHECK-LABEL: umin_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umin.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %b) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @umin_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { |
| ; CHECK-LABEL: umin_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umin.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @umin_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { |
| ; CHECK-LABEL: umin_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umin.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %b) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; UMIN (immediate) |
| ; |
| |
| define <vscale x 16 x i8> @umin_imm_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: umin_imm_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umin z0.b, z0.b, #3 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 16 x i8> undef, i8 3, i32 0 |
| %imm.splat = shufflevector <vscale x 16 x i8> %imm, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.umin.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %imm.splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @umin_imm_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: umin_imm_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umin z0.h, z0.h, #4 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 8 x i16> undef, i16 4, i32 0 |
| %imm.splat = shufflevector <vscale x 8 x i16> %imm, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umin.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %imm.splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @umin_imm_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: umin_imm_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umin z0.s, z0.s, #5 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 4 x i32> undef, i32 5, i32 0 |
| %imm.splat = shufflevector <vscale x 4 x i32> %imm, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umin.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %imm.splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @umin_imm_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: umin_imm_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umin z0.d, z0.d, #6 |
| ; CHECK-NEXT: ret |
| %imm = insertelement <vscale x 2 x i64> undef, i64 6, i32 0 |
| %imm.splat = shufflevector <vscale x 2 x i64> %imm, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umin.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %imm.splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; |
| ; UMULH |
| ; |
| |
| define <vscale x 16 x i8> @umulh_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a, <vscale x 16 x i8> %b) { |
| ; SVE1-LABEL: umulh_i8: |
| ; SVE1: // %bb.0: |
| ; SVE1-NEXT: umulh z0.b, p0/m, z0.b, z1.b |
| ; SVE1-NEXT: ret |
| ; |
| ; SVE2-LABEL: umulh_i8: |
| ; SVE2: // %bb.0: |
| ; SVE2-NEXT: umulh z0.b, z0.b, z1.b |
| ; SVE2-NEXT: ret |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.umulh.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %b) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @umulh_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a, <vscale x 8 x i16> %b) { |
| ; SVE1-LABEL: umulh_i16: |
| ; SVE1: // %bb.0: |
| ; SVE1-NEXT: umulh z0.h, p0/m, z0.h, z1.h |
| ; SVE1-NEXT: ret |
| ; |
| ; SVE2-LABEL: umulh_i16: |
| ; SVE2: // %bb.0: |
| ; SVE2-NEXT: umulh z0.h, z0.h, z1.h |
| ; SVE2-NEXT: ret |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umulh.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %b) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @umulh_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a, <vscale x 4 x i32> %b) { |
| ; SVE1-LABEL: umulh_i32: |
| ; SVE1: // %bb.0: |
| ; SVE1-NEXT: umulh z0.s, p0/m, z0.s, z1.s |
| ; SVE1-NEXT: ret |
| ; |
| ; SVE2-LABEL: umulh_i32: |
| ; SVE2: // %bb.0: |
| ; SVE2-NEXT: umulh z0.s, z0.s, z1.s |
| ; SVE2-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umulh.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @umulh_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a, <vscale x 2 x i64> %b) { |
| ; SVE1-LABEL: umulh_i64: |
| ; SVE1: // %bb.0: |
| ; SVE1-NEXT: umulh z0.d, p0/m, z0.d, z1.d |
| ; SVE1-NEXT: ret |
| ; |
| ; SVE2-LABEL: umulh_i64: |
| ; SVE2: // %bb.0: |
| ; SVE2-NEXT: umulh z0.d, z0.d, z1.d |
| ; SVE2-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umulh.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %b) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| |
| declare <vscale x 16 x i8> @llvm.aarch64.sve.add.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) |
| declare <vscale x 8 x i16> @llvm.aarch64.sve.add.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) |
| declare <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) |
| declare <vscale x 2 x i64> @llvm.aarch64.sve.add.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) |
| |
| declare <vscale x 16 x i8> @llvm.aarch64.sve.mla.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) |
| declare <vscale x 8 x i16> @llvm.aarch64.sve.mla.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) |
| declare <vscale x 4 x i32> @llvm.aarch64.sve.mla.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) |
| declare <vscale x 2 x i64> @llvm.aarch64.sve.mla.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) |
| |
| declare <vscale x 16 x i8> @llvm.aarch64.sve.mls.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>, <vscale x 16 x i8>) |
| declare <vscale x 8 x i16> @llvm.aarch64.sve.mls.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>, <vscale x 8 x i16>) |
| declare <vscale x 4 x i32> @llvm.aarch64.sve.mls.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>, <vscale x 4 x i32>) |
| declare <vscale x 2 x i64> @llvm.aarch64.sve.mls.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>, <vscale x 2 x i64>) |
| |
| declare <vscale x 16 x i8> @llvm.aarch64.sve.mul.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) |
| declare <vscale x 8 x i16> @llvm.aarch64.sve.mul.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) |
| declare <vscale x 4 x i32> @llvm.aarch64.sve.mul.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) |
| declare <vscale x 2 x i64> @llvm.aarch64.sve.mul.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) |
| |
| declare <vscale x 16 x i8> @llvm.aarch64.sve.sabd.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) |
| declare <vscale x 8 x i16> @llvm.aarch64.sve.sabd.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) |
| declare <vscale x 4 x i32> @llvm.aarch64.sve.sabd.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) |
| declare <vscale x 2 x i64> @llvm.aarch64.sve.sabd.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) |
| |
| declare <vscale x 4 x i32> @llvm.aarch64.sve.sdiv.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) |
| declare <vscale x 2 x i64> @llvm.aarch64.sve.sdiv.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) |
| |
| declare <vscale x 16 x i8> @llvm.aarch64.sve.smax.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) |
| declare <vscale x 8 x i16> @llvm.aarch64.sve.smax.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) |
| declare <vscale x 4 x i32> @llvm.aarch64.sve.smax.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) |
| declare <vscale x 2 x i64> @llvm.aarch64.sve.smax.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) |
| |
| declare <vscale x 16 x i8> @llvm.aarch64.sve.smin.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) |
| declare <vscale x 8 x i16> @llvm.aarch64.sve.smin.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) |
| declare <vscale x 4 x i32> @llvm.aarch64.sve.smin.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) |
| declare <vscale x 2 x i64> @llvm.aarch64.sve.smin.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) |
| |
| declare <vscale x 16 x i8> @llvm.aarch64.sve.smulh.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) |
| declare <vscale x 8 x i16> @llvm.aarch64.sve.smulh.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) |
| declare <vscale x 4 x i32> @llvm.aarch64.sve.smulh.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) |
| declare <vscale x 2 x i64> @llvm.aarch64.sve.smulh.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) |
| |
| declare <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) |
| declare <vscale x 8 x i16> @llvm.aarch64.sve.sub.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) |
| declare <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) |
| declare <vscale x 2 x i64> @llvm.aarch64.sve.sub.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) |
| |
| declare <vscale x 16 x i8> @llvm.aarch64.sve.uabd.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) |
| declare <vscale x 8 x i16> @llvm.aarch64.sve.uabd.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) |
| declare <vscale x 4 x i32> @llvm.aarch64.sve.uabd.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) |
| declare <vscale x 2 x i64> @llvm.aarch64.sve.uabd.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) |
| |
| declare <vscale x 4 x i32> @llvm.aarch64.sve.udiv.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) |
| declare <vscale x 2 x i64> @llvm.aarch64.sve.udiv.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) |
| |
| declare <vscale x 16 x i8> @llvm.aarch64.sve.umax.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) |
| declare <vscale x 8 x i16> @llvm.aarch64.sve.umax.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) |
| declare <vscale x 4 x i32> @llvm.aarch64.sve.umax.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) |
| declare <vscale x 2 x i64> @llvm.aarch64.sve.umax.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) |
| |
| declare <vscale x 16 x i8> @llvm.aarch64.sve.umin.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) |
| declare <vscale x 8 x i16> @llvm.aarch64.sve.umin.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) |
| declare <vscale x 4 x i32> @llvm.aarch64.sve.umin.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) |
| declare <vscale x 2 x i64> @llvm.aarch64.sve.umin.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) |
| |
| declare <vscale x 16 x i8> @llvm.aarch64.sve.umulh.u.nxv16i8(<vscale x 16 x i1>, <vscale x 16 x i8>, <vscale x 16 x i8>) |
| declare <vscale x 8 x i16> @llvm.aarch64.sve.umulh.u.nxv8i16(<vscale x 8 x i1>, <vscale x 8 x i16>, <vscale x 8 x i16>) |
| declare <vscale x 4 x i32> @llvm.aarch64.sve.umulh.u.nxv4i32(<vscale x 4 x i1>, <vscale x 4 x i32>, <vscale x 4 x i32>) |
| declare <vscale x 2 x i64> @llvm.aarch64.sve.umulh.u.nxv2i64(<vscale x 2 x i1>, <vscale x 2 x i64>, <vscale x 2 x i64>) |