| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| ; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s |
| |
| ; ADD |
| |
| define <vscale x 16 x i8> @add_i8(<vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: add_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: add z0.b, z0.b, #127 // =0x7f |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) |
| %elt = insertelement <vscale x 16 x i8> undef, i8 127, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.add.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @add_i16(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: add_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: add z0.h, z0.h, #127 // =0x7f |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %elt = insertelement <vscale x 8 x i16> undef, i16 127, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.add.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 8 x i16> @add_i16_out_of_range(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: add_i16_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: dupm z1.b, #0x1 |
| ; CHECK-NEXT: add z0.h, z0.h, z1.h |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %elt = insertelement <vscale x 8 x i16> undef, i16 257, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.add.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @add_i32(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: add_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: add z0.s, z0.s, #127 // =0x7f |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) |
| %elt = insertelement <vscale x 4 x i32> undef, i32 127, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 4 x i32> @add_i32_out_of_range(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: add_i32_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mov w8, #257 // =0x101 |
| ; CHECK-NEXT: mov z1.s, w8 |
| ; CHECK-NEXT: add z0.s, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) |
| %elt = insertelement <vscale x 4 x i32> undef, i32 257, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.add.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @add_i64(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: add_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: add z0.d, z0.d, #127 // =0x7f |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %elt = insertelement <vscale x 2 x i64> undef, i64 127, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.add.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| define <vscale x 2 x i64> @add_i64_out_of_range(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: add_i64_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mov w8, #257 // =0x101 |
| ; CHECK-NEXT: mov z1.d, x8 |
| ; CHECK-NEXT: add z0.d, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %elt = insertelement <vscale x 2 x i64> undef, i64 257, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.add.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; SUB |
| |
| define <vscale x 16 x i8> @sub_i8(<vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: sub_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.b, z0.b, #127 // =0x7f |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) |
| %elt = insertelement <vscale x 16 x i8> undef, i8 127, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sub.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @sub_i16(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: sub_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.h, z0.h, #127 // =0x7f |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %elt = insertelement <vscale x 8 x i16> undef, i16 127, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 8 x i16> @sub_i16_out_of_range(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: sub_i16_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: dupm z1.b, #0x1 |
| ; CHECK-NEXT: sub z0.h, z0.h, z1.h |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %elt = insertelement <vscale x 8 x i16> undef, i16 257, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sub.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @sub_i32(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: sub_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.s, z0.s, #127 // =0x7f |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) |
| %elt = insertelement <vscale x 4 x i32> undef, i32 127, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 4 x i32> @sub_i32_out_of_range(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: sub_i32_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mov w8, #257 // =0x101 |
| ; CHECK-NEXT: mov z1.s, w8 |
| ; CHECK-NEXT: sub z0.s, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) |
| %elt = insertelement <vscale x 4 x i32> undef, i32 257, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @sub_i64(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: sub_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.d, z0.d, #127 // =0x7f |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %elt = insertelement <vscale x 2 x i64> undef, i64 127, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| define <vscale x 2 x i64> @sub_i64_out_of_range(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: sub_i64_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mov w8, #257 // =0x101 |
| ; CHECK-NEXT: mov z1.d, x8 |
| ; CHECK-NEXT: sub z0.d, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %elt = insertelement <vscale x 2 x i64> undef, i64 257, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sub.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; As sub_i32 but where pg is i8 based and thus compatible for i32. |
| define <vscale x 4 x i32> @sub_i32_ptrue_all_b(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: sub_i32_ptrue_all_b: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.s, z0.s, #1 // =0x1 |
| ; CHECK-NEXT: ret |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; As sub_i32 but where pg is i16 based and thus compatible for i32. |
| define <vscale x 4 x i32> @sub_i32_ptrue_all_h(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: sub_i32_ptrue_all_h: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sub z0.s, z0.s, #1 // =0x1 |
| ; CHECK-NEXT: ret |
| %pg.h = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %pg.h) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sub.u.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; As sub_i32 but where pg is i64 based, which is not compatibile for i32 and |
| ; thus inactive lanes are important and the immediate form cannot be used. |
| define <vscale x 4 x i32> @sub_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: sub_i32_ptrue_all_d: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.d |
| ; CHECK-NEXT: mov z1.s, #1 // =0x1 |
| ; CHECK-NEXT: sub z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.sub.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; SUBR |
| |
| define <vscale x 16 x i8> @subr_i8(<vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: subr_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: subr z0.b, z0.b, #127 // =0x7f |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) |
| %elt = insertelement <vscale x 16 x i8> undef, i8 127, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.subr.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @subr_i16(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: subr_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: subr z0.h, z0.h, #127 // =0x7f |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %elt = insertelement <vscale x 8 x i16> undef, i16 127, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 8 x i16> @subr_i16_out_of_range(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: subr_i16_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: dupm z1.b, #0x1 |
| ; CHECK-NEXT: sub z0.h, z1.h, z0.h |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %elt = insertelement <vscale x 8 x i16> undef, i16 257, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.subr.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @subr_i32(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: subr_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: subr z0.s, z0.s, #127 // =0x7f |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) |
| %elt = insertelement <vscale x 4 x i32> undef, i32 127, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 4 x i32> @subr_i32_out_of_range(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: subr_i32_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mov w8, #257 // =0x101 |
| ; CHECK-NEXT: mov z1.s, w8 |
| ; CHECK-NEXT: sub z0.s, z1.s, z0.s |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) |
| %elt = insertelement <vscale x 4 x i32> undef, i32 257, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @subr_i64(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: subr_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: subr z0.d, z0.d, #127 // =0x7f |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %elt = insertelement <vscale x 2 x i64> undef, i64 127, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| define <vscale x 2 x i64> @subr_i64_out_of_range(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: subr_i64_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mov w8, #257 // =0x101 |
| ; CHECK-NEXT: mov z1.d, x8 |
| ; CHECK-NEXT: sub z0.d, z1.d, z0.d |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %elt = insertelement <vscale x 2 x i64> undef, i64 257, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.subr.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; As subr_i32 but where pg is i8 based and thus compatible for i32. |
| define <vscale x 4 x i32> @subr_i32_ptrue_all_b(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: subr_i32_ptrue_all_b: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: subr z0.s, z0.s, #1 // =0x1 |
| ; CHECK-NEXT: ret |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; As subr_i32 but where pg is i16 based and thus compatible for i32. |
| define <vscale x 4 x i32> @subr_i32_ptrue_all_h(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: subr_i32_ptrue_all_h: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: subr z0.s, z0.s, #1 // =0x1 |
| ; CHECK-NEXT: ret |
| %pg.h = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %pg.h) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; As subr_i32 but where pg is i64 based, which is not compatibile for i32 and |
| ; thus inactive lanes are important and the immediate form cannot be used. |
| define <vscale x 4 x i32> @subr_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: subr_i32_ptrue_all_d: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.d |
| ; CHECK-NEXT: mov z1.s, #1 // =0x1 |
| ; CHECK-NEXT: subr z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.subr.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; SMAX |
| |
| define <vscale x 16 x i8> @smax_i8(<vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: smax_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smax z0.b, z0.b, #-128 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) |
| %elt = insertelement <vscale x 16 x i8> undef, i8 -128, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.smax.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @smax_i16(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: smax_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smax z0.h, z0.h, #127 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %elt = insertelement <vscale x 8 x i16> undef, i16 127, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smax.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 8 x i16> @smax_i16_out_of_range(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: smax_i16_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.h |
| ; CHECK-NEXT: mov w8, #129 // =0x81 |
| ; CHECK-NEXT: mov z1.h, w8 |
| ; CHECK-NEXT: smax z0.h, p0/m, z0.h, z1.h |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %elt = insertelement <vscale x 8 x i16> undef, i16 129, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smax.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @smax_i32(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: smax_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smax z0.s, z0.s, #-128 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) |
| %elt = insertelement <vscale x 4 x i32> undef, i32 -128, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smax.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 4 x i32> @smax_i32_out_of_range(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: smax_i32_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.s |
| ; CHECK-NEXT: mov z1.s, #-129 // =0xffffffffffffff7f |
| ; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) |
| %elt = insertelement <vscale x 4 x i32> undef, i32 -129, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smax.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @smax_i64(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: smax_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smax z0.d, z0.d, #127 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %elt = insertelement <vscale x 2 x i64> undef, i64 127, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smax.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| define <vscale x 2 x i64> @smax_i64_out_of_range(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: smax_i64_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.d |
| ; CHECK-NEXT: mov z1.d, #65535 // =0xffff |
| ; CHECK-NEXT: smax z0.d, p0/m, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %elt = insertelement <vscale x 2 x i64> undef, i64 65535, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smax.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; As smax_i32 but where pg is i8 based and thus compatible for i32. |
| define <vscale x 4 x i32> @smax_i32_ptrue_all_b(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: smax_i32_ptrue_all_b: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smax z0.s, z0.s, #1 |
| ; CHECK-NEXT: ret |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smax.u.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; As smax_i32 but where pg is i16 based and thus compatible for i32. |
| define <vscale x 4 x i32> @smax_i32_ptrue_all_h(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: smax_i32_ptrue_all_h: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smax z0.s, z0.s, #1 |
| ; CHECK-NEXT: ret |
| %pg.h = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %pg.h) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smax.u.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; As smax_i32 but where pg is i64 based, which is not compatibile for i32 and |
| ; thus inactive lanes are important and the immediate form cannot be used. |
| define <vscale x 4 x i32> @smax_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: smax_i32_ptrue_all_d: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.d |
| ; CHECK-NEXT: mov z1.s, #1 // =0x1 |
| ; CHECK-NEXT: smax z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smax.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; SMIN |
| |
| define <vscale x 16 x i8> @smin_i8(<vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: smin_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smin z0.b, z0.b, #127 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) |
| %elt = insertelement <vscale x 16 x i8> undef, i8 127, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.smin.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @smin_i16(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: smin_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smin z0.h, z0.h, #-128 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %elt = insertelement <vscale x 8 x i16> undef, i16 -128, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smin.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 8 x i16> @smin_i16_out_of_range(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: smin_i16_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.h |
| ; CHECK-NEXT: mov z1.h, #-129 // =0xffffffffffffff7f |
| ; CHECK-NEXT: smin z0.h, p0/m, z0.h, z1.h |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %elt = insertelement <vscale x 8 x i16> undef, i16 -129, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.smin.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @smin_i32(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: smin_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smin z0.s, z0.s, #127 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) |
| %elt = insertelement <vscale x 4 x i32> undef, i32 127, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smin.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 4 x i32> @smin_i32_out_of_range(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: smin_i32_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.s |
| ; CHECK-NEXT: mov w8, #257 // =0x101 |
| ; CHECK-NEXT: mov z1.s, w8 |
| ; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) |
| %elt = insertelement <vscale x 4 x i32> undef, i32 257, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.smin.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| |
| define <vscale x 2 x i64> @smin_i64(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: smin_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smin z0.d, z0.d, #-128 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %elt = insertelement <vscale x 2 x i64> undef, i64 -128, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smin.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| define <vscale x 2 x i64> @smin_i64_out_of_range(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: smin_i64_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.d |
| ; CHECK-NEXT: mov z1.d, #-256 // =0xffffffffffffff00 |
| ; CHECK-NEXT: smin z0.d, p0/m, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %elt = insertelement <vscale x 2 x i64> undef, i64 -256, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.smin.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; As smin_i32 but where pg is i8 based and thus compatible for i32. |
| define <vscale x 4 x i32> @smin_i32_ptrue_all_b(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: smin_i32_ptrue_all_b: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smin z0.s, z0.s, #1 |
| ; CHECK-NEXT: ret |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smin.u.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; As smin_i32 but where pg is i16 based and thus compatible for i32. |
| define <vscale x 4 x i32> @smin_i32_ptrue_all_h(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: smin_i32_ptrue_all_h: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: smin z0.s, z0.s, #1 |
| ; CHECK-NEXT: ret |
| %pg.h = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %pg.h) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smin.u.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; As smin_i32 but where pg is i64 based, which is not compatibile for i32 and |
| ; thus inactive lanes are important and the immediate form cannot be used. |
| define <vscale x 4 x i32> @smin_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: smin_i32_ptrue_all_d: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.d |
| ; CHECK-NEXT: mov z1.s, #1 // =0x1 |
| ; CHECK-NEXT: smin z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.smin.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; UMAX |
| |
| define <vscale x 16 x i8> @umax_i8(<vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: umax_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umax z0.b, z0.b, #0 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) |
| %elt = insertelement <vscale x 16 x i8> undef, i8 0, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.umax.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @umax_i16(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: umax_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umax z0.h, z0.h, #255 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %elt = insertelement <vscale x 8 x i16> undef, i16 255, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umax.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 8 x i16> @umax_i16_out_of_range(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: umax_i16_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.h |
| ; CHECK-NEXT: dupm z1.b, #0x1 |
| ; CHECK-NEXT: umax z0.h, p0/m, z0.h, z1.h |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %elt = insertelement <vscale x 8 x i16> undef, i16 257, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umax.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @umax_i32(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: umax_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umax z0.s, z0.s, #0 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) |
| %elt = insertelement <vscale x 4 x i32> undef, i32 0, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umax.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 4 x i32> @umax_i32_out_of_range(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: umax_i32_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.s |
| ; CHECK-NEXT: mov w8, #257 // =0x101 |
| ; CHECK-NEXT: mov z1.s, w8 |
| ; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) |
| %elt = insertelement <vscale x 4 x i32> undef, i32 257, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umax.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @umax_i64(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: umax_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umax z0.d, z0.d, #255 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %elt = insertelement <vscale x 2 x i64> undef, i64 255, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umax.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| define <vscale x 2 x i64> @umax_i64_out_of_range(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: umax_i64_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.d |
| ; CHECK-NEXT: mov z1.d, #65535 // =0xffff |
| ; CHECK-NEXT: umax z0.d, p0/m, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %elt = insertelement <vscale x 2 x i64> undef, i64 65535, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umax.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; As umax_i32 but where pg is i8 based and thus compatible for i32. |
| define <vscale x 4 x i32> @umax_i32_ptrue_all_b(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: umax_i32_ptrue_all_b: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umax z0.s, z0.s, #1 |
| ; CHECK-NEXT: ret |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umax.u.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; As umax_i32 but where pg is i16 based and thus compatible for i32. |
| define <vscale x 4 x i32> @umax_i32_ptrue_all_h(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: umax_i32_ptrue_all_h: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umax z0.s, z0.s, #1 |
| ; CHECK-NEXT: ret |
| %pg.h = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %pg.h) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umax.u.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; As umax_i32 but where pg is i64 based, which is not compatibile for i32 and |
| ; thus inactive lanes are important and the immediate form cannot be used. |
| define <vscale x 4 x i32> @umax_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: umax_i32_ptrue_all_d: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.d |
| ; CHECK-NEXT: mov z1.s, #1 // =0x1 |
| ; CHECK-NEXT: umax z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umax.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; UMIN |
| |
| define <vscale x 16 x i8> @umin_i8(<vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: umin_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umin z0.b, z0.b, #255 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) |
| %elt = insertelement <vscale x 16 x i8> undef, i8 255, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.umin.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @umin_i16(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: umin_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umin z0.h, z0.h, #0 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %elt = insertelement <vscale x 8 x i16> undef, i16 0, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umin.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 8 x i16> @umin_i16_out_of_range(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: umin_i16_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.h |
| ; CHECK-NEXT: dupm z1.b, #0x1 |
| ; CHECK-NEXT: umin z0.h, p0/m, z0.h, z1.h |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %elt = insertelement <vscale x 8 x i16> undef, i16 257, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.umin.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @umin_i32(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: umin_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umin z0.s, z0.s, #255 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) |
| %elt = insertelement <vscale x 4 x i32> undef, i32 255, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umin.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 4 x i32> @umin_i32_out_of_range(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: umin_i32_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.s |
| ; CHECK-NEXT: mov w8, #257 // =0x101 |
| ; CHECK-NEXT: mov z1.s, w8 |
| ; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) |
| %elt = insertelement <vscale x 4 x i32> undef, i32 257, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.umin.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @umin_i64(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: umin_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umin z0.d, z0.d, #0 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %elt = insertelement <vscale x 2 x i64> undef, i64 0, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umin.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| define <vscale x 2 x i64> @umin_i64_out_of_range(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: umin_i64_out_of_range: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.d |
| ; CHECK-NEXT: mov z1.d, #65535 // =0xffff |
| ; CHECK-NEXT: umin z0.d, p0/m, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %elt = insertelement <vscale x 2 x i64> undef, i64 65535, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.umin.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; As umin_i32 but where pg is i8 based and thus compatible for i32. |
| define <vscale x 4 x i32> @umin_i32_ptrue_all_b(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: umin_i32_ptrue_all_b: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umin z0.s, z0.s, #1 |
| ; CHECK-NEXT: ret |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umin.u.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; As umin_i32 but where pg is i16 based and thus compatible for i32. |
| define <vscale x 4 x i32> @umin_i32_ptrue_all_h(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: umin_i32_ptrue_all_h: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: umin z0.s, z0.s, #1 |
| ; CHECK-NEXT: ret |
| %pg.h = tail call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv8i1(<vscale x 8 x i1> %pg.h) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umin.u.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; As umin_i32 but where pg is i64 based, which is not compatibile for i32 and |
| ; thus inactive lanes are important and the immediate form cannot be used. |
| define <vscale x 4 x i32> @umin_i32_ptrue_all_d(<vscale x 4 x i32> %a) #0 { |
| ; CHECK-LABEL: umin_i32_ptrue_all_d: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: ptrue p0.d |
| ; CHECK-NEXT: mov z1.s, #1 // =0x1 |
| ; CHECK-NEXT: umin z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %pg.d = tail call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %pg.b = tail call <vscale x 16 x i1> @llvm.aarch64.sve.convert.to.svbool.nxv2i1(<vscale x 2 x i1> %pg.d) |
| %pg.s = tail call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg.b) |
| %b = tail call <vscale x 4 x i32> @llvm.aarch64.sve.dup.x.nxv4i32(i32 1) |
| %out = tail call <vscale x 4 x i32> @llvm.aarch64.sve.umin.nxv4i32(<vscale x 4 x i1> %pg.s, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %b) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; SQADD |
| |
| define <vscale x 16 x i8> @sqadd_b_lowimm(<vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: sqadd_b_lowimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sqadd z0.b, z0.b, #27 // =0x1b |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 16 x i8> undef, i8 27, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqadd.x.nxv16i8(<vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @sqadd_h_lowimm(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: sqadd_h_lowimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sqadd z0.h, z0.h, #43 // =0x2b |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 8 x i16> undef, i16 43, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 8 x i16> @sqadd_h_highimm(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: sqadd_h_highimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sqadd z0.h, z0.h, #2048 // =0x800 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 8 x i16> undef, i16 2048, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqadd.x.nxv8i16(<vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @sqadd_s_lowimm(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: sqadd_s_lowimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sqadd z0.s, z0.s, #1 // =0x1 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 4 x i32> undef, i32 1, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 4 x i32> @sqadd_s_highimm(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: sqadd_s_highimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sqadd z0.s, z0.s, #8192 // =0x2000 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 4 x i32> undef, i32 8192, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqadd.x.nxv4i32(<vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @sqadd_d_lowimm(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: sqadd_d_lowimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sqadd z0.d, z0.d, #255 // =0xff |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 2 x i64> undef, i64 255, i32 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| define <vscale x 2 x i64> @sqadd_d_highimm(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: sqadd_d_highimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sqadd z0.d, z0.d, #65280 // =0xff00 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 2 x i64> undef, i64 65280, i32 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqadd.x.nxv2i64(<vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; SQSUB |
| |
| define <vscale x 16 x i8> @sqsub_b_lowimm(<vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: sqsub_b_lowimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sqsub z0.b, z0.b, #27 // =0x1b |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 16 x i8> undef, i8 27, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.sqsub.x.nxv16i8(<vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @sqsub_h_lowimm(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: sqsub_h_lowimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sqsub z0.h, z0.h, #43 // =0x2b |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 8 x i16> undef, i16 43, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 8 x i16> @sqsub_h_highimm(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: sqsub_h_highimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sqsub z0.h, z0.h, #2048 // =0x800 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 8 x i16> undef, i16 2048, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.sqsub.x.nxv8i16(<vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @sqsub_s_lowimm(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: sqsub_s_lowimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sqsub z0.s, z0.s, #1 // =0x1 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 4 x i32> undef, i32 1, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 4 x i32> @sqsub_s_highimm(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: sqsub_s_highimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sqsub z0.s, z0.s, #8192 // =0x2000 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 4 x i32> undef, i32 8192, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.sqsub.x.nxv4i32(<vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @sqsub_d_lowimm(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: sqsub_d_lowimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sqsub z0.d, z0.d, #255 // =0xff |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 2 x i64> undef, i64 255, i32 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| define <vscale x 2 x i64> @sqsub_d_highimm(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: sqsub_d_highimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: sqsub z0.d, z0.d, #65280 // =0xff00 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 2 x i64> undef, i64 65280, i32 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.sqsub.x.nxv2i64(<vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; UQADD |
| |
| define <vscale x 16 x i8> @uqadd_b_lowimm(<vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: uqadd_b_lowimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: uqadd z0.b, z0.b, #27 // =0x1b |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 16 x i8> undef, i8 27, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqadd.x.nxv16i8(<vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @uqadd_h_lowimm(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: uqadd_h_lowimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: uqadd z0.h, z0.h, #43 // =0x2b |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 8 x i16> undef, i16 43, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.x.nxv8i16(<vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 8 x i16> @uqadd_h_highimm(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: uqadd_h_highimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: uqadd z0.h, z0.h, #2048 // =0x800 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 8 x i16> undef, i16 2048, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqadd.x.nxv8i16(<vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @uqadd_s_lowimm(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: uqadd_s_lowimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: uqadd z0.s, z0.s, #1 // =0x1 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 4 x i32> undef, i32 1, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 4 x i32> @uqadd_s_highimm(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: uqadd_s_highimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: uqadd z0.s, z0.s, #8192 // =0x2000 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 4 x i32> undef, i32 8192, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqadd.x.nxv4i32(<vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @uqadd_d_lowimm(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: uqadd_d_lowimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: uqadd z0.d, z0.d, #255 // =0xff |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 2 x i64> undef, i64 255, i32 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| define <vscale x 2 x i64> @uqadd_d_highimm(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: uqadd_d_highimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: uqadd z0.d, z0.d, #65280 // =0xff00 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 2 x i64> undef, i64 65280, i32 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqadd.x.nxv2i64(<vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; UQSUB |
| |
| define <vscale x 16 x i8> @uqsub_b_lowimm(<vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: uqsub_b_lowimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: uqsub z0.b, z0.b, #27 // =0x1b |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 16 x i8> undef, i8 27, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.uqsub.x.nxv16i8(<vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @uqsub_h_lowimm(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: uqsub_h_lowimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: uqsub z0.h, z0.h, #43 // =0x2b |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 8 x i16> undef, i16 43, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 8 x i16> @uqsub_h_highimm(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: uqsub_h_highimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: uqsub z0.h, z0.h, #2048 // =0x800 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 8 x i16> undef, i16 2048, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.uqsub.x.nxv8i16(<vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @uqsub_s_lowimm(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: uqsub_s_lowimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: uqsub z0.s, z0.s, #1 // =0x1 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 4 x i32> undef, i32 1, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 4 x i32> @uqsub_s_highimm(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: uqsub_s_highimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: uqsub z0.s, z0.s, #8192 // =0x2000 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 4 x i32> undef, i32 8192, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.uqsub.x.nxv4i32(<vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @uqsub_d_lowimm(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: uqsub_d_lowimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: uqsub z0.d, z0.d, #255 // =0xff |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 2 x i64> undef, i64 255, i32 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| define <vscale x 2 x i64> @uqsub_d_highimm(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: uqsub_d_highimm: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: uqsub z0.d, z0.d, #65280 // =0xff00 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 2 x i64> undef, i64 65280, i32 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.uqsub.x.nxv2i64(<vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; ASR |
| |
| define <vscale x 16 x i8> @asr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: asr_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: asr z0.b, p0/m, z0.b, #8 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 16 x i8> undef, i8 9, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 16 x i8> @asr_i8_all_active(<vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: asr_i8_all_active: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: asr z0.b, z0.b, #8 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) |
| %elt = insertelement <vscale x 16 x i8> undef, i8 8, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| ; Ensure we don't match a right shift by zero to the immediate form. |
| define <vscale x 16 x i8> @asr_i8_too_small(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: asr_i8_too_small: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mov z1.b, #0 // =0x0 |
| ; CHECK-NEXT: asr z0.b, p0/m, z0.b, z1.b |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.asr.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> zeroinitializer) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @asr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: asr_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: asr z0.h, p0/m, z0.h, #16 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 8 x i16> undef, i16 17, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 8 x i16> @asr_i16_all_active(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: asr_i16_all_active: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: asr z0.h, z0.h, #16 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %elt = insertelement <vscale x 8 x i16> undef, i16 16, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| ; Ensure we don't match a right shift by zero to the immediate form. |
| define <vscale x 8 x i16> @asr_i16_too_small(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: asr_i16_too_small: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mov z1.h, #0 // =0x0 |
| ; CHECK-NEXT: asr z0.h, p0/m, z0.h, z1.h |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.asr.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> zeroinitializer) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @asr_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: asr_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: asr z0.s, p0/m, z0.s, #32 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 4 x i32> undef, i32 33, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 4 x i32> @asr_i32_all_active(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: asr_i32_all_active: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: asr z0.s, z0.s, #32 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) |
| %elt = insertelement <vscale x 4 x i32> undef, i32 32, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; Ensure we don't match a right shift by zero to the immediate form. |
| define <vscale x 4 x i32> @asr_i32_too_small(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: asr_i32_too_small: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mov z1.s, #0 // =0x0 |
| ; CHECK-NEXT: asr z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.asr.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> zeroinitializer) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @asr_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: asr_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: asr z0.d, p0/m, z0.d, #64 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 2 x i64> undef, i64 65, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| define <vscale x 2 x i64> @asr_i64_all_active(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: asr_i64_all_active: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: asr z0.d, z0.d, #64 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %elt = insertelement <vscale x 2 x i64> undef, i64 64, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; Ensure we don't match a right shift by zero to the immediate form. |
| define <vscale x 2 x i64> @asr_i64_too_small(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: asr_i64_too_small: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mov z1.d, #0 // =0x0 |
| ; CHECK-NEXT: asr z0.d, p0/m, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.asr.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> zeroinitializer) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; LSL |
| |
| define <vscale x 16 x i8> @lsl_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: lsl_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: lsl z0.b, p0/m, z0.b, #7 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 16 x i8> undef, i8 7, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 16 x i8> @lsl_i8_all_active(<vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: lsl_i8_all_active: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: lsl z0.b, z0.b, #7 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) |
| %elt = insertelement <vscale x 16 x i8> undef, i8 7, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| ; Ensure we don't match a left shift bigger than its bitwidth to the immediate form. |
| define <vscale x 16 x i8> @lsl_i8_too_big(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: lsl_i8_too_big: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mov z1.b, #8 // =0x8 |
| ; CHECK-NEXT: lsl z0.b, p0/m, z0.b, z1.b |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 16 x i8> undef, i8 8, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 16 x i8> @lsl_i8_zero(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: lsl_i8_zero: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: lsl z0.b, p0/m, z0.b, #0 |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsl.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> zeroinitializer) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @lsl_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: lsl_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: lsl z0.h, p0/m, z0.h, #15 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 8 x i16> undef, i16 15, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 8 x i16> @lsl_i16_all_active(<vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: lsl_i16_all_active: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: lsl z0.h, z0.h, #15 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 8 x i1> @llvm.aarch64.sve.ptrue.nxv8i1(i32 31) |
| %elt = insertelement <vscale x 8 x i16> undef, i16 15, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.u.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| ; Ensure we don't match a left shift bigger than its bitwidth to the immediate form. |
| define <vscale x 8 x i16> @lsl_i16_too_big(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: lsl_i16_too_big: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mov z1.h, #16 // =0x10 |
| ; CHECK-NEXT: lsl z0.h, p0/m, z0.h, z1.h |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 8 x i16> undef, i16 16, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x i16> undef, <vscale x 8 x i32> zeroinitializer |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> %splat) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 8 x i16> @lsl_i16_zero(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: lsl_i16_zero: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: lsl z0.h, p0/m, z0.h, #0 |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 8 x i16> @llvm.aarch64.sve.lsl.nxv8i16(<vscale x 8 x i1> %pg, |
| <vscale x 8 x i16> %a, |
| <vscale x 8 x i16> zeroinitializer) |
| ret <vscale x 8 x i16> %out |
| } |
| |
| define <vscale x 4 x i32> @lsl_i32(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: lsl_i32: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: lsl z0.s, p0/m, z0.s, #31 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 4 x i32> undef, i32 31, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 4 x i32> @lsl_i32_all_active(<vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: lsl_i32_all_active: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: lsl z0.s, z0.s, #31 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 4 x i1> @llvm.aarch64.sve.ptrue.nxv4i1(i32 31) |
| %elt = insertelement <vscale x 4 x i32> undef, i32 31, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.u.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| ; Ensure we don't match a left shift bigger than its bitwidth to the immediate form. |
| define <vscale x 4 x i32> @lsl_i32_too_big(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: lsl_i32_too_big: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mov z1.s, #32 // =0x20 |
| ; CHECK-NEXT: lsl z0.s, p0/m, z0.s, z1.s |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 4 x i32> undef, i32 32, i32 0 |
| %splat = shufflevector <vscale x 4 x i32> %elt, <vscale x 4 x i32> undef, <vscale x 4 x i32> zeroinitializer |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> %splat) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 4 x i32> @lsl_i32_zero(<vscale x 4 x i1> %pg, <vscale x 4 x i32> %a) { |
| ; CHECK-LABEL: lsl_i32_zero: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: lsl z0.s, p0/m, z0.s, #0 |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 4 x i32> @llvm.aarch64.sve.lsl.nxv4i32(<vscale x 4 x i1> %pg, |
| <vscale x 4 x i32> %a, |
| <vscale x 4 x i32> zeroinitializer) |
| ret <vscale x 4 x i32> %out |
| } |
| |
| define <vscale x 2 x i64> @lsl_i64(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: lsl_i64: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, #63 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 2 x i64> undef, i64 63, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| define <vscale x 2 x i64> @lsl_i64_all_active(<vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: lsl_i64_all_active: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: lsl z0.d, z0.d, #63 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 2 x i1> @llvm.aarch64.sve.ptrue.nxv2i1(i32 31) |
| %elt = insertelement <vscale x 2 x i64> undef, i64 63, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.u.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; Ensure we don't match a left shift bigger than its bitwidth to the immediate form. |
| define <vscale x 2 x i64> @lsl_i64_too_big(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: lsl_i64_too_big: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mov z1.d, #64 // =0x40 |
| ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, z1.d |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 2 x i64> undef, i64 64, i64 0 |
| %splat = shufflevector <vscale x 2 x i64> %elt, <vscale x 2 x i64> undef, <vscale x 2 x i32> zeroinitializer |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> %splat) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| define <vscale x 2 x i64> @lsl_i64_zero(<vscale x 2 x i1> %pg, <vscale x 2 x i64> %a) { |
| ; CHECK-LABEL: lsl_i64_zero: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: lsl z0.d, p0/m, z0.d, #0 |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 2 x i64> @llvm.aarch64.sve.lsl.nxv2i64(<vscale x 2 x i1> %pg, |
| <vscale x 2 x i64> %a, |
| <vscale x 2 x i64> zeroinitializer) |
| ret <vscale x 2 x i64> %out |
| } |
| |
| ; LSR |
| |
| define <vscale x 16 x i8> @lsr_i8(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: lsr_i8: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: lsr z0.b, p0/m, z0.b, #8 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 16 x i8> undef, i8 9, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 16 x i8> @lsr_i8_all_active(<vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: lsr_i8_all_active: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: lsr z0.b, z0.b, #8 |
| ; CHECK-NEXT: ret |
| %pg = call <vscale x 16 x i1> @llvm.aarch64.sve.ptrue.nxv16i1(i32 31) |
| %elt = insertelement <vscale x 16 x i8> undef, i8 8, i32 0 |
| %splat = shufflevector <vscale x 16 x i8> %elt, <vscale x 16 x i8> undef, <vscale x 16 x i32> zeroinitializer |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.u.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> %splat) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| ; Ensure we don't match a right shift by zero to the immediate form. |
| define <vscale x 16 x i8> @lsr_i8_too_small(<vscale x 16 x i1> %pg, <vscale x 16 x i8> %a) { |
| ; CHECK-LABEL: lsr_i8_too_small: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: mov z1.b, #0 // =0x0 |
| ; CHECK-NEXT: lsr z0.b, p0/m, z0.b, z1.b |
| ; CHECK-NEXT: ret |
| %out = call <vscale x 16 x i8> @llvm.aarch64.sve.lsr.nxv16i8(<vscale x 16 x i1> %pg, |
| <vscale x 16 x i8> %a, |
| <vscale x 16 x i8> zeroinitializer) |
| ret <vscale x 16 x i8> %out |
| } |
| |
| define <vscale x 8 x i16> @lsr_i16(<vscale x 8 x i1> %pg, <vscale x 8 x i16> %a) { |
| ; CHECK-LABEL: lsr_i16: |
| ; CHECK: // %bb.0: |
| ; CHECK-NEXT: lsr z0.h, p0/m, z0.h, #16 |
| ; CHECK-NEXT: ret |
| %elt = insertelement <vscale x 8 x i16> undef, i16 17, i32 0 |
| %splat = shufflevector <vscale x 8 x i16> %elt, <vscale x 8 x
|