; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx703 < %s | FileCheck -check-prefixes=GCN,GFX7 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx803 < %s | FileCheck -check-prefixes=GCN,GFX8 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx940 < %s | FileCheck -check-prefixes=GCN,GFX940 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1030 < %s | FileCheck -check-prefixes=GCN,GFX10 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX11 %s
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1200 < %s | FileCheck -check-prefixes=GCN,GFX12 %s

define float @v_maximum_f32(float %src0, float %src1) {
; GFX7-LABEL: v_maximum_f32:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX7-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX8-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX9-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_f32:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX940-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_f32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_f32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v0, v0, v1
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call float @llvm.maximum.f32(float %src0, float %src1)
  ret float %op
}

define float @v_maximum_f32__nnan(float %src0, float %src1) {
; GFX7-LABEL: v_maximum_f32__nnan:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_f32_e32 v0, v0, v1
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f32__nnan:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_max_f32_e32 v0, v0, v1
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_f32__nnan:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_max_f32_e32 v0, v0, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_f32__nnan:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_max_f32_e32 v0, v0, v1
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_f32__nnan:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_max_f32_e32 v0, v0, v1
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_f32__nnan:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_max_f32_e32 v0, v0, v1
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_f32__nnan:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v0, v0, v1
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call nnan float @llvm.maximum.f32(float %src0, float %src1)
  ret float %op
}

define float @v_maximum_f32__nsz(float %src0, float %src1) {
; GFX7-LABEL: v_maximum_f32__nsz:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX7-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f32__nsz:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX8-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_f32__nsz:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX9-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_f32__nsz:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX940-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_f32__nsz:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_f32__nsz:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_f32__nsz:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v0, v0, v1
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call nsz float @llvm.maximum.f32(float %src0, float %src1)
  ret float %op
}

define float @v_maximum_f32__nnan_nsz(float %src0, float %src1) {
; GFX7-LABEL: v_maximum_f32__nnan_nsz:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_f32_e32 v0, v0, v1
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f32__nnan_nsz:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_max_f32_e32 v0, v0, v1
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_f32__nnan_nsz:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_max_f32_e32 v0, v0, v1
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_f32__nnan_nsz:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_max_f32_e32 v0, v0, v1
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_f32__nnan_nsz:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_max_f32_e32 v0, v0, v1
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_f32__nnan_nsz:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_max_f32_e32 v0, v0, v1
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_f32__nnan_nsz:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v0, v0, v1
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call nnan nsz float @llvm.maximum.f32(float %src0, float %src1)
  ret float %op
}

define float @v_maximum_f32__nnan_src0(float %arg0, float %src1) {
; GFX7-LABEL: v_maximum_f32__nnan_src0:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_add_f32_e32 v0, 1.0, v0
; GFX7-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX7-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f32__nnan_src0:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_add_f32_e32 v0, 1.0, v0
; GFX8-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX8-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_f32__nnan_src0:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_add_f32_e32 v0, 1.0, v0
; GFX9-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX9-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_f32__nnan_src0:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_add_f32_e32 v0, 1.0, v0
; GFX940-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX940-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_f32__nnan_src0:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_add_f32_e32 v0, 1.0, v0
; GFX10-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_f32__nnan_src0:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_add_f32_e32 v0, 1.0, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v1
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_f32__nnan_src0:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_add_f32_e32 v0, 1.0, v0
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_maximum_f32 v0, v0, v1
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %src0 = fadd nnan float %arg0, 1.0
  %op = call float @llvm.maximum.f32(float %src0, float %src1)
  ret float %op
}

define float @v_maximum_f32__nnan_src1(float %src0, float %arg1) {
; GFX7-LABEL: v_maximum_f32__nnan_src1:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_add_f32_e32 v1, 1.0, v1
; GFX7-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX7-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_f32__nnan_src1:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_add_f32_e32 v1, 1.0, v1
; GFX8-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX8-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_f32__nnan_src1:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_add_f32_e32 v1, 1.0, v1
; GFX9-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX9-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_f32__nnan_src1:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_add_f32_e32 v1, 1.0, v1
; GFX940-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX940-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v0, v1
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v3, v2, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_f32__nnan_src1:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_add_f32_e32 v1, 1.0, v1
; GFX10-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v1
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_f32__nnan_src1:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_add_f32_e32 v1, 1.0, v1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_max_f32_e32 v2, v0, v1
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v1
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v2, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_f32__nnan_src1:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_add_f32_e32 v1, 1.0, v1
; GFX12-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX12-NEXT:    v_maximum_f32 v0, v0, v1
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %src1 = fadd nnan float %arg1, 1.0
  %op = call float @llvm.maximum.f32(float %src0, float %src1)
  ret float %op
}

define void @s_maximum_f32(float inreg %src0, float inreg %src1) {
; GFX7-LABEL: s_maximum_f32:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_mov_b32_e32 v0, s5
; GFX7-NEXT:    v_max_f32_e32 v1, s4, v0
; GFX7-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, s4, v0
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX7-NEXT:    ;;#ASMSTART
; GFX7-NEXT:    ; use v0
; GFX7-NEXT:    ;;#ASMEND
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: s_maximum_f32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_mov_b32_e32 v0, s5
; GFX8-NEXT:    v_max_f32_e32 v1, s4, v0
; GFX8-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, s4, v0
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX8-NEXT:    ;;#ASMSTART
; GFX8-NEXT:    ; use v0
; GFX8-NEXT:    ;;#ASMEND
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: s_maximum_f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v0, s5
; GFX9-NEXT:    v_max_f32_e32 v1, s4, v0
; GFX9-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, s4, v0
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX9-NEXT:    ;;#ASMSTART
; GFX9-NEXT:    ; use v0
; GFX9-NEXT:    ;;#ASMEND
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: s_maximum_f32:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_mov_b32_e32 v0, s1
; GFX940-NEXT:    v_max_f32_e32 v1, s0, v0
; GFX940-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, s0, v0
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v2, v1, vcc
; GFX940-NEXT:    ;;#ASMSTART
; GFX940-NEXT:    ; use v0
; GFX940-NEXT:    ;;#ASMEND
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: s_maximum_f32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_max_f32_e64 v0, s4, s5
; GFX10-NEXT:    v_cmp_o_f32_e64 vcc_lo, s4, s5
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX10-NEXT:    ;;#ASMSTART
; GFX10-NEXT:    ; use v0
; GFX10-NEXT:    ;;#ASMEND
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: s_maximum_f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_max_f32_e64 v0, s0, s1
; GFX11-NEXT:    v_cmp_o_f32_e64 vcc_lo, s0, s1
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX11-NEXT:    ;;#ASMSTART
; GFX11-NEXT:    ; use v0
; GFX11-NEXT:    ;;#ASMEND
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: s_maximum_f32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    s_maximum_f32 s0, s0, s1
; GFX12-NEXT:    ;;#ASMSTART
; GFX12-NEXT:    ; use s0
; GFX12-NEXT:    ;;#ASMEND
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call float @llvm.maximum.f32(float %src0, float %src1)
  call void asm sideeffect "; use $0", "s"(float %op)
  ret void
}

define <2 x float> @v_maximum_v2f32(<2 x float> %src0, <2 x float> %src1) {
; GFX7-LABEL: v_maximum_v2f32:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_legacy_f32_e32 v4, v0, v2
; GFX7-NEXT:    v_mov_b32_e32 v5, 0x7fc00000
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v2
; GFX7-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v2, v1, v3
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v1, v3
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v2f32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc
; GFX8-NEXT:    v_mov_b32_e32 v5, 0x7fc00000
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v2
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v3
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v3, v1, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v1, v3
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_v2f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc
; GFX9-NEXT:    v_mov_b32_e32 v5, 0x7fc00000
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v0, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v1, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v1, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_v2f32:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
; GFX940-NEXT:    v_mov_b32_e32 v5, 0x7fc00000
; GFX940-NEXT:    s_nop 0
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v0, v2
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v3
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v3, v1, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v1, v3
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v2f32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v2
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v3, v1, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v2
; GFX10-NEXT:    v_cndmask_b32_e32 v4, 0x7fc00000, v4, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v5, 0x7fc00000, v5, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v0, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v1, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v2, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v3, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v2f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v2
; GFX11-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v3
; GFX11-NEXT:    v_cndmask_b32_e32 v5, v3, v1, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_cndmask_b32_e32 v4, 0x7fc00000, v4, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v3
; GFX11-NEXT:    v_cndmask_b32_e32 v5, 0x7fc00000, v5, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v0, 64
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v1, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v2, 64
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v3, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v5
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v2f32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v0, v0, v2
; GFX12-NEXT:    v_maximum_f32 v1, v1, v3
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call <2 x float> @llvm.maximum.v2f32(<2 x float> %src0, <2 x float> %src1)
  ret <2 x float> %op
}

define <2 x float> @v_maximum_v2f32__nnan(<2 x float> %src0, <2 x float> %src1) {
; GFX7-LABEL: v_maximum_v2f32__nnan:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_legacy_f32_e32 v4, v0, v2
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v2, v1, v3
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v2f32__nnan:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v3
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v3, v1, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_v2f32__nnan:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v1, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_v2f32__nnan:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v3
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v3, v1, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v2f32__nnan:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v2
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v3, v1, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v0, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v1, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v2, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v3, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v2f32__nnan:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v2
; GFX11-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v3
; GFX11-NEXT:    v_cndmask_b32_e32 v5, v3, v1, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v0, 64
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v1, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v2, 64
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v2, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v3, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v1, v3, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v5
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v2f32__nnan:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v0, v0, v2
; GFX12-NEXT:    v_maximum_f32 v1, v1, v3
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call nnan <2 x float> @llvm.maximum.v2f32(<2 x float> %src0, <2 x float> %src1)
  ret <2 x float> %op
}

define <2 x float> @v_maximum_v2f32__nsz(<2 x float> %src0, <2 x float> %src1) {
; GFX7-LABEL: v_maximum_v2f32__nsz:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_legacy_f32_e32 v4, v0, v2
; GFX7-NEXT:    v_mov_b32_e32 v5, 0x7fc00000
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v2
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v2, v1, v3
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v1, v3
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v2f32__nsz:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc
; GFX8-NEXT:    v_mov_b32_e32 v5, 0x7fc00000
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v2
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v3
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v3, v1, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v1, v3
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_v2f32__nsz:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc
; GFX9-NEXT:    v_mov_b32_e32 v5, 0x7fc00000
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v0, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v1, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v1, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_v2f32__nsz:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
; GFX940-NEXT:    v_mov_b32_e32 v5, 0x7fc00000
; GFX940-NEXT:    s_nop 0
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v0, v2
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v5, v4, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v3
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v3, v1, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v1, v3
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v5, v2, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v2f32__nsz:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v2
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v3, v1, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v2
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v4, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v5, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v2f32__nsz:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v2
; GFX11-NEXT:    v_cndmask_b32_e32 v4, v2, v0, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v3
; GFX11-NEXT:    v_cndmask_b32_e32 v5, v3, v1, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v4, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v3
; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v5, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v2f32__nsz:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v0, v0, v2
; GFX12-NEXT:    v_maximum_f32 v1, v1, v3
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call nsz <2 x float> @llvm.maximum.v2f32(<2 x float> %src0, <2 x float> %src1)
  ret <2 x float> %op
}

define <2 x float> @v_maximum_v2f32__nnan_nsz(<2 x float> %src0, <2 x float> %src1) {
; GFX7-LABEL: v_maximum_v2f32__nnan_nsz:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v0, v2
; GFX7-NEXT:    v_max_legacy_f32_e32 v1, v1, v3
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v2f32__nnan_nsz:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v3
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_v2f32__nnan_nsz:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_v2f32__nnan_nsz:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v2
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v3
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v2f32__nnan_nsz:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v2
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v2f32__nnan_nsz:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v2
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v3
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v2f32__nnan_nsz:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v0, v0, v2
; GFX12-NEXT:    v_maximum_f32 v1, v1, v3
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call nnan nsz <2 x float> @llvm.maximum.v2f32(<2 x float> %src0, <2 x float> %src1)
  ret <2 x float> %op
}

define void @s_maximum_v2f32(<2 x float> inreg %src0, <2 x float> inreg %src1) {
; GFX7-LABEL: s_maximum_v2f32:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_mov_b32_e32 v0, s7
; GFX7-NEXT:    v_max_legacy_f32_e32 v1, s5, v0
; GFX7-NEXT:    v_mov_b32_e32 v2, 0x7fc00000
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, s5, v0
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX7-NEXT:    v_mov_b32_e32 v3, s5
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, s5, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v3, v1, v3, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, s7, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v1
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v1, v0, vcc
; GFX7-NEXT:    v_mov_b32_e32 v0, s6
; GFX7-NEXT:    v_max_legacy_f32_e32 v3, s4, v0
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, s4, v0
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v2, v3, vcc
; GFX7-NEXT:    v_mov_b32_e32 v3, s4
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, s4, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v3, v2, v3, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, s6, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX7-NEXT:    ;;#ASMSTART
; GFX7-NEXT:    ; use v[0:1]
; GFX7-NEXT:    ;;#ASMEND
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: s_maximum_v2f32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_mov_b32_e32 v0, s7
; GFX8-NEXT:    v_mov_b32_e32 v1, s5
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, s5, v0
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
; GFX8-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, s5, v0
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, s5, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, s7, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v2, v0, vcc
; GFX8-NEXT:    v_mov_b32_e32 v0, s6
; GFX8-NEXT:    v_mov_b32_e32 v2, s4
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v0, v2, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, s4, v0
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, s4, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, s6, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
; GFX8-NEXT:    ;;#ASMSTART
; GFX8-NEXT:    ; use v[0:1]
; GFX8-NEXT:    ;;#ASMEND
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: s_maximum_v2f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_mov_b32_e32 v0, s7
; GFX9-NEXT:    v_mov_b32_e32 v1, s5
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, s5, v0
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
; GFX9-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, s5, v0
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, s5, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, s7, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v2, v0, vcc
; GFX9-NEXT:    v_mov_b32_e32 v0, s6
; GFX9-NEXT:    v_mov_b32_e32 v2, s4
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, s4, v0
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v0, v2, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, s4, v0
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, s4, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, s6, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
; GFX9-NEXT:    ;;#ASMSTART
; GFX9-NEXT:    ; use v[0:1]
; GFX9-NEXT:    ;;#ASMEND
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: s_maximum_v2f32:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_mov_b32_e32 v0, s3
; GFX940-NEXT:    v_mov_b32_e32 v1, s1
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, s1, v0
; GFX940-NEXT:    v_mov_b32_e32 v3, 0x7fc00000
; GFX940-NEXT:    s_nop 0
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v0, v1, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, s1, v0
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, s1, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v2, v1, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, s3, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v1, v0, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v2
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v2, v0, vcc
; GFX940-NEXT:    v_mov_b32_e32 v0, s2
; GFX940-NEXT:    v_mov_b32_e32 v2, s0
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, s0, v0
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v0, v2, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, s0, v0
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v3, v4, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, s0, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, s2, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
; GFX940-NEXT:    ;;#ASMSTART
; GFX940-NEXT:    ; use v[0:1]
; GFX940-NEXT:    ;;#ASMEND
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: s_maximum_v2f32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_mov_b32_e32 v0, s5
; GFX10-NEXT:    v_cmp_gt_f32_e64 vcc_lo, s5, s7
; GFX10-NEXT:    v_mov_b32_e32 v1, s4
; GFX10-NEXT:    v_cmp_class_f32_e64 s8, s5, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v0, s7, v0, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e64 vcc_lo, s4, s6
; GFX10-NEXT:    v_cndmask_b32_e32 v1, s6, v1, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e64 vcc_lo, s5, s7
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e64 vcc_lo, s4, s6
; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v1, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e64 v1, v0, s5, s8
; GFX10-NEXT:    v_cmp_class_f32_e64 s5, s4, 64
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v0
; GFX10-NEXT:    v_cndmask_b32_e64 v3, v2, s4, s5
; GFX10-NEXT:    v_cmp_class_f32_e64 s4, s7, 64
; GFX10-NEXT:    v_cndmask_b32_e64 v1, v1, s7, s4
; GFX10-NEXT:    v_cmp_class_f32_e64 s4, s6, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc_lo
; GFX10-NEXT:    v_cndmask_b32_e64 v3, v3, s6, s4
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc_lo
; GFX10-NEXT:    ;;#ASMSTART
; GFX10-NEXT:    ; use v[0:1]
; GFX10-NEXT:    ;;#ASMEND
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: s_maximum_v2f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0
; GFX11-NEXT:    v_cmp_gt_f32_e64 vcc_lo, s1, s3
; GFX11-NEXT:    v_cmp_class_f32_e64 s4, s1, 64
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_3) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, s3, v0, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e64 vcc_lo, s0, s2
; GFX11-NEXT:    v_cndmask_b32_e32 v1, s2, v1, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e64 vcc_lo, s1, s3
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v0, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e64 vcc_lo, s0, s2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v1, vcc_lo
; GFX11-NEXT:    v_cndmask_b32_e64 v1, v0, s1, s4
; GFX11-NEXT:    v_cmp_class_f32_e64 s1, s0, 64
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v0
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_1)
; GFX11-NEXT:    v_cndmask_b32_e64 v3, v2, s0, s1
; GFX11-NEXT:    v_cmp_class_f32_e64 s0, s3, 64
; GFX11-NEXT:    v_cndmask_b32_e64 v1, v1, s3, s0
; GFX11-NEXT:    v_cmp_class_f32_e64 s0, s2, 64
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-NEXT:    v_cndmask_b32_e64 v3, v3, s2, s0
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v0, v1, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v2
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_3)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v2, v3, vcc_lo
; GFX11-NEXT:    ;;#ASMSTART
; GFX11-NEXT:    ; use v[0:1]
; GFX11-NEXT:    ;;#ASMEND
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: s_maximum_v2f32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    s_maximum_f32 s1, s1, s3
; GFX12-NEXT:    s_maximum_f32 s0, s0, s2
; GFX12-NEXT:    ;;#ASMSTART
; GFX12-NEXT:    ; use s[0:1]
; GFX12-NEXT:    ;;#ASMEND
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call <2 x float> @llvm.maximum.v2f32(<2 x float> %src0, <2 x float> %src1)
  call void asm sideeffect "; use $0", "s"(<2 x float> %op)
  ret void
}

define <3 x float> @v_maximum_v3f32(<3 x float> %src0, <3 x float> %src1) {
; GFX7-LABEL: v_maximum_v3f32:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_legacy_f32_e32 v6, v0, v3
; GFX7-NEXT:    v_mov_b32_e32 v7, 0x7fc00000
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v3
; GFX7-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v6
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v3, v1, v4
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v1, v4
; GFX7-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v3, v2, v5
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v2, v5
; GFX7-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v3f32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v3
; GFX8-NEXT:    v_cndmask_b32_e32 v6, v3, v0, vcc
; GFX8-NEXT:    v_mov_b32_e32 v7, 0x7fc00000
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v3
; GFX8-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v6
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v4, v1, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v1, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v5
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v5, v2, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v2, v5
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_v3f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v3, v0, vcc
; GFX9-NEXT:    v_mov_b32_e32 v7, 0x7fc00000
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v0, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v6
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v1, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v1, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v5, v2, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v2, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_v3f32:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v3
; GFX940-NEXT:    v_mov_b32_e32 v7, 0x7fc00000
; GFX940-NEXT:    s_nop 0
; GFX940-NEXT:    v_cndmask_b32_e32 v6, v3, v0, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v0, v3
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v6, v7, v6, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v6
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v4, v1, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v1, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v5
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v5, v2, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v2, v5
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v3f32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v6, v3, v0, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v4, v1, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v5, v2, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v6, 0x7fc00000, v6, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v7, 0x7fc00000, v7, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v8, 0x7fc00000, v8, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v0, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v1, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v2, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v3, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v4, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v5, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v3f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v3
; GFX11-NEXT:    v_cndmask_b32_e32 v6, v3, v0, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v4
; GFX11-NEXT:    v_cndmask_b32_e32 v7, v4, v1, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v5
; GFX11-NEXT:    v_cndmask_b32_e32 v8, v5, v2, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v3
; GFX11-NEXT:    v_cndmask_b32_e32 v6, 0x7fc00000, v6, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v4
; GFX11-NEXT:    v_cndmask_b32_e32 v7, 0x7fc00000, v7, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v5
; GFX11-NEXT:    v_cndmask_b32_e32 v8, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v0, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v1, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v2, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v3, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v4, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v5, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v3f32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v0, v0, v3
; GFX12-NEXT:    v_maximum_f32 v1, v1, v4
; GFX12-NEXT:    v_maximum_f32 v2, v2, v5
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call <3 x float> @llvm.maximum.v3f32(<3 x float> %src0, <3 x float> %src1)
  ret <3 x float> %op
}

define <3 x float> @v_maximum_v3f32__nnan(<3 x float> %src0, <3 x float> %src1) {
; GFX7-LABEL: v_maximum_v3f32__nnan:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_legacy_f32_e32 v6, v0, v3
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v6
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v3, v1, v4
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v3, v2, v5
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v3f32__nnan:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v3
; GFX8-NEXT:    v_cndmask_b32_e32 v6, v3, v0, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v6
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v4, v1, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v5
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v5, v2, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_v3f32__nnan:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v3, v0, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v6
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v1, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v5, v2, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_v3f32__nnan:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v3
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v6, v3, v0, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v6
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v4, v1, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v3, v1, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v5
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v5, v2, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v3
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v3, v2, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v3f32__nnan:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v6, v3, v0, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v4, v1, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v5, v2, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v0, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v1, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v2, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v3, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v4, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v5, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v3f32__nnan:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v3
; GFX11-NEXT:    v_cndmask_b32_e32 v6, v3, v0, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v4
; GFX11-NEXT:    v_cndmask_b32_e32 v7, v4, v1, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v5
; GFX11-NEXT:    v_cndmask_b32_e32 v8, v5, v2, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v0, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v1, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v2, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v3, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v3, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v4, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v5, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v2, v5, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v6
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v6, v0, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v7
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v7, v1, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v3f32__nnan:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v0, v0, v3
; GFX12-NEXT:    v_maximum_f32 v1, v1, v4
; GFX12-NEXT:    v_maximum_f32 v2, v2, v5
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call nnan <3 x float> @llvm.maximum.v3f32(<3 x float> %src0, <3 x float> %src1)
  ret <3 x float> %op
}

define <3 x float> @v_maximum_v3f32__nsz(<3 x float> %src0, <3 x float> %src1) {
; GFX7-LABEL: v_maximum_v3f32__nsz:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_legacy_f32_e32 v6, v0, v3
; GFX7-NEXT:    v_mov_b32_e32 v7, 0x7fc00000
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v3
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v7, v6, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v3, v1, v4
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v1, v4
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v7, v3, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v3, v2, v5
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v2, v5
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v3f32__nsz:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v3
; GFX8-NEXT:    v_cndmask_b32_e32 v6, v3, v0, vcc
; GFX8-NEXT:    v_mov_b32_e32 v7, 0x7fc00000
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v3
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v7, v6, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v4, v1, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v1, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v7, v3, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v5
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v5, v2, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v2, v5
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_v3f32__nsz:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v3, v0, vcc
; GFX9-NEXT:    v_mov_b32_e32 v7, 0x7fc00000
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v0, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v7, v6, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v1, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v1, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v7, v3, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v5, v2, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v2, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_v3f32__nsz:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v3
; GFX940-NEXT:    v_mov_b32_e32 v7, 0x7fc00000
; GFX940-NEXT:    s_nop 0
; GFX940-NEXT:    v_cndmask_b32_e32 v6, v3, v0, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v0, v3
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v7, v6, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v4, v1, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v1, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v7, v3, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v5
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v5, v2, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v2, v5
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v7, v3, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v3f32__nsz:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v6, v3, v0, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v4, v1, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v5, v2, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v6, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v7, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v3f32__nsz:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v3
; GFX11-NEXT:    v_cndmask_b32_e32 v6, v3, v0, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v4
; GFX11-NEXT:    v_cndmask_b32_e32 v7, v4, v1, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v5
; GFX11-NEXT:    v_cndmask_b32_e32 v8, v5, v2, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v3
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v6, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v4
; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v7, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v5
; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v3f32__nsz:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v0, v0, v3
; GFX12-NEXT:    v_maximum_f32 v1, v1, v4
; GFX12-NEXT:    v_maximum_f32 v2, v2, v5
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call nsz <3 x float> @llvm.maximum.v3f32(<3 x float> %src0, <3 x float> %src1)
  ret <3 x float> %op
}

define <3 x float> @v_maximum_v3f32__nnan_nsz(<3 x float> %src0, <3 x float> %src1) {
; GFX7-LABEL: v_maximum_v3f32__nnan_nsz:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v0, v3
; GFX7-NEXT:    v_max_legacy_f32_e32 v1, v1, v4
; GFX7-NEXT:    v_max_legacy_f32_e32 v2, v2, v5
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v3f32__nnan_nsz:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v3
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v5
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_v3f32__nnan_nsz:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v3
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_v3f32__nnan_nsz:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v3
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v5
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v3f32__nnan_nsz:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v3
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v3f32__nnan_nsz:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v3
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v3, v0, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v4
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v5
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v5, v2, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v3f32__nnan_nsz:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v0, v0, v3
; GFX12-NEXT:    v_maximum_f32 v1, v1, v4
; GFX12-NEXT:    v_maximum_f32 v2, v2, v5
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call nnan nsz <3 x float> @llvm.maximum.v3f32(<3 x float> %src0, <3 x float> %src1)
  ret <3 x float> %op
}

define <4 x float> @v_maximum_v4f32(<4 x float> %src0, <4 x float> %src1) {
; GFX7-LABEL: v_maximum_v4f32:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_legacy_f32_e32 v8, v0, v4
; GFX7-NEXT:    v_mov_b32_e32 v9, 0x7fc00000
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v4
; GFX7-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v4, v1, v5
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v1, v5
; GFX7-NEXT:    v_cndmask_b32_e32 v4, v9, v4, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v4, v2, v6
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v2, v6
; GFX7-NEXT:    v_cndmask_b32_e32 v4, v9, v4, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v6, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v4, v3, v7
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v3, v7
; GFX7-NEXT:    v_cndmask_b32_e32 v4, v9, v4, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v7, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX7-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v4f32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v4, v0, vcc
; GFX8-NEXT:    v_mov_b32_e32 v9, 0x7fc00000
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v5
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v5, v1, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v1, v5
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v9, v4, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v6
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v6, v2, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v2, v6
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v9, v4, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v6, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v7
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v7, v3, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v3, v7
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v9, v4, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v7, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_v4f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v4, v0, vcc
; GFX9-NEXT:    v_mov_b32_e32 v9, 0x7fc00000
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v0, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v5, v1, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v1, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v9, v4, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v6
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v6, v2, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v2, v6
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v9, v4, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v6, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v7
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v7, v3, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v3, v7
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v9, v4, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v7, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_v4f32:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v4
; GFX940-NEXT:    v_mov_b32_e32 v9, 0x7fc00000
; GFX940-NEXT:    s_nop 0
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v4, v0, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v0, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v9, v8, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v5
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v5, v1, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v1, v5
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v9, v4, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v6
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v6, v2, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v2, v6
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v9, v4, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v6, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v7
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v7, v3, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v3, v7
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v9, v4, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v7, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v4f32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v4, v0, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v8, 0x7fc00000, v8, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v0, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v9, v5, v1, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v6
; GFX10-NEXT:    v_cndmask_b32_e32 v10, v6, v2, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v4, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v7
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v7, v3, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v9, 0x7fc00000, v9, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v6
; GFX10-NEXT:    v_cndmask_b32_e32 v8, 0x7fc00000, v10, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v3, v7
; GFX10-NEXT:    v_cndmask_b32_e32 v4, 0x7fc00000, v4, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v1, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v9, v1, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v2, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v3, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v5, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v6, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v7, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v9, v1, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v4f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v4
; GFX11-NEXT:    v_cndmask_b32_e32 v8, v4, v0, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_cndmask_b32_e32 v8, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v0, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v5
; GFX11-NEXT:    v_cndmask_b32_e32 v9, v5, v1, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v6
; GFX11-NEXT:    v_cndmask_b32_e32 v10, v6, v2, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v4, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v7
; GFX11-NEXT:    v_cndmask_b32_e32 v4, v7, v3, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v5
; GFX11-NEXT:    v_cndmask_b32_e32 v9, 0x7fc00000, v9, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v6
; GFX11-NEXT:    v_cndmask_b32_e32 v8, 0x7fc00000, v10, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v3, v7
; GFX11-NEXT:    v_cndmask_b32_e32 v4, 0x7fc00000, v4, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v1, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v9, v1, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v2, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v3, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v5, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v6, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v7, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v9, v1, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v4
; GFX11-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v4f32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v0, v0, v4
; GFX12-NEXT:    v_maximum_f32 v1, v1, v5
; GFX12-NEXT:    v_maximum_f32 v2, v2, v6
; GFX12-NEXT:    v_maximum_f32 v3, v3, v7
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call <4 x float> @llvm.maximum.v4f32(<4 x float> %src0, <4 x float> %src1)
  ret <4 x float> %op
}

define <4 x float> @v_maximum_v4f32__nnan(<4 x float> %src0, <4 x float> %src1) {
; GFX7-LABEL: v_maximum_v4f32__nnan:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_legacy_f32_e32 v8, v0, v4
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v4, v1, v5
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v4, v2, v6
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v6, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v4, v3, v7
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v7, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX7-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v4f32__nnan:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v4, v0, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v5
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v5, v1, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v6
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v6, v2, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v6, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v7
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v7, v3, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v7, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_v4f32__nnan:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v4, v0, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v5, v1, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v6
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v6, v2, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v6, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v7
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v7, v3, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v7, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_v4f32__nnan:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v4, v0, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v5
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v5, v1, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v6
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v6, v2, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v6, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v4, v2, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v7
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v7, v3, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v7, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v4, v3, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v4f32__nnan:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v4, v0, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v0, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v4, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v5, v1, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v6
; GFX10-NEXT:    v_cndmask_b32_e32 v9, v6, v2, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v7
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v7, v3, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v1, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v2, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v3, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v5, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v6, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v7, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v4f32__nnan:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v4
; GFX11-NEXT:    v_cndmask_b32_e32 v8, v4, v0, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v0, 64
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(VALU_DEP_2)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v4, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v4, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v5
; GFX11-NEXT:    v_cndmask_b32_e32 v4, v5, v1, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v6
; GFX11-NEXT:    v_cndmask_b32_e32 v9, v6, v2, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v8, v0, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v7
; GFX11-NEXT:    v_cndmask_b32_e32 v8, v7, v3, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v1, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v2, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v3, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v5, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v1, v5, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v6, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v2, v6, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v7, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v3, v3, v7, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v4
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v4, v1, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v9, v2, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX11-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v4f32__nnan:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v0, v0, v4
; GFX12-NEXT:    v_maximum_f32 v1, v1, v5
; GFX12-NEXT:    v_maximum_f32 v2, v2, v6
; GFX12-NEXT:    v_maximum_f32 v3, v3, v7
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call nnan <4 x float> @llvm.maximum.v4f32(<4 x float> %src0, <4 x float> %src1)
  ret <4 x float> %op
}

define <4 x float> @v_maximum_v4f32__nsz(<4 x float> %src0, <4 x float> %src1) {
; GFX7-LABEL: v_maximum_v4f32__nsz:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_legacy_f32_e32 v8, v0, v4
; GFX7-NEXT:    v_mov_b32_e32 v9, 0x7fc00000
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v4
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v9, v8, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v4, v1, v5
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v1, v5
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v4, v2, v6
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v2, v6
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v9, v4, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v4, v3, v7
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v3, v7
; GFX7-NEXT:    v_cndmask_b32_e32 v3, v9, v4, vcc
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v4f32__nsz:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v4, v0, vcc
; GFX8-NEXT:    v_mov_b32_e32 v9, 0x7fc00000
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v9, v8, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v5
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v5, v1, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v1, v5
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v6
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v6, v2, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v2, v6
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v9, v4, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v7
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v7, v3, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v3, v7
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v9, v4, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_v4f32__nsz:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v4, v0, vcc
; GFX9-NEXT:    v_mov_b32_e32 v9, 0x7fc00000
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v0, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v9, v8, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v5, v1, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v1, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v6
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v6, v2, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v2, v6
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v9, v4, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v7
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v7, v3, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v3, v7
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v9, v4, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_v4f32__nsz:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v4
; GFX940-NEXT:    v_mov_b32_e32 v9, 0x7fc00000
; GFX940-NEXT:    s_nop 0
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v4, v0, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v0, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v9, v8, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v5
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v5, v1, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v1, v5
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v9, v4, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v6
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v6, v2, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v2, v6
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v9, v4, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v7
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v7, v3, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v3, v7
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v9, v4, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v4f32__nsz:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v4, v0, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v5, v1, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v6
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v6, v2, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v7
; GFX10-NEXT:    v_cndmask_b32_e32 v9, v7, v3, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v6
; GFX10-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v3, v7
; GFX10-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v9, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v4f32__nsz:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v4
; GFX11-NEXT:    v_cndmask_b32_e32 v8, v4, v0, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v4
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_2)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v5
; GFX11-NEXT:    v_cndmask_b32_e32 v4, v5, v1, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v6
; GFX11-NEXT:    v_cndmask_b32_e32 v8, v6, v2, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v7
; GFX11-NEXT:    v_cndmask_b32_e32 v9, v7, v3, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v5
; GFX11-NEXT:    v_cndmask_b32_e32 v1, 0x7fc00000, v4, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v6
; GFX11-NEXT:    v_cndmask_b32_e32 v2, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v3, v7
; GFX11-NEXT:    v_cndmask_b32_e32 v3, 0x7fc00000, v9, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v4f32__nsz:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v0, v0, v4
; GFX12-NEXT:    v_maximum_f32 v1, v1, v5
; GFX12-NEXT:    v_maximum_f32 v2, v2, v6
; GFX12-NEXT:    v_maximum_f32 v3, v3, v7
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call nsz <4 x float> @llvm.maximum.v4f32(<4 x float> %src0, <4 x float> %src1)
  ret <4 x float> %op
}

define <4 x float> @v_maximum_v4f32__nnan_nsz(<4 x float> %src0, <4 x float> %src1) {
; GFX7-LABEL: v_maximum_v4f32__nnan_nsz:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_legacy_f32_e32 v0, v0, v4
; GFX7-NEXT:    v_max_legacy_f32_e32 v1, v1, v5
; GFX7-NEXT:    v_max_legacy_f32_e32 v2, v2, v6
; GFX7-NEXT:    v_max_legacy_f32_e32 v3, v3, v7
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v4f32__nnan_nsz:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v4
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v5
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v6
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v7
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_v4f32__nnan_nsz:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v4
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v5
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v6
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v7
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_v4f32__nnan_nsz:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v4
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v5
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v6
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v7
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v4f32__nnan_nsz:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v4
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v5
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v6
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v7
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v4f32__nnan_nsz:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v4
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v4, v0, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v5
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v5, v1, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v6
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v6, v2, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v7
; GFX11-NEXT:    v_cndmask_b32_e32 v3, v7, v3, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v4f32__nnan_nsz:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v0, v0, v4
; GFX12-NEXT:    v_maximum_f32 v1, v1, v5
; GFX12-NEXT:    v_maximum_f32 v2, v2, v6
; GFX12-NEXT:    v_maximum_f32 v3, v3, v7
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call nnan nsz <4 x float> @llvm.maximum.v4f32(<4 x float> %src0, <4 x float> %src1)
  ret <4 x float> %op
}

define <8 x float> @v_maximum_v8f32(<8 x float> %src0, <8 x float> %src1) {
; GFX7-LABEL: v_maximum_v8f32:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_legacy_f32_e32 v16, v0, v8
; GFX7-NEXT:    v_mov_b32_e32 v17, 0x7fc00000
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v8
; GFX7-NEXT:    v_cndmask_b32_e32 v16, v17, v16, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v8, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v8, v1, v9
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v1, v9
; GFX7-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v9, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v8, v2, v10
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v2, v10
; GFX7-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v10, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v8, v3, v11
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v3, v11
; GFX7-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v11, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX7-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v8, v4, v12
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v4, v12
; GFX7-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v12, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX7-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v8, v5, v13
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v5, v13
; GFX7-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v13, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX7-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v8, v6, v14
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v6, v14
; GFX7-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v6, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v14, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX7-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v8, v7, v15
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v7, v15
; GFX7-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v7, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v15, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v7, v7, v15, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX7-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v8f32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v8
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v8, v0, vcc
; GFX8-NEXT:    v_mov_b32_e32 v17, 0x7fc00000
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v8
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v17, v16, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v8, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v9
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v9, v1, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v1, v9
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v9, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v10
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v10, v2, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v2, v10
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v10, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v11
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v11, v3, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v3, v11
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v11, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v4, v12
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v12, v4, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v4, v12
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v12, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v5, v13
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v13, v5, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v5, v13
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v13, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX8-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v6, v14
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v14, v6, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v6, v14
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v6, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v14, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX8-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v7, v15
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v15, v7, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v7, v15
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v7, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v15, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v7, v7, v15, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX8-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_v8f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v8
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v8, v0, vcc
; GFX9-NEXT:    v_mov_b32_e32 v17, 0x7fc00000
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v0, v8
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v17, v16, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v8, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v9
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v9, v1, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v1, v9
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v9, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v10
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v10, v2, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v2, v10
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v10, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v11
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v11, v3, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v3, v11
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v11, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v4, v12
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v12, v4, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v4, v12
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v12, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v5, v13
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v13, v5, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v5, v13
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v13, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v6, v14
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v14, v6, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v6, v14
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v6, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v14, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v7, v15
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v15, v7, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v7, v15
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v7, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v15, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v15, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_v8f32:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v8
; GFX940-NEXT:    v_mov_b32_e32 v17, 0x7fc00000
; GFX940-NEXT:    s_nop 0
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v8, v0, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v0, v8
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v17, v16, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v8, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v9
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v9, v1, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v1, v9
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v9, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v8, v1, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v10
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v10, v2, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v2, v10
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v10, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v11
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v11, v3, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v3, v11
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v11, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v8, v3, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v4, v12
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v12, v4, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v4, v12
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v12, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v8, v4, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v5, v13
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v13, v5, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v5, v13
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v13, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v6, v14
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v14, v6, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v6, v14
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v6, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v14, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v6, v8, v6, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v7, v15
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v15, v7, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v7, v15
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v17, v8, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v7, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v15, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v7, v7, v15, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v8
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v7, v8, v7, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v8f32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v8
; GFX10-NEXT:    v_cndmask_b32_e32 v16, v8, v0, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v9
; GFX10-NEXT:    v_cndmask_b32_e32 v17, v9, v1, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v8
; GFX10-NEXT:    v_cndmask_b32_e32 v16, 0x7fc00000, v16, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v9
; GFX10-NEXT:    v_cndmask_b32_e32 v17, 0x7fc00000, v17, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v0, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v16, v0, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v1, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v17, v1, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v8, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v9, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v16
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v16, v0, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v17
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v17, v1, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v10
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v10, v2, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v11
; GFX10-NEXT:    v_cndmask_b32_e32 v9, v11, v3, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v4, v12
; GFX10-NEXT:    v_cndmask_b32_e32 v16, v12, v4, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v10
; GFX10-NEXT:    v_cndmask_b32_e32 v8, 0x7fc00000, v8, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v3, v11
; GFX10-NEXT:    v_cndmask_b32_e32 v9, 0x7fc00000, v9, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v4, v12
; GFX10-NEXT:    v_cndmask_b32_e32 v16, 0x7fc00000, v16, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v2, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v3, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v4, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v16, v4, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v10, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v11, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v12, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v16
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v16, v4, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v5, v13
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v13, v5, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v6, v14
; GFX10-NEXT:    v_cndmask_b32_e32 v9, v14, v6, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v7, v15
; GFX10-NEXT:    v_cndmask_b32_e32 v10, v15, v7, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v5, v13
; GFX10-NEXT:    v_cndmask_b32_e32 v8, 0x7fc00000, v8, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v6, v14
; GFX10-NEXT:    v_cndmask_b32_e32 v9, 0x7fc00000, v9, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v7, v15
; GFX10-NEXT:    v_cndmask_b32_e32 v10, 0x7fc00000, v10, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v5, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v6, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v6, v9, v6, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v7, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v10, v7, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v13, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v14, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v15, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v15, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX10-NEXT:    v_cndmask_b32_e32 v6, v9, v6, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v10
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v10, v7, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v8f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v8
; GFX11-NEXT:    v_cndmask_b32_e32 v16, v8, v0, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v9
; GFX11-NEXT:    v_cndmask_b32_e32 v17, v9, v1, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v8
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_cndmask_b32_e32 v16, 0x7fc00000, v16, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v9
; GFX11-NEXT:    v_cndmask_b32_e32 v17, 0x7fc00000, v17, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v0, 64
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v16, v0, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v1, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v17, v1, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v8, 64
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v8, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v9, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v1, v9, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v16
; GFX11-NEXT:    s_delay_alu instid0(VALU_DEP_4) | instskip(SKIP_1) | instid1(VALU_DEP_4)
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v16, v0, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v17
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v17, v1, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v10
; GFX11-NEXT:    v_cndmask_b32_e32 v8, v10, v2, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v11
; GFX11-NEXT:    v_cndmask_b32_e32 v9, v11, v3, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v4, v12
; GFX11-NEXT:    v_cndmask_b32_e32 v16, v12, v4, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v10
; GFX11-NEXT:    v_cndmask_b32_e32 v8, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v3, v11
; GFX11-NEXT:    v_cndmask_b32_e32 v9, 0x7fc00000, v9, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v4, v12
; GFX11-NEXT:    v_cndmask_b32_e32 v16, 0x7fc00000, v16, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v2, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v3, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v4, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v4, v16, v4, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v10, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v2, v10, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v11, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v3, v3, v11, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v12, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v4, v4, v12, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX11-NEXT:    v_cndmask_b32_e32 v3, v9, v3, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v16
; GFX11-NEXT:    v_cndmask_b32_e32 v4, v16, v4, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v5, v13
; GFX11-NEXT:    v_cndmask_b32_e32 v8, v13, v5, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v6, v14
; GFX11-NEXT:    v_cndmask_b32_e32 v9, v14, v6, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v7, v15
; GFX11-NEXT:    v_cndmask_b32_e32 v10, v15, v7, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v5, v13
; GFX11-NEXT:    v_cndmask_b32_e32 v8, 0x7fc00000, v8, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v6, v14
; GFX11-NEXT:    v_cndmask_b32_e32 v9, 0x7fc00000, v9, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v7, v15
; GFX11-NEXT:    v_cndmask_b32_e32 v10, 0x7fc00000, v10, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v5, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v6, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v6, v9, v6, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v7, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v7, v10, v7, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v13, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v5, v5, v13, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v14, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v6, v6, v14, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v15, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v7, v7, v15, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v8
; GFX11-NEXT:    v_cndmask_b32_e32 v5, v8, v5, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v9
; GFX11-NEXT:    v_cndmask_b32_e32 v6, v9, v6, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v10
; GFX11-NEXT:    v_cndmask_b32_e32 v7, v10, v7, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v8f32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v0, v0, v8
; GFX12-NEXT:    v_maximum_f32 v1, v1, v9
; GFX12-NEXT:    v_maximum_f32 v2, v2, v10
; GFX12-NEXT:    v_maximum_f32 v3, v3, v11
; GFX12-NEXT:    v_maximum_f32 v4, v4, v12
; GFX12-NEXT:    v_maximum_f32 v5, v5, v13
; GFX12-NEXT:    v_maximum_f32 v6, v6, v14
; GFX12-NEXT:    v_maximum_f32 v7, v7, v15
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call <8 x float> @llvm.maximum.v8f32(<8 x float> %src0, <8 x float> %src1)
  ret <8 x float> %op
}

define <16 x float> @v_maximum_v16f32(<16 x float> %src0, <16 x float> %src1) {
; GFX7-LABEL: v_maximum_v16f32:
; GFX7:       ; %bb.0:
; GFX7-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX7-NEXT:    v_max_legacy_f32_e32 v32, v0, v16
; GFX7-NEXT:    v_mov_b32_e32 v31, 0x7fc00000
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v0, v16
; GFX7-NEXT:    v_cndmask_b32_e32 v32, v31, v32, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v32, v0, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v16, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v32
; GFX7-NEXT:    v_cndmask_b32_e32 v0, v32, v0, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v16, v1, v17
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v1, v17
; GFX7-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v16, v1, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v17, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc
; GFX7-NEXT:    buffer_load_dword v17, off, s[0:3], s32
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX7-NEXT:    v_cndmask_b32_e32 v1, v16, v1, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v16, v2, v18
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v2, v18
; GFX7-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v16, v2, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v18, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v2, v18, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX7-NEXT:    v_cndmask_b32_e32 v2, v16, v2, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v16, v3, v19
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v3, v19
; GFX7-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v3, v16, v3, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v19, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v3, v3, v19, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX7-NEXT:    v_cndmask_b32_e32 v3, v16, v3, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v16, v4, v20
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v4, v20
; GFX7-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v4, v16, v4, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v20, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX7-NEXT:    v_cndmask_b32_e32 v4, v16, v4, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v16, v5, v21
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v5, v21
; GFX7-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v5, v16, v5, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v21, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v5, v5, v21, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX7-NEXT:    v_cndmask_b32_e32 v5, v16, v5, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v16, v6, v22
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v6, v22
; GFX7-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v6, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v6, v16, v6, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v22, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX7-NEXT:    v_cndmask_b32_e32 v6, v16, v6, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v16, v7, v23
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v7, v23
; GFX7-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v7, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v7, v16, v7, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v23, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v7, v7, v23, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX7-NEXT:    v_cndmask_b32_e32 v7, v16, v7, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v16, v8, v24
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v8, v24
; GFX7-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v8, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v8, v16, v8, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v24, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX7-NEXT:    v_cndmask_b32_e32 v8, v16, v8, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v16, v9, v25
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v9, v25
; GFX7-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v9, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v9, v16, v9, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v25, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v9, v9, v25, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX7-NEXT:    v_cndmask_b32_e32 v9, v16, v9, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v16, v10, v26
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v10, v26
; GFX7-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v10, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v10, v16, v10, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v26, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v10, v10, v26, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX7-NEXT:    v_cndmask_b32_e32 v10, v16, v10, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v16, v11, v27
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v11, v27
; GFX7-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v11, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v11, v16, v11, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v27, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX7-NEXT:    v_cndmask_b32_e32 v11, v16, v11, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v16, v12, v28
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v12, v28
; GFX7-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v12, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v12, v16, v12, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v28, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v12, v12, v28, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX7-NEXT:    v_cndmask_b32_e32 v12, v16, v12, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v16, v13, v29
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v13, v29
; GFX7-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v13, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v13, v16, v13, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v29, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v13, v13, v29, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX7-NEXT:    v_cndmask_b32_e32 v13, v16, v13, vcc
; GFX7-NEXT:    v_max_legacy_f32_e32 v16, v14, v30
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v14, v30
; GFX7-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v14, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v14, v16, v14, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v30, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v14, v14, v30, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX7-NEXT:    v_cndmask_b32_e32 v14, v16, v14, vcc
; GFX7-NEXT:    s_waitcnt vmcnt(0)
; GFX7-NEXT:    v_max_legacy_f32_e32 v16, v15, v17
; GFX7-NEXT:    v_cmp_o_f32_e32 vcc, v15, v17
; GFX7-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v15, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v15, v16, v15, vcc
; GFX7-NEXT:    v_cmp_class_f32_e64 vcc, v17, 64
; GFX7-NEXT:    v_cndmask_b32_e32 v15, v15, v17, vcc
; GFX7-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX7-NEXT:    v_cndmask_b32_e32 v15, v16, v15, vcc
; GFX7-NEXT:    s_setpc_b64 s[30:31]
;
; GFX8-LABEL: v_maximum_v16f32:
; GFX8:       ; %bb.0:
; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v32, v16, v0, vcc
; GFX8-NEXT:    v_mov_b32_e32 v31, 0x7fc00000
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v32, v31, v32, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v32, v0, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v16, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v32
; GFX8-NEXT:    v_cndmask_b32_e32 v0, v32, v0, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v17
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v17, v1, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v1, v17
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v16, v1, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v17, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc
; GFX8-NEXT:    buffer_load_dword v17, off, s[0:3], s32
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v1, v16, v1, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v18
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v18, v2, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v2, v18
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v16, v2, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v18, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v2, v18, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v2, v16, v2, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v19
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v19, v3, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v3, v19
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v16, v3, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v19, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v3, v19, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v3, v16, v3, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v4, v20
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v20, v4, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v4, v20
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v16, v4, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v20, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v4, v16, v4, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v5, v21
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v21, v5, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v5, v21
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v5, v16, v5, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v21, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v5, v5, v21, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v5, v16, v5, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v6, v22
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v22, v6, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v6, v22
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v6, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v6, v16, v6, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v22, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v6, v16, v6, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v7, v23
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v23, v7, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v7, v23
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v7, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v7, v16, v7, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v23, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v7, v7, v23, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v7, v16, v7, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v8, v24
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v24, v8, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v8, v24
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v8, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v16, v8, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v24, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v8, v16, v8, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v9, v25
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v25, v9, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v9, v25
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v9, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v9, v16, v9, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v25, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v9, v9, v25, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v9, v16, v9, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v10, v26
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v26, v10, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v10, v26
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v10, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v10, v16, v10, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v26, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v10, v10, v26, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v10, v16, v10, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v11, v27
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v27, v11, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v11, v27
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v11, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v11, v16, v11, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v27, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v11, v16, v11, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v12, v28
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v28, v12, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v12, v28
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v12, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v12, v16, v12, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v28, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v12, v12, v28, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v12, v16, v12, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v13, v29
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v29, v13, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v13, v29
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v13, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v13, v16, v13, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v29, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v13, v13, v29, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v13, v16, v13, vcc
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v14, v30
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v30, v14, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v14, v30
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v14, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v14, v16, v14, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v30, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v14, v14, v30, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v14, v16, v14, vcc
; GFX8-NEXT:    s_waitcnt vmcnt(0)
; GFX8-NEXT:    v_cmp_gt_f32_e32 vcc, v15, v17
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v17, v15, vcc
; GFX8-NEXT:    v_cmp_o_f32_e32 vcc, v15, v17
; GFX8-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v15, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v15, v16, v15, vcc
; GFX8-NEXT:    v_cmp_class_f32_e64 vcc, v17, 64
; GFX8-NEXT:    v_cndmask_b32_e32 v15, v15, v17, vcc
; GFX8-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX8-NEXT:    v_cndmask_b32_e32 v15, v16, v15, vcc
; GFX8-NEXT:    s_setpc_b64 s[30:31]
;
; GFX9-LABEL: v_maximum_v16f32:
; GFX9:       ; %bb.0:
; GFX9-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v32, v16, v0, vcc
; GFX9-NEXT:    v_mov_b32_e32 v31, 0x7fc00000
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v32, v31, v32, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v32, v0, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v16, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v32
; GFX9-NEXT:    v_cndmask_b32_e32 v0, v32, v0, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v17
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v17, v1, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v1, v17
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v16, v1, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v17, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc
; GFX9-NEXT:    buffer_load_dword v17, off, s[0:3], s32
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v1, v16, v1, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v18
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v18, v2, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v2, v18
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v16, v2, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v18, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v2, v18, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v2, v16, v2, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v19
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v19, v3, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v3, v19
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v16, v3, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v19, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v3, v19, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v3, v16, v3, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v4, v20
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v20, v4, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v4, v20
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v16, v4, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v20, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v4, v16, v4, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v5, v21
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v21, v5, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v5, v21
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v16, v5, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v21, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v5, v21, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v5, v16, v5, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v6, v22
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v22, v6, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v6, v22
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v6, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v16, v6, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v22, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v6, v16, v6, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v7, v23
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v23, v7, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v7, v23
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v7, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v16, v7, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v23, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v7, v23, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v7, v16, v7, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v8, v24
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v24, v8, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v8, v24
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v8, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v16, v8, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v24, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v8, v16, v8, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v9, v25
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v25, v9, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v9, v25
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v9, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v9, v16, v9, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v25, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v9, v9, v25, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v9, v16, v9, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v10, v26
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v26, v10, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v10, v26
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v10, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v10, v16, v10, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v26, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v10, v10, v26, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v10, v16, v10, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v11, v27
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v27, v11, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v11, v27
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v11, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v11, v16, v11, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v27, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v11, v16, v11, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v12, v28
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v28, v12, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v12, v28
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v12, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v12, v16, v12, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v28, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v12, v12, v28, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v12, v16, v12, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v13, v29
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v29, v13, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v13, v29
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v13, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v13, v16, v13, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v29, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v13, v13, v29, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v13, v16, v13, vcc
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v14, v30
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v30, v14, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v14, v30
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v14, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v14, v16, v14, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v30, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v14, v14, v30, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v14, v16, v14, vcc
; GFX9-NEXT:    s_waitcnt vmcnt(0)
; GFX9-NEXT:    v_cmp_gt_f32_e32 vcc, v15, v17
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v17, v15, vcc
; GFX9-NEXT:    v_cmp_o_f32_e32 vcc, v15, v17
; GFX9-NEXT:    v_cndmask_b32_e32 v16, v31, v16, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v15, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v15, v16, v15, vcc
; GFX9-NEXT:    v_cmp_class_f32_e64 vcc, v17, 64
; GFX9-NEXT:    v_cndmask_b32_e32 v15, v15, v17, vcc
; GFX9-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX9-NEXT:    v_cndmask_b32_e32 v15, v16, v15, vcc
; GFX9-NEXT:    s_setpc_b64 s[30:31]
;
; GFX940-LABEL: v_maximum_v16f32:
; GFX940:       ; %bb.0:
; GFX940-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX940-NEXT:    scratch_load_dword v31, off, s32
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v0, v16
; GFX940-NEXT:    v_mov_b32_e32 v32, 0x7fc00000
; GFX940-NEXT:    s_nop 0
; GFX940-NEXT:    v_cndmask_b32_e32 v33, v16, v0, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v0, v16
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v33, v32, v33, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v0, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v33, v0, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v16, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v33
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v0, v33, v0, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v1, v17
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v17, v1, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v1, v17
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v32, v16, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v1, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v16, v1, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v17, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v1, v16, v1, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v2, v18
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v18, v2, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v2, v18
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v32, v16, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v2, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v16, v2, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v18, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v2, v18, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v2, v16, v2, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v3, v19
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v19, v3, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v3, v19
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v32, v16, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v3, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v16, v3, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v19, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v3, v19, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v3, v16, v3, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v4, v20
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v20, v4, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v4, v20
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v32, v16, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v4, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v16, v4, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v20, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v4, v16, v4, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v5, v21
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v21, v5, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v5, v21
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v32, v16, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v5, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v5, v16, v5, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v21, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v5, v5, v21, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v5, v16, v5, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v6, v22
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v22, v6, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v6, v22
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v32, v16, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v6, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v6, v16, v6, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v22, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v6, v16, v6, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v7, v23
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v23, v7, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v7, v23
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v32, v16, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v7, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v7, v16, v7, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v23, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v7, v7, v23, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v7, v16, v7, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v8, v24
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v24, v8, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v8, v24
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v32, v16, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v8, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v16, v8, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v24, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v8, v16, v8, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v9, v25
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v25, v9, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v9, v25
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v32, v16, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v9, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v9, v16, v9, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v25, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v9, v9, v25, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v9, v16, v9, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v10, v26
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v26, v10, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v10, v26
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v32, v16, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v10, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v10, v16, v10, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v26, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v10, v10, v26, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v10, v16, v10, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v11, v27
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v27, v11, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v11, v27
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v32, v16, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v11, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v11, v16, v11, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v27, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v11, v16, v11, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v12, v28
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v28, v12, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v12, v28
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v32, v16, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v12, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v12, v16, v12, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v28, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v12, v12, v28, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v12, v16, v12, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v13, v29
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v29, v13, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v13, v29
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v32, v16, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v13, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v13, v16, v13, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v29, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v13, v13, v29, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v13, v16, v13, vcc
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v14, v30
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v30, v14, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v14, v30
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v32, v16, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v14, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v14, v16, v14, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v30, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v14, v14, v30, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v14, v16, v14, vcc
; GFX940-NEXT:    s_waitcnt vmcnt(0)
; GFX940-NEXT:    v_cmp_gt_f32_e32 vcc, v15, v31
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v31, v15, vcc
; GFX940-NEXT:    v_cmp_o_f32_e32 vcc, v15, v31
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v16, v32, v16, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v15, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v15, v16, v15, vcc
; GFX940-NEXT:    v_cmp_class_f32_e64 vcc, v31, 64
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v15, v15, v31, vcc
; GFX940-NEXT:    v_cmp_eq_f32_e32 vcc, 0, v16
; GFX940-NEXT:    s_nop 1
; GFX940-NEXT:    v_cndmask_b32_e32 v15, v16, v15, vcc
; GFX940-NEXT:    s_setpc_b64 s[30:31]
;
; GFX10-LABEL: v_maximum_v16f32:
; GFX10:       ; %bb.0:
; GFX10-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v16
; GFX10-NEXT:    buffer_load_dword v31, off, s[0:3], s32
; GFX10-NEXT:    v_cndmask_b32_e32 v32, v16, v0, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v17
; GFX10-NEXT:    v_cndmask_b32_e32 v33, v17, v1, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v18
; GFX10-NEXT:    v_cndmask_b32_e32 v34, v18, v2, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v19
; GFX10-NEXT:    v_cndmask_b32_e32 v35, v19, v3, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v4, v20
; GFX10-NEXT:    v_cndmask_b32_e32 v36, v20, v4, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v5, v21
; GFX10-NEXT:    v_cndmask_b32_e32 v37, v21, v5, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v6, v22
; GFX10-NEXT:    v_cndmask_b32_e32 v38, v22, v6, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v7, v23
; GFX10-NEXT:    v_cndmask_b32_e32 v39, v23, v7, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v8, v24
; GFX10-NEXT:    v_cndmask_b32_e32 v48, v24, v8, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v9, v25
; GFX10-NEXT:    v_cndmask_b32_e32 v49, v25, v9, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v10, v26
; GFX10-NEXT:    v_cndmask_b32_e32 v50, v26, v10, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v11, v27
; GFX10-NEXT:    v_cndmask_b32_e32 v51, v27, v11, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v12, v28
; GFX10-NEXT:    v_cndmask_b32_e32 v52, v28, v12, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v13, v29
; GFX10-NEXT:    v_cndmask_b32_e32 v53, v29, v13, vcc_lo
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v14, v30
; GFX10-NEXT:    v_cndmask_b32_e32 v54, v30, v14, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v16
; GFX10-NEXT:    v_cndmask_b32_e32 v32, 0x7fc00000, v32, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v17
; GFX10-NEXT:    v_cndmask_b32_e32 v33, 0x7fc00000, v33, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v18
; GFX10-NEXT:    v_cndmask_b32_e32 v34, 0x7fc00000, v34, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v3, v19
; GFX10-NEXT:    v_cndmask_b32_e32 v35, 0x7fc00000, v35, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v4, v20
; GFX10-NEXT:    v_cndmask_b32_e32 v36, 0x7fc00000, v36, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v5, v21
; GFX10-NEXT:    v_cndmask_b32_e32 v37, 0x7fc00000, v37, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v6, v22
; GFX10-NEXT:    v_cndmask_b32_e32 v38, 0x7fc00000, v38, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v7, v23
; GFX10-NEXT:    v_cndmask_b32_e32 v39, 0x7fc00000, v39, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v8, v24
; GFX10-NEXT:    v_cndmask_b32_e32 v48, 0x7fc00000, v48, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v9, v25
; GFX10-NEXT:    v_cndmask_b32_e32 v49, 0x7fc00000, v49, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v10, v26
; GFX10-NEXT:    v_cndmask_b32_e32 v50, 0x7fc00000, v50, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v11, v27
; GFX10-NEXT:    v_cndmask_b32_e32 v51, 0x7fc00000, v51, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v12, v28
; GFX10-NEXT:    v_cndmask_b32_e32 v52, 0x7fc00000, v52, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v13, v29
; GFX10-NEXT:    v_cndmask_b32_e32 v53, 0x7fc00000, v53, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v14, v30
; GFX10-NEXT:    v_cndmask_b32_e32 v54, 0x7fc00000, v54, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v0, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v32, v0, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v1, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v33, v1, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v2, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v34, v2, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v3, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v35, v3, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v4, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v36, v4, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v5, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v37, v5, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v6, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v6, v38, v6, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v7, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v39, v7, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v8, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v48, v8, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v9, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v9, v49, v9, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v10, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v10, v50, v10, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v11, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v11, v51, v11, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v12, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v12, v52, v12, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v13, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v13, v53, v13, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v14, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v14, v54, v14, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v16, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v17, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v18, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v2, v18, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v19, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v3, v19, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v20, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v21, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v5, v21, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v22, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v23, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v7, v23, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v24, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v25, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v9, v9, v25, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v26, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v10, v10, v26, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v27, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v28, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v12, v12, v28, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v29, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v13, v13, v29, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v30, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v14, v14, v30, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v32
; GFX10-NEXT:    v_cndmask_b32_e32 v0, v32, v0, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v33
; GFX10-NEXT:    v_cndmask_b32_e32 v1, v33, v1, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v34
; GFX10-NEXT:    v_cndmask_b32_e32 v2, v34, v2, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v35
; GFX10-NEXT:    v_cndmask_b32_e32 v3, v35, v3, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v36
; GFX10-NEXT:    v_cndmask_b32_e32 v4, v36, v4, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v37
; GFX10-NEXT:    v_cndmask_b32_e32 v5, v37, v5, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v38
; GFX10-NEXT:    v_cndmask_b32_e32 v6, v38, v6, vcc_lo
; GFX10-NEXT:    s_waitcnt vmcnt(0)
; GFX10-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v15, v31
; GFX10-NEXT:    v_cndmask_b32_e32 v16, v31, v15, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v39
; GFX10-NEXT:    v_cndmask_b32_e32 v7, v39, v7, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v48
; GFX10-NEXT:    v_cndmask_b32_e32 v8, v48, v8, vcc_lo
; GFX10-NEXT:    v_cmp_o_f32_e32 vcc_lo, v15, v31
; GFX10-NEXT:    v_cndmask_b32_e32 v16, 0x7fc00000, v16, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v49
; GFX10-NEXT:    v_cndmask_b32_e32 v9, v49, v9, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v50
; GFX10-NEXT:    v_cndmask_b32_e32 v10, v50, v10, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v15, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v15, v16, v15, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v51
; GFX10-NEXT:    v_cndmask_b32_e32 v11, v51, v11, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v52
; GFX10-NEXT:    v_cndmask_b32_e32 v12, v52, v12, vcc_lo
; GFX10-NEXT:    v_cmp_class_f32_e64 vcc_lo, v31, 64
; GFX10-NEXT:    v_cndmask_b32_e32 v15, v15, v31, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v53
; GFX10-NEXT:    v_cndmask_b32_e32 v13, v53, v13, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v54
; GFX10-NEXT:    v_cndmask_b32_e32 v14, v54, v14, vcc_lo
; GFX10-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v16
; GFX10-NEXT:    v_cndmask_b32_e32 v15, v16, v15, vcc_lo
; GFX10-NEXT:    s_setpc_b64 s[30:31]
;
; GFX11-LABEL: v_maximum_v16f32:
; GFX11:       ; %bb.0:
; GFX11-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v0, v16
; GFX11-NEXT:    scratch_load_b32 v31, off, s32
; GFX11-NEXT:    v_cndmask_b32_e32 v32, v16, v0, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v1, v17
; GFX11-NEXT:    v_cndmask_b32_e32 v33, v17, v1, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v2, v18
; GFX11-NEXT:    v_cndmask_b32_e32 v34, v18, v2, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v3, v19
; GFX11-NEXT:    v_cndmask_b32_e32 v35, v19, v3, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v4, v20
; GFX11-NEXT:    v_cndmask_b32_e32 v36, v20, v4, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v5, v21
; GFX11-NEXT:    v_cndmask_b32_e32 v37, v21, v5, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v6, v22
; GFX11-NEXT:    v_cndmask_b32_e32 v38, v22, v6, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v7, v23
; GFX11-NEXT:    v_cndmask_b32_e32 v39, v23, v7, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v8, v24
; GFX11-NEXT:    v_cndmask_b32_e32 v48, v24, v8, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v9, v25
; GFX11-NEXT:    v_cndmask_b32_e32 v49, v25, v9, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v10, v26
; GFX11-NEXT:    v_cndmask_b32_e32 v50, v26, v10, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v11, v27
; GFX11-NEXT:    v_cndmask_b32_e32 v51, v27, v11, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v12, v28
; GFX11-NEXT:    v_cndmask_b32_e32 v52, v28, v12, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v13, v29
; GFX11-NEXT:    v_cndmask_b32_e32 v53, v29, v13, vcc_lo
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v14, v30
; GFX11-NEXT:    v_cndmask_b32_e32 v54, v30, v14, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v0, v16
; GFX11-NEXT:    v_cndmask_b32_e32 v32, 0x7fc00000, v32, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v1, v17
; GFX11-NEXT:    v_cndmask_b32_e32 v33, 0x7fc00000, v33, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v2, v18
; GFX11-NEXT:    v_cndmask_b32_e32 v34, 0x7fc00000, v34, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v3, v19
; GFX11-NEXT:    v_cndmask_b32_e32 v35, 0x7fc00000, v35, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v4, v20
; GFX11-NEXT:    v_cndmask_b32_e32 v36, 0x7fc00000, v36, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v5, v21
; GFX11-NEXT:    v_cndmask_b32_e32 v37, 0x7fc00000, v37, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v6, v22
; GFX11-NEXT:    v_cndmask_b32_e32 v38, 0x7fc00000, v38, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v7, v23
; GFX11-NEXT:    v_cndmask_b32_e32 v39, 0x7fc00000, v39, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v8, v24
; GFX11-NEXT:    v_cndmask_b32_e32 v48, 0x7fc00000, v48, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v9, v25
; GFX11-NEXT:    v_cndmask_b32_e32 v49, 0x7fc00000, v49, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v10, v26
; GFX11-NEXT:    v_cndmask_b32_e32 v50, 0x7fc00000, v50, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v11, v27
; GFX11-NEXT:    v_cndmask_b32_e32 v51, 0x7fc00000, v51, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v12, v28
; GFX11-NEXT:    v_cndmask_b32_e32 v52, 0x7fc00000, v52, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v13, v29
; GFX11-NEXT:    v_cndmask_b32_e32 v53, 0x7fc00000, v53, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v14, v30
; GFX11-NEXT:    v_cndmask_b32_e32 v54, 0x7fc00000, v54, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v0, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v32, v0, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v1, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v33, v1, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v2, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v34, v2, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v3, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v3, v35, v3, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v4, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v4, v36, v4, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v5, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v5, v37, v5, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v6, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v6, v38, v6, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v7, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v7, v39, v7, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v8, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v8, v48, v8, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v9, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v9, v49, v9, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v10, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v10, v50, v10, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v11, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v11, v51, v11, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v12, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v12, v52, v12, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v13, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v13, v53, v13, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v14, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v14, v54, v14, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v16, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v0, v16, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v17, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v1, v17, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v18, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v2, v18, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v19, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v3, v3, v19, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v20, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v4, v4, v20, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v21, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v5, v5, v21, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v22, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v6, v6, v22, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v23, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v7, v7, v23, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v24, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v8, v8, v24, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v25, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v9, v9, v25, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v26, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v10, v10, v26, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v27, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v11, v11, v27, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v28, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v12, v12, v28, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v29, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v13, v13, v29, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v30, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v14, v14, v30, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v32
; GFX11-NEXT:    v_cndmask_b32_e32 v0, v32, v0, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v33
; GFX11-NEXT:    v_cndmask_b32_e32 v1, v33, v1, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v34
; GFX11-NEXT:    v_cndmask_b32_e32 v2, v34, v2, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v35
; GFX11-NEXT:    v_cndmask_b32_e32 v3, v35, v3, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v36
; GFX11-NEXT:    v_cndmask_b32_e32 v4, v36, v4, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v37
; GFX11-NEXT:    v_cndmask_b32_e32 v5, v37, v5, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v38
; GFX11-NEXT:    v_cndmask_b32_e32 v6, v38, v6, vcc_lo
; GFX11-NEXT:    s_waitcnt vmcnt(0)
; GFX11-NEXT:    v_cmp_gt_f32_e32 vcc_lo, v15, v31
; GFX11-NEXT:    v_cndmask_b32_e32 v16, v31, v15, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v39
; GFX11-NEXT:    v_cndmask_b32_e32 v7, v39, v7, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v48
; GFX11-NEXT:    v_cndmask_b32_e32 v8, v48, v8, vcc_lo
; GFX11-NEXT:    v_cmp_o_f32_e32 vcc_lo, v15, v31
; GFX11-NEXT:    v_cndmask_b32_e32 v16, 0x7fc00000, v16, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v49
; GFX11-NEXT:    v_cndmask_b32_e32 v9, v49, v9, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v50
; GFX11-NEXT:    v_cndmask_b32_e32 v10, v50, v10, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v15, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v15, v16, v15, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v51
; GFX11-NEXT:    v_cndmask_b32_e32 v11, v51, v11, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v52
; GFX11-NEXT:    v_cndmask_b32_e32 v12, v52, v12, vcc_lo
; GFX11-NEXT:    v_cmp_class_f32_e64 vcc_lo, v31, 64
; GFX11-NEXT:    v_cndmask_b32_e32 v15, v15, v31, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v53
; GFX11-NEXT:    v_cndmask_b32_e32 v13, v53, v13, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v54
; GFX11-NEXT:    v_cndmask_b32_e32 v14, v54, v14, vcc_lo
; GFX11-NEXT:    v_cmp_eq_f32_e32 vcc_lo, 0, v16
; GFX11-NEXT:    v_cndmask_b32_e32 v15, v16, v15, vcc_lo
; GFX11-NEXT:    s_setpc_b64 s[30:31]
;
; GFX12-LABEL: v_maximum_v16f32:
; GFX12:       ; %bb.0:
; GFX12-NEXT:    s_wait_loadcnt_dscnt 0x0
; GFX12-NEXT:    s_wait_expcnt 0x0
; GFX12-NEXT:    s_wait_samplecnt 0x0
; GFX12-NEXT:    s_wait_bvhcnt 0x0
; GFX12-NEXT:    s_wait_kmcnt 0x0
; GFX12-NEXT:    scratch_load_b32 v31, off, s32
; GFX12-NEXT:    v_maximum_f32 v0, v0, v16
; GFX12-NEXT:    v_maximum_f32 v1, v1, v17
; GFX12-NEXT:    v_maximum_f32 v2, v2, v18
; GFX12-NEXT:    v_maximum_f32 v3, v3, v19
; GFX12-NEXT:    v_maximum_f32 v4, v4, v20
; GFX12-NEXT:    v_maximum_f32 v5, v5, v21
; GFX12-NEXT:    v_maximum_f32 v6, v6, v22
; GFX12-NEXT:    v_maximum_f32 v7, v7, v23
; GFX12-NEXT:    v_maximum_f32 v8, v8, v24
; GFX12-NEXT:    v_maximum_f32 v9, v9, v25
; GFX12-NEXT:    v_maximum_f32 v10, v10, v26
; GFX12-NEXT:    v_maximum_f32 v11, v11, v27
; GFX12-NEXT:    v_maximum_f32 v12, v12, v28
; GFX12-NEXT:    v_maximum_f32 v13, v13, v29
; GFX12-NEXT:    v_maximum_f32 v14, v14, v30
; GFX12-NEXT:    s_wait_loadcnt 0x0
; GFX12-NEXT:    v_maximum_f32 v15, v15, v31
; GFX12-NEXT:    s_setpc_b64 s[30:31]
  %op = call <16 x float> @llvm.maximum.v16f32(<16 x float> %src0, <16 x float> %src1)
  ret <16 x float> %op
}
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
; GCN: {{.*}}