)]}'
{
  "commit": "41f1b467a29d2ca4e35df37c3aa79a0a8c04bc4f",
  "tree": "52fc648196f33adb03defeed5dd97ca0d8a5de9b",
  "parents": [
    "6af2f225a0f820d331f251af69c2dad0c845964e"
  ],
  "author": {
    "name": "Luke Lau",
    "email": "luke@igalia.com",
    "time": "Tue Sep 17 13:50:19 2024 +0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Sep 17 13:50:19 2024 +0800"
  },
  "message": "[RISCV] Account for zvfhmin and zvfbfmin promotion in register usage (#108370)\n\nA half with only zvfhmin or bfloat will end up getting promoted to a f32\r\nfor most instructions.\r\n\r\nUnless the loop consists only of memory ops and permutation instructions\r\nwhich don\u0027t need promoted (is this common?), we\u0027ll end up using double\r\nthe LMUL than what\u0027s currently being returned by getRegUsageForType.\r\n\r\nSince this is used by the loop vectorizer, it seems better to be\r\nconservative and assume that any usage of a zvfhmin half/bfloat will end\r\nup being widened to a f32",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2b5e7c4727928479983d81457fb59799b97b8c82",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp",
      "new_id": "0e06511138529922e55948dc35761a2861c18cb1",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "89514431278a747e3b621f31c19c2eeb23f539a6",
      "new_mode": 33188,
      "new_path": "llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-bf16.ll"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "ceedcfba4691e1fe8dea9ae2730110efb142e34e",
      "new_mode": 33188,
      "new_path": "llvm/test/Transforms/LoopVectorize/RISCV/reg-usage-f16.ll"
    }
  ]
}