| //===---- TargetInfo.cpp - Encapsulate target details -----------*- C++ -*-===// |
| // |
| // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| // See https://llvm.org/LICENSE.txt for license information. |
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // These classes wrap the information about a call or function |
| // definition used to handle ABI compliancy. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| #include "TargetInfo.h" |
| #include "ABIInfo.h" |
| #include "CGBlocks.h" |
| #include "CGCXXABI.h" |
| #include "CGValue.h" |
| #include "CodeGenFunction.h" |
| #include "clang/AST/Attr.h" |
| #include "clang/AST/RecordLayout.h" |
| #include "clang/Basic/CodeGenOptions.h" |
| #include "clang/Basic/DiagnosticFrontend.h" |
| #include "clang/Basic/Builtins.h" |
| #include "clang/CodeGen/CGFunctionInfo.h" |
| #include "clang/CodeGen/SwiftCallingConv.h" |
| #include "llvm/ADT/SmallBitVector.h" |
| #include "llvm/ADT/StringExtras.h" |
| #include "llvm/ADT/StringSwitch.h" |
| #include "llvm/ADT/Triple.h" |
| #include "llvm/ADT/Twine.h" |
| #include "llvm/IR/DataLayout.h" |
| #include "llvm/IR/IntrinsicsNVPTX.h" |
| #include "llvm/IR/IntrinsicsS390.h" |
| #include "llvm/IR/Type.h" |
| #include "llvm/Support/raw_ostream.h" |
| #include <algorithm> // std::sort |
| |
| using namespace clang; |
| using namespace CodeGen; |
| |
| // Helper for coercing an aggregate argument or return value into an integer |
| // array of the same size (including padding) and alignment. This alternate |
| // coercion happens only for the RenderScript ABI and can be removed after |
| // runtimes that rely on it are no longer supported. |
| // |
| // RenderScript assumes that the size of the argument / return value in the IR |
| // is the same as the size of the corresponding qualified type. This helper |
| // coerces the aggregate type into an array of the same size (including |
| // padding). This coercion is used in lieu of expansion of struct members or |
| // other canonical coercions that return a coerced-type of larger size. |
| // |
| // Ty - The argument / return value type |
| // Context - The associated ASTContext |
| // LLVMContext - The associated LLVMContext |
| static ABIArgInfo coerceToIntArray(QualType Ty, |
| ASTContext &Context, |
| llvm::LLVMContext &LLVMContext) { |
| // Alignment and Size are measured in bits. |
| const uint64_t Size = Context.getTypeSize(Ty); |
| const uint64_t Alignment = Context.getTypeAlign(Ty); |
| llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Alignment); |
| const uint64_t NumElements = (Size + Alignment - 1) / Alignment; |
| return ABIArgInfo::getDirect(llvm::ArrayType::get(IntType, NumElements)); |
| } |
| |
| static void AssignToArrayRange(CodeGen::CGBuilderTy &Builder, |
| llvm::Value *Array, |
| llvm::Value *Value, |
| unsigned FirstIndex, |
| unsigned LastIndex) { |
| // Alternatively, we could emit this as a loop in the source. |
| for (unsigned I = FirstIndex; I <= LastIndex; ++I) { |
| llvm::Value *Cell = |
| Builder.CreateConstInBoundsGEP1_32(Builder.getInt8Ty(), Array, I); |
| Builder.CreateAlignedStore(Value, Cell, CharUnits::One()); |
| } |
| } |
| |
| static bool isAggregateTypeForABI(QualType T) { |
| return !CodeGenFunction::hasScalarEvaluationKind(T) || |
| T->isMemberFunctionPointerType(); |
| } |
| |
| ABIArgInfo ABIInfo::getNaturalAlignIndirect(QualType Ty, bool ByVal, |
| bool Realign, |
| llvm::Type *Padding) const { |
| return ABIArgInfo::getIndirect(getContext().getTypeAlignInChars(Ty), ByVal, |
| Realign, Padding); |
| } |
| |
| ABIArgInfo |
| ABIInfo::getNaturalAlignIndirectInReg(QualType Ty, bool Realign) const { |
| return ABIArgInfo::getIndirectInReg(getContext().getTypeAlignInChars(Ty), |
| /*ByVal*/ false, Realign); |
| } |
| |
| Address ABIInfo::EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr, |
| QualType Ty) const { |
| return Address::invalid(); |
| } |
| |
| bool ABIInfo::isPromotableIntegerTypeForABI(QualType Ty) const { |
| if (Ty->isPromotableIntegerType()) |
| return true; |
| |
| if (const auto *EIT = Ty->getAs<ExtIntType>()) |
| if (EIT->getNumBits() < getContext().getTypeSize(getContext().IntTy)) |
| return true; |
| |
| return false; |
| } |
| |
| ABIInfo::~ABIInfo() {} |
| |
| /// Does the given lowering require more than the given number of |
| /// registers when expanded? |
| /// |
| /// This is intended to be the basis of a reasonable basic implementation |
| /// of should{Pass,Return}IndirectlyForSwift. |
| /// |
| /// For most targets, a limit of four total registers is reasonable; this |
| /// limits the amount of code required in order to move around the value |
| /// in case it wasn't produced immediately prior to the call by the caller |
| /// (or wasn't produced in exactly the right registers) or isn't used |
| /// immediately within the callee. But some targets may need to further |
| /// limit the register count due to an inability to support that many |
| /// return registers. |
| static bool occupiesMoreThan(CodeGenTypes &cgt, |
| ArrayRef<llvm::Type*> scalarTypes, |
| unsigned maxAllRegisters) { |
| unsigned intCount = 0, fpCount = 0; |
| for (llvm::Type *type : scalarTypes) { |
| if (type->isPointerTy()) { |
| intCount++; |
| } else if (auto intTy = dyn_cast<llvm::IntegerType>(type)) { |
| auto ptrWidth = cgt.getTarget().getPointerWidth(0); |
| intCount += (intTy->getBitWidth() + ptrWidth - 1) / ptrWidth; |
| } else { |
| assert(type->isVectorTy() || type->isFloatingPointTy()); |
| fpCount++; |
| } |
| } |
| |
| return (intCount + fpCount > maxAllRegisters); |
| } |
| |
| bool SwiftABIInfo::isLegalVectorTypeForSwift(CharUnits vectorSize, |
| llvm::Type *eltTy, |
| unsigned numElts) const { |
| // The default implementation of this assumes that the target guarantees |
| // 128-bit SIMD support but nothing more. |
| return (vectorSize.getQuantity() > 8 && vectorSize.getQuantity() <= 16); |
| } |
| |
| static CGCXXABI::RecordArgABI getRecordArgABI(const RecordType *RT, |
| CGCXXABI &CXXABI) { |
| const CXXRecordDecl *RD = dyn_cast<CXXRecordDecl>(RT->getDecl()); |
| if (!RD) { |
| if (!RT->getDecl()->canPassInRegisters()) |
| return CGCXXABI::RAA_Indirect; |
| return CGCXXABI::RAA_Default; |
| } |
| return CXXABI.getRecordArgABI(RD); |
| } |
| |
| static CGCXXABI::RecordArgABI getRecordArgABI(QualType T, |
| CGCXXABI &CXXABI) { |
| const RecordType *RT = T->getAs<RecordType>(); |
| if (!RT) |
| return CGCXXABI::RAA_Default; |
| return getRecordArgABI(RT, CXXABI); |
| } |
| |
| static bool classifyReturnType(const CGCXXABI &CXXABI, CGFunctionInfo &FI, |
| const ABIInfo &Info) { |
| QualType Ty = FI.getReturnType(); |
| |
| if (const auto *RT = Ty->getAs<RecordType>()) |
| if (!isa<CXXRecordDecl>(RT->getDecl()) && |
| !RT->getDecl()->canPassInRegisters()) { |
| FI.getReturnInfo() = Info.getNaturalAlignIndirect(Ty); |
| return true; |
| } |
| |
| return CXXABI.classifyReturnType(FI); |
| } |
| |
| /// Pass transparent unions as if they were the type of the first element. Sema |
| /// should ensure that all elements of the union have the same "machine type". |
| static QualType useFirstFieldIfTransparentUnion(QualType Ty) { |
| if (const RecordType *UT = Ty->getAsUnionType()) { |
| const RecordDecl *UD = UT->getDecl(); |
| if (UD->hasAttr<TransparentUnionAttr>()) { |
| assert(!UD->field_empty() && "sema created an empty transparent union"); |
| return UD->field_begin()->getType(); |
| } |
| } |
| return Ty; |
| } |
| |
| CGCXXABI &ABIInfo::getCXXABI() const { |
| return CGT.getCXXABI(); |
| } |
| |
| ASTContext &ABIInfo::getContext() const { |
| return CGT.getContext(); |
| } |
| |
| llvm::LLVMContext &ABIInfo::getVMContext() const { |
| return CGT.getLLVMContext(); |
| } |
| |
| const llvm::DataLayout &ABIInfo::getDataLayout() const { |
| return CGT.getDataLayout(); |
| } |
| |
| const TargetInfo &ABIInfo::getTarget() const { |
| return CGT.getTarget(); |
| } |
| |
| const CodeGenOptions &ABIInfo::getCodeGenOpts() const { |
| return CGT.getCodeGenOpts(); |
| } |
| |
| bool ABIInfo::isAndroid() const { return getTarget().getTriple().isAndroid(); } |
| |
| bool ABIInfo::isHomogeneousAggregateBaseType(QualType Ty) const { |
| return false; |
| } |
| |
| bool ABIInfo::isHomogeneousAggregateSmallEnough(const Type *Base, |
| uint64_t Members) const { |
| return false; |
| } |
| |
| LLVM_DUMP_METHOD void ABIArgInfo::dump() const { |
| raw_ostream &OS = llvm::errs(); |
| OS << "(ABIArgInfo Kind="; |
| switch (TheKind) { |
| case Direct: |
| OS << "Direct Type="; |
| if (llvm::Type *Ty = getCoerceToType()) |
| Ty->print(OS); |
| else |
| OS << "null"; |
| break; |
| case Extend: |
| OS << "Extend"; |
| break; |
| case Ignore: |
| OS << "Ignore"; |
| break; |
| case InAlloca: |
| OS << "InAlloca Offset=" << getInAllocaFieldIndex(); |
| break; |
| case Indirect: |
| OS << "Indirect Align=" << getIndirectAlign().getQuantity() |
| << " ByVal=" << getIndirectByVal() |
| << " Realign=" << getIndirectRealign(); |
| break; |
| case IndirectAliased: |
| OS << "Indirect Align=" << getIndirectAlign().getQuantity() |
| << " AadrSpace=" << getIndirectAddrSpace() |
| << " Realign=" << getIndirectRealign(); |
| break; |
| case Expand: |
| OS << "Expand"; |
| break; |
| case CoerceAndExpand: |
| OS << "CoerceAndExpand Type="; |
| getCoerceAndExpandType()->print(OS); |
| break; |
| } |
| OS << ")\n"; |
| } |
| |
| // Dynamically round a pointer up to a multiple of the given alignment. |
| static llvm::Value *emitRoundPointerUpToAlignment(CodeGenFunction &CGF, |
| llvm::Value *Ptr, |
| CharUnits Align) { |
| llvm::Value *PtrAsInt = Ptr; |
| // OverflowArgArea = (OverflowArgArea + Align - 1) & -Align; |
| PtrAsInt = CGF.Builder.CreatePtrToInt(PtrAsInt, CGF.IntPtrTy); |
| PtrAsInt = CGF.Builder.CreateAdd(PtrAsInt, |
| llvm::ConstantInt::get(CGF.IntPtrTy, Align.getQuantity() - 1)); |
| PtrAsInt = CGF.Builder.CreateAnd(PtrAsInt, |
| llvm::ConstantInt::get(CGF.IntPtrTy, -Align.getQuantity())); |
| PtrAsInt = CGF.Builder.CreateIntToPtr(PtrAsInt, |
| Ptr->getType(), |
| Ptr->getName() + ".aligned"); |
| return PtrAsInt; |
| } |
| |
| /// Emit va_arg for a platform using the common void* representation, |
| /// where arguments are simply emitted in an array of slots on the stack. |
| /// |
| /// This version implements the core direct-value passing rules. |
| /// |
| /// \param SlotSize - The size and alignment of a stack slot. |
| /// Each argument will be allocated to a multiple of this number of |
| /// slots, and all the slots will be aligned to this value. |
| /// \param AllowHigherAlign - The slot alignment is not a cap; |
| /// an argument type with an alignment greater than the slot size |
| /// will be emitted on a higher-alignment address, potentially |
| /// leaving one or more empty slots behind as padding. If this |
| /// is false, the returned address might be less-aligned than |
| /// DirectAlign. |
| static Address emitVoidPtrDirectVAArg(CodeGenFunction &CGF, |
| Address VAListAddr, |
| llvm::Type *DirectTy, |
| CharUnits DirectSize, |
| CharUnits DirectAlign, |
| CharUnits SlotSize, |
| bool AllowHigherAlign) { |
| // Cast the element type to i8* if necessary. Some platforms define |
| // va_list as a struct containing an i8* instead of just an i8*. |
| if (VAListAddr.getElementType() != CGF.Int8PtrTy) |
| VAListAddr = CGF.Builder.CreateElementBitCast(VAListAddr, CGF.Int8PtrTy); |
| |
| llvm::Value *Ptr = CGF.Builder.CreateLoad(VAListAddr, "argp.cur"); |
| |
| // If the CC aligns values higher than the slot size, do so if needed. |
| Address Addr = Address::invalid(); |
| if (AllowHigherAlign && DirectAlign > SlotSize) { |
| Addr = Address(emitRoundPointerUpToAlignment(CGF, Ptr, DirectAlign), |
| DirectAlign); |
| } else { |
| Addr = Address(Ptr, SlotSize); |
| } |
| |
| // Advance the pointer past the argument, then store that back. |
| CharUnits FullDirectSize = DirectSize.alignTo(SlotSize); |
| Address NextPtr = |
| CGF.Builder.CreateConstInBoundsByteGEP(Addr, FullDirectSize, "argp.next"); |
| CGF.Builder.CreateStore(NextPtr.getPointer(), VAListAddr); |
| |
| // If the argument is smaller than a slot, and this is a big-endian |
| // target, the argument will be right-adjusted in its slot. |
| if (DirectSize < SlotSize && CGF.CGM.getDataLayout().isBigEndian() && |
| !DirectTy->isStructTy()) { |
| Addr = CGF.Builder.CreateConstInBoundsByteGEP(Addr, SlotSize - DirectSize); |
| } |
| |
| Addr = CGF.Builder.CreateElementBitCast(Addr, DirectTy); |
| return Addr; |
| } |
| |
| /// Emit va_arg for a platform using the common void* representation, |
| /// where arguments are simply emitted in an array of slots on the stack. |
| /// |
| /// \param IsIndirect - Values of this type are passed indirectly. |
| /// \param ValueInfo - The size and alignment of this type, generally |
| /// computed with getContext().getTypeInfoInChars(ValueTy). |
| /// \param SlotSizeAndAlign - The size and alignment of a stack slot. |
| /// Each argument will be allocated to a multiple of this number of |
| /// slots, and all the slots will be aligned to this value. |
| /// \param AllowHigherAlign - The slot alignment is not a cap; |
| /// an argument type with an alignment greater than the slot size |
| /// will be emitted on a higher-alignment address, potentially |
| /// leaving one or more empty slots behind as padding. |
| static Address emitVoidPtrVAArg(CodeGenFunction &CGF, Address VAListAddr, |
| QualType ValueTy, bool IsIndirect, |
| TypeInfoChars ValueInfo, |
| CharUnits SlotSizeAndAlign, |
| bool AllowHigherAlign) { |
| // The size and alignment of the value that was passed directly. |
| CharUnits DirectSize, DirectAlign; |
| if (IsIndirect) { |
| DirectSize = CGF.getPointerSize(); |
| DirectAlign = CGF.getPointerAlign(); |
| } else { |
| DirectSize = ValueInfo.Width; |
| DirectAlign = ValueInfo.Align; |
| } |
| |
| // Cast the address we've calculated to the right type. |
| llvm::Type *DirectTy = CGF.ConvertTypeForMem(ValueTy); |
| if (IsIndirect) |
| DirectTy = DirectTy->getPointerTo(0); |
| |
| Address Addr = emitVoidPtrDirectVAArg(CGF, VAListAddr, DirectTy, |
| DirectSize, DirectAlign, |
| SlotSizeAndAlign, |
| AllowHigherAlign); |
| |
| if (IsIndirect) { |
| Addr = Address(CGF.Builder.CreateLoad(Addr), ValueInfo.Align); |
| } |
| |
| return Addr; |
| |
| } |
| |
| static Address complexTempStructure(CodeGenFunction &CGF, Address VAListAddr, |
| QualType Ty, CharUnits SlotSize, |
| CharUnits EltSize, const ComplexType *CTy) { |
| Address Addr = |
| emitVoidPtrDirectVAArg(CGF, VAListAddr, CGF.Int8Ty, SlotSize * 2, |
| SlotSize, SlotSize, /*AllowHigher*/ true); |
| |
| Address RealAddr = Addr; |
| Address ImagAddr = RealAddr; |
| if (CGF.CGM.getDataLayout().isBigEndian()) { |
| RealAddr = |
| CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize - EltSize); |
| ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(ImagAddr, |
| 2 * SlotSize - EltSize); |
| } else { |
| ImagAddr = CGF.Builder.CreateConstInBoundsByteGEP(RealAddr, SlotSize); |
| } |
| |
| llvm::Type *EltTy = CGF.ConvertTypeForMem(CTy->getElementType()); |
| RealAddr = CGF.Builder.CreateElementBitCast(RealAddr, EltTy); |
| ImagAddr = CGF.Builder.CreateElementBitCast(ImagAddr, EltTy); |
| llvm::Value *Real = CGF.Builder.CreateLoad(RealAddr, ".vareal"); |
| llvm::Value *Imag = CGF.Builder.CreateLoad(ImagAddr, ".vaimag"); |
| |
| Address Temp = CGF.CreateMemTemp(Ty, "vacplx"); |
| CGF.EmitStoreOfComplex({Real, Imag}, CGF.MakeAddrLValue(Temp, Ty), |
| /*init*/ true); |
| return Temp; |
| } |
| |
| static Address emitMergePHI(CodeGenFunction &CGF, |
| Address Addr1, llvm::BasicBlock *Block1, |
| Address Addr2, llvm::BasicBlock *Block2, |
| const llvm::Twine &Name = "") { |
| assert(Addr1.getType() == Addr2.getType()); |
| llvm::PHINode *PHI = CGF.Builder.CreatePHI(Addr1.getType(), 2, Name); |
| PHI->addIncoming(Addr1.getPointer(), Block1); |
| PHI->addIncoming(Addr2.getPointer(), Block2); |
| CharUnits Align = std::min(Addr1.getAlignment(), Addr2.getAlignment()); |
| return Address(PHI, Align); |
| } |
| |
| TargetCodeGenInfo::~TargetCodeGenInfo() = default; |
| |
| // If someone can figure out a general rule for this, that would be great. |
| // It's probably just doomed to be platform-dependent, though. |
| unsigned TargetCodeGenInfo::getSizeOfUnwindException() const { |
| // Verified for: |
| // x86-64 FreeBSD, Linux, Darwin |
| // x86-32 FreeBSD, Linux, Darwin |
| // PowerPC Linux, Darwin |
| // ARM Darwin (*not* EABI) |
| // AArch64 Linux |
| return 32; |
| } |
| |
| bool TargetCodeGenInfo::isNoProtoCallVariadic(const CallArgList &args, |
| const FunctionNoProtoType *fnType) const { |
| // The following conventions are known to require this to be false: |
| // x86_stdcall |
| // MIPS |
| // For everything else, we just prefer false unless we opt out. |
| return false; |
| } |
| |
| void |
| TargetCodeGenInfo::getDependentLibraryOption(llvm::StringRef Lib, |
| llvm::SmallString<24> &Opt) const { |
| // This assumes the user is passing a library name like "rt" instead of a |
| // filename like "librt.a/so", and that they don't care whether it's static or |
| // dynamic. |
| Opt = "-l"; |
| Opt += Lib; |
| } |
| |
| unsigned TargetCodeGenInfo::getOpenCLKernelCallingConv() const { |
| // OpenCL kernels are called via an explicit runtime API with arguments |
| // set with clSetKernelArg(), not as normal sub-functions. |
| // Return SPIR_KERNEL by default as the kernel calling convention to |
| // ensure the fingerprint is fixed such way that each OpenCL argument |
| // gets one matching argument in the produced kernel function argument |
| // list to enable feasible implementation of clSetKernelArg() with |
| // aggregates etc. In case we would use the default C calling conv here, |
| // clSetKernelArg() might break depending on the target-specific |
| // conventions; different targets might split structs passed as values |
| // to multiple function arguments etc. |
| return llvm::CallingConv::SPIR_KERNEL; |
| } |
| |
| llvm::Constant *TargetCodeGenInfo::getNullPointer(const CodeGen::CodeGenModule &CGM, |
| llvm::PointerType *T, QualType QT) const { |
| return llvm::ConstantPointerNull::get(T); |
| } |
| |
| LangAS TargetCodeGenInfo::getGlobalVarAddressSpace(CodeGenModule &CGM, |
| const VarDecl *D) const { |
| assert(!CGM.getLangOpts().OpenCL && |
| !(CGM.getLangOpts().CUDA && CGM.getLangOpts().CUDAIsDevice) && |
| "Address space agnostic languages only"); |
| return D ? D->getType().getAddressSpace() : LangAS::Default; |
| } |
| |
| llvm::Value *TargetCodeGenInfo::performAddrSpaceCast( |
| CodeGen::CodeGenFunction &CGF, llvm::Value *Src, LangAS SrcAddr, |
| LangAS DestAddr, llvm::Type *DestTy, bool isNonNull) const { |
| // Since target may map different address spaces in AST to the same address |
| // space, an address space conversion may end up as a bitcast. |
| if (auto *C = dyn_cast<llvm::Constant>(Src)) |
| return performAddrSpaceCast(CGF.CGM, C, SrcAddr, DestAddr, DestTy); |
| // Try to preserve the source's name to make IR more readable. |
| return CGF.Builder.CreatePointerBitCastOrAddrSpaceCast( |
| Src, DestTy, Src->hasName() ? Src->getName() + ".ascast" : ""); |
| } |
| |
| llvm::Constant * |
| TargetCodeGenInfo::performAddrSpaceCast(CodeGenModule &CGM, llvm::Constant *Src, |
| LangAS SrcAddr, LangAS DestAddr, |
| llvm::Type *DestTy) const { |
| // Since target may map different address spaces in AST to the same address |
| // space, an address space conversion may end up as a bitcast. |
| return llvm::ConstantExpr::getPointerCast(Src, DestTy); |
| } |
| |
| llvm::SyncScope::ID |
| TargetCodeGenInfo::getLLVMSyncScopeID(const LangOptions &LangOpts, |
| SyncScope Scope, |
| llvm::AtomicOrdering Ordering, |
| llvm::LLVMContext &Ctx) const { |
| return Ctx.getOrInsertSyncScopeID(""); /* default sync scope */ |
| } |
| |
| static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays); |
| |
| /// isEmptyField - Return true iff a the field is "empty", that is it |
| /// is an unnamed bit-field or an (array of) empty record(s). |
| static bool isEmptyField(ASTContext &Context, const FieldDecl *FD, |
| bool AllowArrays) { |
| if (FD->isUnnamedBitfield()) |
| return true; |
| |
| QualType FT = FD->getType(); |
| |
| // Constant arrays of empty records count as empty, strip them off. |
| // Constant arrays of zero length always count as empty. |
| bool WasArray = false; |
| if (AllowArrays) |
| while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) { |
| if (AT->getSize() == 0) |
| return true; |
| FT = AT->getElementType(); |
| // The [[no_unique_address]] special case below does not apply to |
| // arrays of C++ empty records, so we need to remember this fact. |
| WasArray = true; |
| } |
| |
| const RecordType *RT = FT->getAs<RecordType>(); |
| if (!RT) |
| return false; |
| |
| // C++ record fields are never empty, at least in the Itanium ABI. |
| // |
| // FIXME: We should use a predicate for whether this behavior is true in the |
| // current ABI. |
| // |
| // The exception to the above rule are fields marked with the |
| // [[no_unique_address]] attribute (since C++20). Those do count as empty |
| // according to the Itanium ABI. The exception applies only to records, |
| // not arrays of records, so we must also check whether we stripped off an |
| // array type above. |
| if (isa<CXXRecordDecl>(RT->getDecl()) && |
| (WasArray || !FD->hasAttr<NoUniqueAddressAttr>())) |
| return false; |
| |
| return isEmptyRecord(Context, FT, AllowArrays); |
| } |
| |
| /// isEmptyRecord - Return true iff a structure contains only empty |
| /// fields. Note that a structure with a flexible array member is not |
| /// considered empty. |
| static bool isEmptyRecord(ASTContext &Context, QualType T, bool AllowArrays) { |
| const RecordType *RT = T->getAs<RecordType>(); |
| if (!RT) |
| return false; |
| const RecordDecl *RD = RT->getDecl(); |
| if (RD->hasFlexibleArrayMember()) |
| return false; |
| |
| // If this is a C++ record, check the bases first. |
| if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) |
| for (const auto &I : CXXRD->bases()) |
| if (!isEmptyRecord(Context, I.getType(), true)) |
| return false; |
| |
| for (const auto *I : RD->fields()) |
| if (!isEmptyField(Context, I, AllowArrays)) |
| return false; |
| return true; |
| } |
| |
| /// isSingleElementStruct - Determine if a structure is a "single |
| /// element struct", i.e. it has exactly one non-empty field or |
| /// exactly one field which is itself a single element |
| /// struct. Structures with flexible array members are never |
| /// considered single element structs. |
| /// |
| /// \return The field declaration for the single non-empty field, if |
| /// it exists. |
| static const Type *isSingleElementStruct(QualType T, ASTContext &Context) { |
| const RecordType *RT = T->getAs<RecordType>(); |
| if (!RT) |
| return nullptr; |
| |
| const RecordDecl *RD = RT->getDecl(); |
| if (RD->hasFlexibleArrayMember()) |
| return nullptr; |
| |
| const Type *Found = nullptr; |
| |
| // If this is a C++ record, check the bases first. |
| if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { |
| for (const auto &I : CXXRD->bases()) { |
| // Ignore empty records. |
| if (isEmptyRecord(Context, I.getType(), true)) |
| continue; |
| |
| // If we already found an element then this isn't a single-element struct. |
| if (Found) |
| return nullptr; |
| |
| // If this is non-empty and not a single element struct, the composite |
| // cannot be a single element struct. |
| Found = isSingleElementStruct(I.getType(), Context); |
| if (!Found) |
| return nullptr; |
| } |
| } |
| |
| // Check for single element. |
| for (const auto *FD : RD->fields()) { |
| QualType FT = FD->getType(); |
| |
| // Ignore empty fields. |
| if (isEmptyField(Context, FD, true)) |
| continue; |
| |
| // If we already found an element then this isn't a single-element |
| // struct. |
| if (Found) |
| return nullptr; |
| |
| // Treat single element arrays as the element. |
| while (const ConstantArrayType *AT = Context.getAsConstantArrayType(FT)) { |
| if (AT->getSize().getZExtValue() != 1) |
| break; |
| FT = AT->getElementType(); |
| } |
| |
| if (!isAggregateTypeForABI(FT)) { |
| Found = FT.getTypePtr(); |
| } else { |
| Found = isSingleElementStruct(FT, Context); |
| if (!Found) |
| return nullptr; |
| } |
| } |
| |
| // We don't consider a struct a single-element struct if it has |
| // padding beyond the element type. |
| if (Found && Context.getTypeSize(Found) != Context.getTypeSize(T)) |
| return nullptr; |
| |
| return Found; |
| } |
| |
| namespace { |
| Address EmitVAArgInstr(CodeGenFunction &CGF, Address VAListAddr, QualType Ty, |
| const ABIArgInfo &AI) { |
| // This default implementation defers to the llvm backend's va_arg |
| // instruction. It can handle only passing arguments directly |
| // (typically only handled in the backend for primitive types), or |
| // aggregates passed indirectly by pointer (NOTE: if the "byval" |
| // flag has ABI impact in the callee, this implementation cannot |
| // work.) |
| |
| // Only a few cases are covered here at the moment -- those needed |
| // by the default abi. |
| llvm::Value *Val; |
| |
| if (AI.isIndirect()) { |
| assert(!AI.getPaddingType() && |
| "Unexpected PaddingType seen in arginfo in generic VAArg emitter!"); |
| assert( |
| !AI.getIndirectRealign() && |
| "Unexpected IndirectRealign seen in arginfo in generic VAArg emitter!"); |
| |
| auto TyInfo = CGF.getContext().getTypeInfoInChars(Ty); |
| CharUnits TyAlignForABI = TyInfo.Align; |
| |
| llvm::Type *BaseTy = |
| llvm::PointerType::getUnqual(CGF.ConvertTypeForMem(Ty)); |
| llvm::Value *Addr = |
| CGF.Builder.CreateVAArg(VAListAddr.getPointer(), BaseTy); |
| return Address(Addr, TyAlignForABI); |
| } else { |
| assert((AI.isDirect() || AI.isExtend()) && |
| "Unexpected ArgInfo Kind in generic VAArg emitter!"); |
| |
| assert(!AI.getInReg() && |
| "Unexpected InReg seen in arginfo in generic VAArg emitter!"); |
| assert(!AI.getPaddingType() && |
| "Unexpected PaddingType seen in arginfo in generic VAArg emitter!"); |
| assert(!AI.getDirectOffset() && |
| "Unexpected DirectOffset seen in arginfo in generic VAArg emitter!"); |
| assert(!AI.getCoerceToType() && |
| "Unexpected CoerceToType seen in arginfo in generic VAArg emitter!"); |
| |
| Address Temp = CGF.CreateMemTemp(Ty, "varet"); |
| Val = CGF.Builder.CreateVAArg(VAListAddr.getPointer(), CGF.ConvertType(Ty)); |
| CGF.Builder.CreateStore(Val, Temp); |
| return Temp; |
| } |
| } |
| |
| /// DefaultABIInfo - The default implementation for ABI specific |
| /// details. This implementation provides information which results in |
| /// self-consistent and sensible LLVM IR generation, but does not |
| /// conform to any particular ABI. |
| class DefaultABIInfo : public ABIInfo { |
| public: |
| DefaultABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {} |
| |
| ABIArgInfo classifyReturnType(QualType RetTy) const; |
| ABIArgInfo classifyArgumentType(QualType RetTy) const; |
| |
| void computeInfo(CGFunctionInfo &FI) const override { |
| if (!getCXXABI().classifyReturnType(FI)) |
| FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); |
| for (auto &I : FI.arguments()) |
| I.info = classifyArgumentType(I.type); |
| } |
| |
| Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, |
| QualType Ty) const override { |
| return EmitVAArgInstr(CGF, VAListAddr, Ty, classifyArgumentType(Ty)); |
| } |
| }; |
| |
| class DefaultTargetCodeGenInfo : public TargetCodeGenInfo { |
| public: |
| DefaultTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) |
| : TargetCodeGenInfo(std::make_unique<DefaultABIInfo>(CGT)) {} |
| }; |
| |
| ABIArgInfo DefaultABIInfo::classifyArgumentType(QualType Ty) const { |
| Ty = useFirstFieldIfTransparentUnion(Ty); |
| |
| if (isAggregateTypeForABI(Ty)) { |
| // Records with non-trivial destructors/copy-constructors should not be |
| // passed by value. |
| if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) |
| return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory); |
| |
| return getNaturalAlignIndirect(Ty); |
| } |
| |
| // Treat an enum type as its underlying type. |
| if (const EnumType *EnumTy = Ty->getAs<EnumType>()) |
| Ty = EnumTy->getDecl()->getIntegerType(); |
| |
| ASTContext &Context = getContext(); |
| if (const auto *EIT = Ty->getAs<ExtIntType>()) |
| if (EIT->getNumBits() > |
| Context.getTypeSize(Context.getTargetInfo().hasInt128Type() |
| ? Context.Int128Ty |
| : Context.LongLongTy)) |
| return getNaturalAlignIndirect(Ty); |
| |
| return (isPromotableIntegerTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty) |
| : ABIArgInfo::getDirect()); |
| } |
| |
| ABIArgInfo DefaultABIInfo::classifyReturnType(QualType RetTy) const { |
| if (RetTy->isVoidType()) |
| return ABIArgInfo::getIgnore(); |
| |
| if (isAggregateTypeForABI(RetTy)) |
| return getNaturalAlignIndirect(RetTy); |
| |
| // Treat an enum type as its underlying type. |
| if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) |
| RetTy = EnumTy->getDecl()->getIntegerType(); |
| |
| if (const auto *EIT = RetTy->getAs<ExtIntType>()) |
| if (EIT->getNumBits() > |
| getContext().getTypeSize(getContext().getTargetInfo().hasInt128Type() |
| ? getContext().Int128Ty |
| : getContext().LongLongTy)) |
| return getNaturalAlignIndirect(RetTy); |
| |
| return (isPromotableIntegerTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy) |
| : ABIArgInfo::getDirect()); |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // WebAssembly ABI Implementation |
| // |
| // This is a very simple ABI that relies a lot on DefaultABIInfo. |
| //===----------------------------------------------------------------------===// |
| |
| class WebAssemblyABIInfo final : public SwiftABIInfo { |
| public: |
| enum ABIKind { |
| MVP = 0, |
| ExperimentalMV = 1, |
| }; |
| |
| private: |
| DefaultABIInfo defaultInfo; |
| ABIKind Kind; |
| |
| public: |
| explicit WebAssemblyABIInfo(CodeGen::CodeGenTypes &CGT, ABIKind Kind) |
| : SwiftABIInfo(CGT), defaultInfo(CGT), Kind(Kind) {} |
| |
| private: |
| ABIArgInfo classifyReturnType(QualType RetTy) const; |
| ABIArgInfo classifyArgumentType(QualType Ty) const; |
| |
| // DefaultABIInfo's classifyReturnType and classifyArgumentType are |
| // non-virtual, but computeInfo and EmitVAArg are virtual, so we |
| // overload them. |
| void computeInfo(CGFunctionInfo &FI) const override { |
| if (!getCXXABI().classifyReturnType(FI)) |
| FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); |
| for (auto &Arg : FI.arguments()) |
| Arg.info = classifyArgumentType(Arg.type); |
| } |
| |
| Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, |
| QualType Ty) const override; |
| |
| bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars, |
| bool asReturnValue) const override { |
| return occupiesMoreThan(CGT, scalars, /*total*/ 4); |
| } |
| |
| bool isSwiftErrorInRegister() const override { |
| return false; |
| } |
| }; |
| |
| class WebAssemblyTargetCodeGenInfo final : public TargetCodeGenInfo { |
| public: |
| explicit WebAssemblyTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, |
| WebAssemblyABIInfo::ABIKind K) |
| : TargetCodeGenInfo(std::make_unique<WebAssemblyABIInfo>(CGT, K)) {} |
| |
| void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, |
| CodeGen::CodeGenModule &CGM) const override { |
| TargetCodeGenInfo::setTargetAttributes(D, GV, CGM); |
| if (const auto *FD = dyn_cast_or_null<FunctionDecl>(D)) { |
| if (const auto *Attr = FD->getAttr<WebAssemblyImportModuleAttr>()) { |
| llvm::Function *Fn = cast<llvm::Function>(GV); |
| llvm::AttrBuilder B; |
| B.addAttribute("wasm-import-module", Attr->getImportModule()); |
| Fn->addFnAttrs(B); |
| } |
| if (const auto *Attr = FD->getAttr<WebAssemblyImportNameAttr>()) { |
| llvm::Function *Fn = cast<llvm::Function>(GV); |
| llvm::AttrBuilder B; |
| B.addAttribute("wasm-import-name", Attr->getImportName()); |
| Fn->addFnAttrs(B); |
| } |
| if (const auto *Attr = FD->getAttr<WebAssemblyExportNameAttr>()) { |
| llvm::Function *Fn = cast<llvm::Function>(GV); |
| llvm::AttrBuilder B; |
| B.addAttribute("wasm-export-name", Attr->getExportName()); |
| Fn->addFnAttrs(B); |
| } |
| } |
| |
| if (auto *FD = dyn_cast_or_null<FunctionDecl>(D)) { |
| llvm::Function *Fn = cast<llvm::Function>(GV); |
| if (!FD->doesThisDeclarationHaveABody() && !FD->hasPrototype()) |
| Fn->addFnAttr("no-prototype"); |
| } |
| } |
| }; |
| |
| /// Classify argument of given type \p Ty. |
| ABIArgInfo WebAssemblyABIInfo::classifyArgumentType(QualType Ty) const { |
| Ty = useFirstFieldIfTransparentUnion(Ty); |
| |
| if (isAggregateTypeForABI(Ty)) { |
| // Records with non-trivial destructors/copy-constructors should not be |
| // passed by value. |
| if (auto RAA = getRecordArgABI(Ty, getCXXABI())) |
| return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory); |
| // Ignore empty structs/unions. |
| if (isEmptyRecord(getContext(), Ty, true)) |
| return ABIArgInfo::getIgnore(); |
| // Lower single-element structs to just pass a regular value. TODO: We |
| // could do reasonable-size multiple-element structs too, using getExpand(), |
| // though watch out for things like bitfields. |
| if (const Type *SeltTy = isSingleElementStruct(Ty, getContext())) |
| return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0))); |
| // For the experimental multivalue ABI, fully expand all other aggregates |
| if (Kind == ABIKind::ExperimentalMV) { |
| const RecordType *RT = Ty->getAs<RecordType>(); |
| assert(RT); |
| bool HasBitField = false; |
| for (auto *Field : RT->getDecl()->fields()) { |
| if (Field->isBitField()) { |
| HasBitField = true; |
| break; |
| } |
| } |
| if (!HasBitField) |
| return ABIArgInfo::getExpand(); |
| } |
| } |
| |
| // Otherwise just do the default thing. |
| return defaultInfo.classifyArgumentType(Ty); |
| } |
| |
| ABIArgInfo WebAssemblyABIInfo::classifyReturnType(QualType RetTy) const { |
| if (isAggregateTypeForABI(RetTy)) { |
| // Records with non-trivial destructors/copy-constructors should not be |
| // returned by value. |
| if (!getRecordArgABI(RetTy, getCXXABI())) { |
| // Ignore empty structs/unions. |
| if (isEmptyRecord(getContext(), RetTy, true)) |
| return ABIArgInfo::getIgnore(); |
| // Lower single-element structs to just return a regular value. TODO: We |
| // could do reasonable-size multiple-element structs too, using |
| // ABIArgInfo::getDirect(). |
| if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext())) |
| return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0))); |
| // For the experimental multivalue ABI, return all other aggregates |
| if (Kind == ABIKind::ExperimentalMV) |
| return ABIArgInfo::getDirect(); |
| } |
| } |
| |
| // Otherwise just do the default thing. |
| return defaultInfo.classifyReturnType(RetTy); |
| } |
| |
| Address WebAssemblyABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, |
| QualType Ty) const { |
| bool IsIndirect = isAggregateTypeForABI(Ty) && |
| !isEmptyRecord(getContext(), Ty, true) && |
| !isSingleElementStruct(Ty, getContext()); |
| return emitVoidPtrVAArg(CGF, VAListAddr, Ty, IsIndirect, |
| getContext().getTypeInfoInChars(Ty), |
| CharUnits::fromQuantity(4), |
| /*AllowHigherAlign=*/true); |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // le32/PNaCl bitcode ABI Implementation |
| // |
| // This is a simplified version of the x86_32 ABI. Arguments and return values |
| // are always passed on the stack. |
| //===----------------------------------------------------------------------===// |
| |
| class PNaClABIInfo : public ABIInfo { |
| public: |
| PNaClABIInfo(CodeGen::CodeGenTypes &CGT) : ABIInfo(CGT) {} |
| |
| ABIArgInfo classifyReturnType(QualType RetTy) const; |
| ABIArgInfo classifyArgumentType(QualType RetTy) const; |
| |
| void computeInfo(CGFunctionInfo &FI) const override; |
| Address EmitVAArg(CodeGenFunction &CGF, |
| Address VAListAddr, QualType Ty) const override; |
| }; |
| |
| class PNaClTargetCodeGenInfo : public TargetCodeGenInfo { |
| public: |
| PNaClTargetCodeGenInfo(CodeGen::CodeGenTypes &CGT) |
| : TargetCodeGenInfo(std::make_unique<PNaClABIInfo>(CGT)) {} |
| }; |
| |
| void PNaClABIInfo::computeInfo(CGFunctionInfo &FI) const { |
| if (!getCXXABI().classifyReturnType(FI)) |
| FI.getReturnInfo() = classifyReturnType(FI.getReturnType()); |
| |
| for (auto &I : FI.arguments()) |
| I.info = classifyArgumentType(I.type); |
| } |
| |
| Address PNaClABIInfo::EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, |
| QualType Ty) const { |
| // The PNaCL ABI is a bit odd, in that varargs don't use normal |
| // function classification. Structs get passed directly for varargs |
| // functions, through a rewriting transform in |
| // pnacl-llvm/lib/Transforms/NaCl/ExpandVarArgs.cpp, which allows |
| // this target to actually support a va_arg instructions with an |
| // aggregate type, unlike other targets. |
| return EmitVAArgInstr(CGF, VAListAddr, Ty, ABIArgInfo::getDirect()); |
| } |
| |
| /// Classify argument of given type \p Ty. |
| ABIArgInfo PNaClABIInfo::classifyArgumentType(QualType Ty) const { |
| if (isAggregateTypeForABI(Ty)) { |
| if (CGCXXABI::RecordArgABI RAA = getRecordArgABI(Ty, getCXXABI())) |
| return getNaturalAlignIndirect(Ty, RAA == CGCXXABI::RAA_DirectInMemory); |
| return getNaturalAlignIndirect(Ty); |
| } else if (const EnumType *EnumTy = Ty->getAs<EnumType>()) { |
| // Treat an enum type as its underlying type. |
| Ty = EnumTy->getDecl()->getIntegerType(); |
| } else if (Ty->isFloatingType()) { |
| // Floating-point types don't go inreg. |
| return ABIArgInfo::getDirect(); |
| } else if (const auto *EIT = Ty->getAs<ExtIntType>()) { |
| // Treat extended integers as integers if <=64, otherwise pass indirectly. |
| if (EIT->getNumBits() > 64) |
| return getNaturalAlignIndirect(Ty); |
| return ABIArgInfo::getDirect(); |
| } |
| |
| return (isPromotableIntegerTypeForABI(Ty) ? ABIArgInfo::getExtend(Ty) |
| : ABIArgInfo::getDirect()); |
| } |
| |
| ABIArgInfo PNaClABIInfo::classifyReturnType(QualType RetTy) const { |
| if (RetTy->isVoidType()) |
| return ABIArgInfo::getIgnore(); |
| |
| // In the PNaCl ABI we always return records/structures on the stack. |
| if (isAggregateTypeForABI(RetTy)) |
| return getNaturalAlignIndirect(RetTy); |
| |
| // Treat extended integers as integers if <=64, otherwise pass indirectly. |
| if (const auto *EIT = RetTy->getAs<ExtIntType>()) { |
| if (EIT->getNumBits() > 64) |
| return getNaturalAlignIndirect(RetTy); |
| return ABIArgInfo::getDirect(); |
| } |
| |
| // Treat an enum type as its underlying type. |
| if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) |
| RetTy = EnumTy->getDecl()->getIntegerType(); |
| |
| return (isPromotableIntegerTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy) |
| : ABIArgInfo::getDirect()); |
| } |
| |
| /// IsX86_MMXType - Return true if this is an MMX type. |
| bool IsX86_MMXType(llvm::Type *IRType) { |
| // Return true if the type is an MMX type <2 x i32>, <4 x i16>, or <8 x i8>. |
| return IRType->isVectorTy() && IRType->getPrimitiveSizeInBits() == 64 && |
| cast<llvm::VectorType>(IRType)->getElementType()->isIntegerTy() && |
| IRType->getScalarSizeInBits() != 64; |
| } |
| |
| static llvm::Type* X86AdjustInlineAsmType(CodeGen::CodeGenFunction &CGF, |
| StringRef Constraint, |
| llvm::Type* Ty) { |
| bool IsMMXCons = llvm::StringSwitch<bool>(Constraint) |
| .Cases("y", "&y", "^Ym", true) |
| .Default(false); |
| if (IsMMXCons && Ty->isVectorTy()) { |
| if (cast<llvm::VectorType>(Ty)->getPrimitiveSizeInBits().getFixedSize() != |
| 64) { |
| // Invalid MMX constraint |
| return nullptr; |
| } |
| |
| return llvm::Type::getX86_MMXTy(CGF.getLLVMContext()); |
| } |
| |
| // No operation needed |
| return Ty; |
| } |
| |
| /// Returns true if this type can be passed in SSE registers with the |
| /// X86_VectorCall calling convention. Shared between x86_32 and x86_64. |
| static bool isX86VectorTypeForVectorCall(ASTContext &Context, QualType Ty) { |
| if (const BuiltinType *BT = Ty->getAs<BuiltinType>()) { |
| if (BT->isFloatingPoint() && BT->getKind() != BuiltinType::Half) { |
| if (BT->getKind() == BuiltinType::LongDouble) { |
| if (&Context.getTargetInfo().getLongDoubleFormat() == |
| &llvm::APFloat::x87DoubleExtended()) |
| return false; |
| } |
| return true; |
| } |
| } else if (const VectorType *VT = Ty->getAs<VectorType>()) { |
| // vectorcall can pass XMM, YMM, and ZMM vectors. We don't pass SSE1 MMX |
| // registers specially. |
| unsigned VecSize = Context.getTypeSize(VT); |
| if (VecSize == 128 || VecSize == 256 || VecSize == 512) |
| return true; |
| } |
| return false; |
| } |
| |
| /// Returns true if this aggregate is small enough to be passed in SSE registers |
| /// in the X86_VectorCall calling convention. Shared between x86_32 and x86_64. |
| static bool isX86VectorCallAggregateSmallEnough(uint64_t NumMembers) { |
| return NumMembers <= 4; |
| } |
| |
| /// Returns a Homogeneous Vector Aggregate ABIArgInfo, used in X86. |
| static ABIArgInfo getDirectX86Hva(llvm::Type* T = nullptr) { |
| auto AI = ABIArgInfo::getDirect(T); |
| AI.setInReg(true); |
| AI.setCanBeFlattened(false); |
| return AI; |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // X86-32 ABI Implementation |
| //===----------------------------------------------------------------------===// |
| |
| /// Similar to llvm::CCState, but for Clang. |
| struct CCState { |
| CCState(CGFunctionInfo &FI) |
| : IsPreassigned(FI.arg_size()), CC(FI.getCallingConvention()) {} |
| |
| llvm::SmallBitVector IsPreassigned; |
| unsigned CC = CallingConv::CC_C; |
| unsigned FreeRegs = 0; |
| unsigned FreeSSERegs = 0; |
| }; |
| |
| /// X86_32ABIInfo - The X86-32 ABI information. |
| class X86_32ABIInfo : public SwiftABIInfo { |
| enum Class { |
| Integer, |
| Float |
| }; |
| |
| static const unsigned MinABIStackAlignInBytes = 4; |
| |
| bool IsDarwinVectorABI; |
| bool IsRetSmallStructInRegABI; |
| bool IsWin32StructABI; |
| bool IsSoftFloatABI; |
| bool IsMCUABI; |
| bool IsLinuxABI; |
| unsigned DefaultNumRegisterParameters; |
| |
| static bool isRegisterSize(unsigned Size) { |
| return (Size == 8 || Size == 16 || Size == 32 || Size == 64); |
| } |
| |
| bool isHomogeneousAggregateBaseType(QualType Ty) const override { |
| // FIXME: Assumes vectorcall is in use. |
| return isX86VectorTypeForVectorCall(getContext(), Ty); |
| } |
| |
| bool isHomogeneousAggregateSmallEnough(const Type *Ty, |
| uint64_t NumMembers) const override { |
| // FIXME: Assumes vectorcall is in use. |
| return isX86VectorCallAggregateSmallEnough(NumMembers); |
| } |
| |
| bool shouldReturnTypeInRegister(QualType Ty, ASTContext &Context) const; |
| |
| /// getIndirectResult - Give a source type \arg Ty, return a suitable result |
| /// such that the argument will be passed in memory. |
| ABIArgInfo getIndirectResult(QualType Ty, bool ByVal, CCState &State) const; |
| |
| ABIArgInfo getIndirectReturnResult(QualType Ty, CCState &State) const; |
| |
| /// Return the alignment to use for the given type on the stack. |
| unsigned getTypeStackAlignInBytes(QualType Ty, unsigned Align) const; |
| |
| Class classify(QualType Ty) const; |
| ABIArgInfo classifyReturnType(QualType RetTy, CCState &State) const; |
| ABIArgInfo classifyArgumentType(QualType RetTy, CCState &State) const; |
| |
| /// Updates the number of available free registers, returns |
| /// true if any registers were allocated. |
| bool updateFreeRegs(QualType Ty, CCState &State) const; |
| |
| bool shouldAggregateUseDirect(QualType Ty, CCState &State, bool &InReg, |
| bool &NeedsPadding) const; |
| bool shouldPrimitiveUseInReg(QualType Ty, CCState &State) const; |
| |
| bool canExpandIndirectArgument(QualType Ty) const; |
| |
| /// Rewrite the function info so that all memory arguments use |
| /// inalloca. |
| void rewriteWithInAlloca(CGFunctionInfo &FI) const; |
| |
| void addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields, |
| CharUnits &StackOffset, ABIArgInfo &Info, |
| QualType Type) const; |
| void runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const; |
| |
| public: |
| |
| void computeInfo(CGFunctionInfo &FI) const override; |
| Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, |
| QualType Ty) const override; |
| |
| X86_32ABIInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI, |
| bool RetSmallStructInRegABI, bool Win32StructABI, |
| unsigned NumRegisterParameters, bool SoftFloatABI) |
| : SwiftABIInfo(CGT), IsDarwinVectorABI(DarwinVectorABI), |
| IsRetSmallStructInRegABI(RetSmallStructInRegABI), |
| IsWin32StructABI(Win32StructABI), IsSoftFloatABI(SoftFloatABI), |
| IsMCUABI(CGT.getTarget().getTriple().isOSIAMCU()), |
| IsLinuxABI(CGT.getTarget().getTriple().isOSLinux() || |
| CGT.getTarget().getTriple().isOSCygMing()), |
| DefaultNumRegisterParameters(NumRegisterParameters) {} |
| |
| bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars, |
| bool asReturnValue) const override { |
| // LLVM's x86-32 lowering currently only assigns up to three |
| // integer registers and three fp registers. Oddly, it'll use up to |
| // four vector registers for vectors, but those can overlap with the |
| // scalar registers. |
| return occupiesMoreThan(CGT, scalars, /*total*/ 3); |
| } |
| |
| bool isSwiftErrorInRegister() const override { |
| // x86-32 lowering does not support passing swifterror in a register. |
| return false; |
| } |
| }; |
| |
| class X86_32TargetCodeGenInfo : public TargetCodeGenInfo { |
| public: |
| X86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, bool DarwinVectorABI, |
| bool RetSmallStructInRegABI, bool Win32StructABI, |
| unsigned NumRegisterParameters, bool SoftFloatABI) |
| : TargetCodeGenInfo(std::make_unique<X86_32ABIInfo>( |
| CGT, DarwinVectorABI, RetSmallStructInRegABI, Win32StructABI, |
| NumRegisterParameters, SoftFloatABI)) {} |
| |
| static bool isStructReturnInRegABI( |
| const llvm::Triple &Triple, const CodeGenOptions &Opts); |
| |
| void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, |
| CodeGen::CodeGenModule &CGM) const override; |
| |
| int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override { |
| // Darwin uses different dwarf register numbers for EH. |
| if (CGM.getTarget().getTriple().isOSDarwin()) return 5; |
| return 4; |
| } |
| |
| bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, |
| llvm::Value *Address) const override; |
| |
| llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF, |
| StringRef Constraint, |
| llvm::Type* Ty) const override { |
| return X86AdjustInlineAsmType(CGF, Constraint, Ty); |
| } |
| |
| void addReturnRegisterOutputs(CodeGenFunction &CGF, LValue ReturnValue, |
| std::string &Constraints, |
| std::vector<llvm::Type *> &ResultRegTypes, |
| std::vector<llvm::Type *> &ResultTruncRegTypes, |
| std::vector<LValue> &ResultRegDests, |
| std::string &AsmString, |
| unsigned NumOutputs) const override; |
| |
| llvm::Constant * |
| getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override { |
| unsigned Sig = (0xeb << 0) | // jmp rel8 |
| (0x06 << 8) | // .+0x08 |
| ('v' << 16) | |
| ('2' << 24); |
| return llvm::ConstantInt::get(CGM.Int32Ty, Sig); |
| } |
| |
| StringRef getARCRetainAutoreleasedReturnValueMarker() const override { |
| return "movl\t%ebp, %ebp" |
| "\t\t// marker for objc_retainAutoreleaseReturnValue"; |
| } |
| }; |
| |
| } |
| |
| /// Rewrite input constraint references after adding some output constraints. |
| /// In the case where there is one output and one input and we add one output, |
| /// we need to replace all operand references greater than or equal to 1: |
| /// mov $0, $1 |
| /// mov eax, $1 |
| /// The result will be: |
| /// mov $0, $2 |
| /// mov eax, $2 |
| static void rewriteInputConstraintReferences(unsigned FirstIn, |
| unsigned NumNewOuts, |
| std::string &AsmString) { |
| std::string Buf; |
| llvm::raw_string_ostream OS(Buf); |
| size_t Pos = 0; |
| while (Pos < AsmString.size()) { |
| size_t DollarStart = AsmString.find('$', Pos); |
| if (DollarStart == std::string::npos) |
| DollarStart = AsmString.size(); |
| size_t DollarEnd = AsmString.find_first_not_of('$', DollarStart); |
| if (DollarEnd == std::string::npos) |
| DollarEnd = AsmString.size(); |
| OS << StringRef(&AsmString[Pos], DollarEnd - Pos); |
| Pos = DollarEnd; |
| size_t NumDollars = DollarEnd - DollarStart; |
| if (NumDollars % 2 != 0 && Pos < AsmString.size()) { |
| // We have an operand reference. |
| size_t DigitStart = Pos; |
| if (AsmString[DigitStart] == '{') { |
| OS << '{'; |
| ++DigitStart; |
| } |
| size_t DigitEnd = AsmString.find_first_not_of("0123456789", DigitStart); |
| if (DigitEnd == std::string::npos) |
| DigitEnd = AsmString.size(); |
| StringRef OperandStr(&AsmString[DigitStart], DigitEnd - DigitStart); |
| unsigned OperandIndex; |
| if (!OperandStr.getAsInteger(10, OperandIndex)) { |
| if (OperandIndex >= FirstIn) |
| OperandIndex += NumNewOuts; |
| OS << OperandIndex; |
| } else { |
| OS << OperandStr; |
| } |
| Pos = DigitEnd; |
| } |
| } |
| AsmString = std::move(OS.str()); |
| } |
| |
| /// Add output constraints for EAX:EDX because they are return registers. |
| void X86_32TargetCodeGenInfo::addReturnRegisterOutputs( |
| CodeGenFunction &CGF, LValue ReturnSlot, std::string &Constraints, |
| std::vector<llvm::Type *> &ResultRegTypes, |
| std::vector<llvm::Type *> &ResultTruncRegTypes, |
| std::vector<LValue> &ResultRegDests, std::string &AsmString, |
| unsigned NumOutputs) const { |
| uint64_t RetWidth = CGF.getContext().getTypeSize(ReturnSlot.getType()); |
| |
| // Use the EAX constraint if the width is 32 or smaller and EAX:EDX if it is |
| // larger. |
| if (!Constraints.empty()) |
| Constraints += ','; |
| if (RetWidth <= 32) { |
| Constraints += "={eax}"; |
| ResultRegTypes.push_back(CGF.Int32Ty); |
| } else { |
| // Use the 'A' constraint for EAX:EDX. |
| Constraints += "=A"; |
| ResultRegTypes.push_back(CGF.Int64Ty); |
| } |
| |
| // Truncate EAX or EAX:EDX to an integer of the appropriate size. |
| llvm::Type *CoerceTy = llvm::IntegerType::get(CGF.getLLVMContext(), RetWidth); |
| ResultTruncRegTypes.push_back(CoerceTy); |
| |
| // Coerce the integer by bitcasting the return slot pointer. |
| ReturnSlot.setAddress(CGF.Builder.CreateBitCast(ReturnSlot.getAddress(CGF), |
| CoerceTy->getPointerTo())); |
| ResultRegDests.push_back(ReturnSlot); |
| |
| rewriteInputConstraintReferences(NumOutputs, 1, AsmString); |
| } |
| |
| /// shouldReturnTypeInRegister - Determine if the given type should be |
| /// returned in a register (for the Darwin and MCU ABI). |
| bool X86_32ABIInfo::shouldReturnTypeInRegister(QualType Ty, |
| ASTContext &Context) const { |
| uint64_t Size = Context.getTypeSize(Ty); |
| |
| // For i386, type must be register sized. |
| // For the MCU ABI, it only needs to be <= 8-byte |
| if ((IsMCUABI && Size > 64) || (!IsMCUABI && !isRegisterSize(Size))) |
| return false; |
| |
| if (Ty->isVectorType()) { |
| // 64- and 128- bit vectors inside structures are not returned in |
| // registers. |
| if (Size == 64 || Size == 128) |
| return false; |
| |
| return true; |
| } |
| |
| // If this is a builtin, pointer, enum, complex type, member pointer, or |
| // member function pointer it is ok. |
| if (Ty->getAs<BuiltinType>() || Ty->hasPointerRepresentation() || |
| Ty->isAnyComplexType() || Ty->isEnumeralType() || |
| Ty->isBlockPointerType() || Ty->isMemberPointerType()) |
| return true; |
| |
| // Arrays are treated like records. |
| if (const ConstantArrayType *AT = Context.getAsConstantArrayType(Ty)) |
| return shouldReturnTypeInRegister(AT->getElementType(), Context); |
| |
| // Otherwise, it must be a record type. |
| const RecordType *RT = Ty->getAs<RecordType>(); |
| if (!RT) return false; |
| |
| // FIXME: Traverse bases here too. |
| |
| // Structure types are passed in register if all fields would be |
| // passed in a register. |
| for (const auto *FD : RT->getDecl()->fields()) { |
| // Empty fields are ignored. |
| if (isEmptyField(Context, FD, true)) |
| continue; |
| |
| // Check fields recursively. |
| if (!shouldReturnTypeInRegister(FD->getType(), Context)) |
| return false; |
| } |
| return true; |
| } |
| |
| static bool is32Or64BitBasicType(QualType Ty, ASTContext &Context) { |
| // Treat complex types as the element type. |
| if (const ComplexType *CTy = Ty->getAs<ComplexType>()) |
| Ty = CTy->getElementType(); |
| |
| // Check for a type which we know has a simple scalar argument-passing |
| // convention without any padding. (We're specifically looking for 32 |
| // and 64-bit integer and integer-equivalents, float, and double.) |
| if (!Ty->getAs<BuiltinType>() && !Ty->hasPointerRepresentation() && |
| !Ty->isEnumeralType() && !Ty->isBlockPointerType()) |
| return false; |
| |
| uint64_t Size = Context.getTypeSize(Ty); |
| return Size == 32 || Size == 64; |
| } |
| |
| static bool addFieldSizes(ASTContext &Context, const RecordDecl *RD, |
| uint64_t &Size) { |
| for (const auto *FD : RD->fields()) { |
| // Scalar arguments on the stack get 4 byte alignment on x86. If the |
| // argument is smaller than 32-bits, expanding the struct will create |
| // alignment padding. |
| if (!is32Or64BitBasicType(FD->getType(), Context)) |
| return false; |
| |
| // FIXME: Reject bit-fields wholesale; there are two problems, we don't know |
| // how to expand them yet, and the predicate for telling if a bitfield still |
| // counts as "basic" is more complicated than what we were doing previously. |
| if (FD->isBitField()) |
| return false; |
| |
| Size += Context.getTypeSize(FD->getType()); |
| } |
| return true; |
| } |
| |
| static bool addBaseAndFieldSizes(ASTContext &Context, const CXXRecordDecl *RD, |
| uint64_t &Size) { |
| // Don't do this if there are any non-empty bases. |
| for (const CXXBaseSpecifier &Base : RD->bases()) { |
| if (!addBaseAndFieldSizes(Context, Base.getType()->getAsCXXRecordDecl(), |
| Size)) |
| return false; |
| } |
| if (!addFieldSizes(Context, RD, Size)) |
| return false; |
| return true; |
| } |
| |
| /// Test whether an argument type which is to be passed indirectly (on the |
| /// stack) would have the equivalent layout if it was expanded into separate |
| /// arguments. If so, we prefer to do the latter to avoid inhibiting |
| /// optimizations. |
| bool X86_32ABIInfo::canExpandIndirectArgument(QualType Ty) const { |
| // We can only expand structure types. |
| const RecordType *RT = Ty->getAs<RecordType>(); |
| if (!RT) |
| return false; |
| const RecordDecl *RD = RT->getDecl(); |
| uint64_t Size = 0; |
| if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) { |
| if (!IsWin32StructABI) { |
| // On non-Windows, we have to conservatively match our old bitcode |
| // prototypes in order to be ABI-compatible at the bitcode level. |
| if (!CXXRD->isCLike()) |
| return false; |
| } else { |
| // Don't do this for dynamic classes. |
| if (CXXRD->isDynamicClass()) |
| return false; |
| } |
| if (!addBaseAndFieldSizes(getContext(), CXXRD, Size)) |
| return false; |
| } else { |
| if (!addFieldSizes(getContext(), RD, Size)) |
| return false; |
| } |
| |
| // We can do this if there was no alignment padding. |
| return Size == getContext().getTypeSize(Ty); |
| } |
| |
| ABIArgInfo X86_32ABIInfo::getIndirectReturnResult(QualType RetTy, CCState &State) const { |
| // If the return value is indirect, then the hidden argument is consuming one |
| // integer register. |
| if (State.FreeRegs) { |
| --State.FreeRegs; |
| if (!IsMCUABI) |
| return getNaturalAlignIndirectInReg(RetTy); |
| } |
| return getNaturalAlignIndirect(RetTy, /*ByVal=*/false); |
| } |
| |
| ABIArgInfo X86_32ABIInfo::classifyReturnType(QualType RetTy, |
| CCState &State) const { |
| if (RetTy->isVoidType()) |
| return ABIArgInfo::getIgnore(); |
| |
| const Type *Base = nullptr; |
| uint64_t NumElts = 0; |
| if ((State.CC == llvm::CallingConv::X86_VectorCall || |
| State.CC == llvm::CallingConv::X86_RegCall) && |
| isHomogeneousAggregate(RetTy, Base, NumElts)) { |
| // The LLVM struct type for such an aggregate should lower properly. |
| return ABIArgInfo::getDirect(); |
| } |
| |
| if (const VectorType *VT = RetTy->getAs<VectorType>()) { |
| // On Darwin, some vectors are returned in registers. |
| if (IsDarwinVectorABI) { |
| uint64_t Size = getContext().getTypeSize(RetTy); |
| |
| // 128-bit vectors are a special case; they are returned in |
| // registers and we need to make sure to pick a type the LLVM |
| // backend will like. |
| if (Size == 128) |
| return ABIArgInfo::getDirect(llvm::FixedVectorType::get( |
| llvm::Type::getInt64Ty(getVMContext()), 2)); |
| |
| // Always return in register if it fits in a general purpose |
| // register, or if it is 64 bits and has a single element. |
| if ((Size == 8 || Size == 16 || Size == 32) || |
| (Size == 64 && VT->getNumElements() == 1)) |
| return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), |
| Size)); |
| |
| return getIndirectReturnResult(RetTy, State); |
| } |
| |
| return ABIArgInfo::getDirect(); |
| } |
| |
| if (isAggregateTypeForABI(RetTy)) { |
| if (const RecordType *RT = RetTy->getAs<RecordType>()) { |
| // Structures with flexible arrays are always indirect. |
| if (RT->getDecl()->hasFlexibleArrayMember()) |
| return getIndirectReturnResult(RetTy, State); |
| } |
| |
| // If specified, structs and unions are always indirect. |
| if (!IsRetSmallStructInRegABI && !RetTy->isAnyComplexType()) |
| return getIndirectReturnResult(RetTy, State); |
| |
| // Ignore empty structs/unions. |
| if (isEmptyRecord(getContext(), RetTy, true)) |
| return ABIArgInfo::getIgnore(); |
| |
| // Return complex of _Float16 as <2 x half> so the backend will use xmm0. |
| if (const ComplexType *CT = RetTy->getAs<ComplexType>()) { |
| QualType ET = getContext().getCanonicalType(CT->getElementType()); |
| if (ET->isFloat16Type()) |
| return ABIArgInfo::getDirect(llvm::FixedVectorType::get( |
| llvm::Type::getHalfTy(getVMContext()), 2)); |
| } |
| |
| // Small structures which are register sized are generally returned |
| // in a register. |
| if (shouldReturnTypeInRegister(RetTy, getContext())) { |
| uint64_t Size = getContext().getTypeSize(RetTy); |
| |
| // As a special-case, if the struct is a "single-element" struct, and |
| // the field is of type "float" or "double", return it in a |
| // floating-point register. (MSVC does not apply this special case.) |
| // We apply a similar transformation for pointer types to improve the |
| // quality of the generated IR. |
| if (const Type *SeltTy = isSingleElementStruct(RetTy, getContext())) |
| if ((!IsWin32StructABI && SeltTy->isRealFloatingType()) |
| || SeltTy->hasPointerRepresentation()) |
| return ABIArgInfo::getDirect(CGT.ConvertType(QualType(SeltTy, 0))); |
| |
| // FIXME: We should be able to narrow this integer in cases with dead |
| // padding. |
| return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(),Size)); |
| } |
| |
| return getIndirectReturnResult(RetTy, State); |
| } |
| |
| // Treat an enum type as its underlying type. |
| if (const EnumType *EnumTy = RetTy->getAs<EnumType>()) |
| RetTy = EnumTy->getDecl()->getIntegerType(); |
| |
| if (const auto *EIT = RetTy->getAs<ExtIntType>()) |
| if (EIT->getNumBits() > 64) |
| return getIndirectReturnResult(RetTy, State); |
| |
| return (isPromotableIntegerTypeForABI(RetTy) ? ABIArgInfo::getExtend(RetTy) |
| : ABIArgInfo::getDirect()); |
| } |
| |
| static bool isSIMDVectorType(ASTContext &Context, QualType Ty) { |
| return Ty->getAs<VectorType>() && Context.getTypeSize(Ty) == 128; |
| } |
| |
| static bool isRecordWithSIMDVectorType(ASTContext &Context, QualType Ty) { |
| const RecordType *RT = Ty->getAs<RecordType>(); |
| if (!RT) |
| return 0; |
| const RecordDecl *RD = RT->getDecl(); |
| |
| // If this is a C++ record, check the bases first. |
| if (const CXXRecordDecl *CXXRD = dyn_cast<CXXRecordDecl>(RD)) |
| for (const auto &I : CXXRD->bases()) |
| if (!isRecordWithSIMDVectorType(Context, I.getType())) |
| return false; |
| |
| for (const auto *i : RD->fields()) { |
| QualType FT = i->getType(); |
| |
| if (isSIMDVectorType(Context, FT)) |
| return true; |
| |
| if (isRecordWithSIMDVectorType(Context, FT)) |
| return true; |
| } |
| |
| return false; |
| } |
| |
| unsigned X86_32ABIInfo::getTypeStackAlignInBytes(QualType Ty, |
| unsigned Align) const { |
| // Otherwise, if the alignment is less than or equal to the minimum ABI |
| // alignment, just use the default; the backend will handle this. |
| if (Align <= MinABIStackAlignInBytes) |
| return 0; // Use default alignment. |
| |
| if (IsLinuxABI) { |
| // Exclude other System V OS (e.g Darwin, PS4 and FreeBSD) since we don't |
| // want to spend any effort dealing with the ramifications of ABI breaks. |
| // |
| // If the vector type is __m128/__m256/__m512, return the default alignment. |
| if (Ty->isVectorType() && (Align == 16 || Align == 32 || Align == 64)) |
| return Align; |
| } |
| // On non-Darwin, the stack type alignment is always 4. |
| if (!IsDarwinVectorABI) { |
| // Set explicit alignment, since we may need to realign the top. |
| return MinABIStackAlignInBytes; |
| } |
| |
| // Otherwise, if the type contains an SSE vector type, the alignment is 16. |
| if (Align >= 16 && (isSIMDVectorType(getContext(), Ty) || |
| isRecordWithSIMDVectorType(getContext(), Ty))) |
| return 16; |
| |
| return MinABIStackAlignInBytes; |
| } |
| |
| ABIArgInfo X86_32ABIInfo::getIndirectResult(QualType Ty, bool ByVal, |
| CCState &State) const { |
| if (!ByVal) { |
| if (State.FreeRegs) { |
| --State.FreeRegs; // Non-byval indirects just use one pointer. |
| if (!IsMCUABI) |
| return getNaturalAlignIndirectInReg(Ty); |
| } |
| return getNaturalAlignIndirect(Ty, false); |
| } |
| |
| // Compute the byval alignment. |
| unsigned TypeAlign = getContext().getTypeAlign(Ty) / 8; |
| unsigned StackAlign = getTypeStackAlignInBytes(Ty, TypeAlign); |
| if (StackAlign == 0) |
| return ABIArgInfo::getIndirect(CharUnits::fromQuantity(4), /*ByVal=*/true); |
| |
| // If the stack alignment is less than the type alignment, realign the |
| // argument. |
| bool Realign = TypeAlign > StackAlign; |
| return ABIArgInfo::getIndirect(CharUnits::fromQuantity(StackAlign), |
| /*ByVal=*/true, Realign); |
| } |
| |
| X86_32ABIInfo::Class X86_32ABIInfo::classify(QualType Ty) const { |
| const Type *T = isSingleElementStruct(Ty, getContext()); |
| if (!T) |
| T = Ty.getTypePtr(); |
| |
| if (const BuiltinType *BT = T->getAs<BuiltinType>()) { |
| BuiltinType::Kind K = BT->getKind(); |
| if (K == BuiltinType::Float || K == BuiltinType::Double) |
| return Float; |
| } |
| return Integer; |
| } |
| |
| bool X86_32ABIInfo::updateFreeRegs(QualType Ty, CCState &State) const { |
| if (!IsSoftFloatABI) { |
| Class C = classify(Ty); |
| if (C == Float) |
| return false; |
| } |
| |
| unsigned Size = getContext().getTypeSize(Ty); |
| unsigned SizeInRegs = (Size + 31) / 32; |
| |
| if (SizeInRegs == 0) |
| return false; |
| |
| if (!IsMCUABI) { |
| if (SizeInRegs > State.FreeRegs) { |
| State.FreeRegs = 0; |
| return false; |
| } |
| } else { |
| // The MCU psABI allows passing parameters in-reg even if there are |
| // earlier parameters that are passed on the stack. Also, |
| // it does not allow passing >8-byte structs in-register, |
| // even if there are 3 free registers available. |
| if (SizeInRegs > State.FreeRegs || SizeInRegs > 2) |
| return false; |
| } |
| |
| State.FreeRegs -= SizeInRegs; |
| return true; |
| } |
| |
| bool X86_32ABIInfo::shouldAggregateUseDirect(QualType Ty, CCState &State, |
| bool &InReg, |
| bool &NeedsPadding) const { |
| // On Windows, aggregates other than HFAs are never passed in registers, and |
| // they do not consume register slots. Homogenous floating-point aggregates |
| // (HFAs) have already been dealt with at this point. |
| if (IsWin32StructABI && isAggregateTypeForABI(Ty)) |
| return false; |
| |
| NeedsPadding = false; |
| InReg = !IsMCUABI; |
| |
| if (!updateFreeRegs(Ty, State)) |
| return false; |
| |
| if (IsMCUABI) |
| return true; |
| |
| if (State.CC == llvm::CallingConv::X86_FastCall || |
| State.CC == llvm::CallingConv::X86_VectorCall || |
| State.CC == llvm::CallingConv::X86_RegCall) { |
| if (getContext().getTypeSize(Ty) <= 32 && State.FreeRegs) |
| NeedsPadding = true; |
| |
| return false; |
| } |
| |
| return true; |
| } |
| |
| bool X86_32ABIInfo::shouldPrimitiveUseInReg(QualType Ty, CCState &State) const { |
| if (!updateFreeRegs(Ty, State)) |
| return false; |
| |
| if (IsMCUABI) |
| return false; |
| |
| if (State.CC == llvm::CallingConv::X86_FastCall || |
| State.CC == llvm::CallingConv::X86_VectorCall || |
| State.CC == llvm::CallingConv::X86_RegCall) { |
| if (getContext().getTypeSize(Ty) > 32) |
| return false; |
| |
| return (Ty->isIntegralOrEnumerationType() || Ty->isPointerType() || |
| Ty->isReferenceType()); |
| } |
| |
| return true; |
| } |
| |
| void X86_32ABIInfo::runVectorCallFirstPass(CGFunctionInfo &FI, CCState &State) const { |
| // Vectorcall x86 works subtly different than in x64, so the format is |
| // a bit different than the x64 version. First, all vector types (not HVAs) |
| // are assigned, with the first 6 ending up in the [XYZ]MM0-5 registers. |
| // This differs from the x64 implementation, where the first 6 by INDEX get |
| // registers. |
| // In the second pass over the arguments, HVAs are passed in the remaining |
| // vector registers if possible, or indirectly by address. The address will be |
| // passed in ECX/EDX if available. Any other arguments are passed according to |
| // the usual fastcall rules. |
| MutableArrayRef<CGFunctionInfoArgInfo> Args = FI.arguments(); |
| for (int I = 0, E = Args.size(); I < E; ++I) { |
| const Type *Base = nullptr; |
| uint64_t NumElts = 0; |
| const QualType &Ty = Args[I].type; |
| if ((Ty->isVectorType() || Ty->isBuiltinType()) && |
| isHomogeneousAggregate(Ty, Base, NumElts)) { |
| if (State.FreeSSERegs >= NumElts) { |
| State.FreeSSERegs -= NumElts; |
| Args[I].info = ABIArgInfo::getDirectInReg(); |
| State.IsPreassigned.set(I); |
| } |
| } |
| } |
| } |
| |
| ABIArgInfo X86_32ABIInfo::classifyArgumentType(QualType Ty, |
| CCState &State) const { |
| // FIXME: Set alignment on indirect arguments. |
| bool IsFastCall = State.CC == llvm::CallingConv::X86_FastCall; |
| bool IsRegCall = State.CC == llvm::CallingConv::X86_RegCall; |
| bool IsVectorCall = State.CC == llvm::CallingConv::X86_VectorCall; |
| |
| Ty = useFirstFieldIfTransparentUnion(Ty); |
| TypeInfo TI = getContext().getTypeInfo(Ty); |
| |
| // Check with the C++ ABI first. |
| const RecordType *RT = Ty->getAs<RecordType>(); |
| if (RT) { |
| CGCXXABI::RecordArgABI RAA = getRecordArgABI(RT, getCXXABI()); |
| if (RAA == CGCXXABI::RAA_Indirect) { |
| return getIndirectResult(Ty, false, State); |
| } else if (RAA == CGCXXABI::RAA_DirectInMemory) { |
| // The field index doesn't matter, we'll fix it up later. |
| return ABIArgInfo::getInAlloca(/*FieldIndex=*/0); |
| } |
| } |
| |
| // Regcall uses the concept of a homogenous vector aggregate, similar |
| // to other targets. |
| const Type *Base = nullptr; |
| uint64_t NumElts = 0; |
| if ((IsRegCall || IsVectorCall) && |
| isHomogeneousAggregate(Ty, Base, NumElts)) { |
| if (State.FreeSSERegs >= NumElts) { |
| State.FreeSSERegs -= NumElts; |
| |
| // Vectorcall passes HVAs directly and does not flatten them, but regcall |
| // does. |
| if (IsVectorCall) |
| return getDirectX86Hva(); |
| |
| if (Ty->isBuiltinType() || Ty->isVectorType()) |
| return ABIArgInfo::getDirect(); |
| return ABIArgInfo::getExpand(); |
| } |
| return getIndirectResult(Ty, /*ByVal=*/false, State); |
| } |
| |
| if (isAggregateTypeForABI(Ty)) { |
| // Structures with flexible arrays are always indirect. |
| // FIXME: This should not be byval! |
| if (RT && RT->getDecl()->hasFlexibleArrayMember()) |
| return getIndirectResult(Ty, true, State); |
| |
| // Ignore empty structs/unions on non-Windows. |
| if (!IsWin32StructABI && isEmptyRecord(getContext(), Ty, true)) |
| return ABIArgInfo::getIgnore(); |
| |
| llvm::LLVMContext &LLVMContext = getVMContext(); |
| llvm::IntegerType *Int32 = llvm::Type::getInt32Ty(LLVMContext); |
| bool NeedsPadding = false; |
| bool InReg; |
| if (shouldAggregateUseDirect(Ty, State, InReg, NeedsPadding)) { |
| unsigned SizeInRegs = (TI.Width + 31) / 32; |
| SmallVector<llvm::Type*, 3> Elements(SizeInRegs, Int32); |
| llvm::Type *Result = llvm::StructType::get(LLVMContext, Elements); |
| if (InReg) |
| return ABIArgInfo::getDirectInReg(Result); |
| else |
| return ABIArgInfo::getDirect(Result); |
| } |
| llvm::IntegerType *PaddingType = NeedsPadding ? Int32 : nullptr; |
| |
| // Pass over-aligned aggregates on Windows indirectly. This behavior was |
| // added in MSVC 2015. |
| if (IsWin32StructABI && TI.isAlignRequired() && TI.Align > 32) |
| return getIndirectResult(Ty, /*ByVal=*/false, State); |
| |
| // Expand small (<= 128-bit) record types when we know that the stack layout |
| // of those arguments will match the struct. This is important because the |
| // LLVM backend isn't smart enough to remove byval, which inhibits many |
| // optimizations. |
| // Don't do this for the MCU if there are still free integer registers |
| // (see X86_64 ABI for full explanation). |
| if (TI.Width <= 4 * 32 && (!IsMCUABI || State.FreeRegs == 0) && |
| canExpandIndirectArgument(Ty)) |
| return ABIArgInfo::getExpandWithPadding( |
| IsFastCall || IsVectorCall || IsRegCall, PaddingType); |
| |
| return getIndirectResult(Ty, true, State); |
| } |
| |
| if (const VectorType *VT = Ty->getAs<VectorType>()) { |
| // On Windows, vectors are passed directly if registers are available, or |
| // indirectly if not. This avoids the need to align argument memory. Pass |
| // user-defined vector types larger than 512 bits indirectly for simplicity. |
| if (IsWin32StructABI) { |
| if (TI.Width <= 512 && State.FreeSSERegs > 0) { |
| --State.FreeSSERegs; |
| return ABIArgInfo::getDirectInReg(); |
| } |
| return getIndirectResult(Ty, /*ByVal=*/false, State); |
| } |
| |
| // On Darwin, some vectors are passed in memory, we handle this by passing |
| // it as an i8/i16/i32/i64. |
| if (IsDarwinVectorABI) { |
| if ((TI.Width == 8 || TI.Width == 16 || TI.Width == 32) || |
| (TI.Width == 64 && VT->getNumElements() == 1)) |
| return ABIArgInfo::getDirect( |
| llvm::IntegerType::get(getVMContext(), TI.Width)); |
| } |
| |
| if (IsX86_MMXType(CGT.ConvertType(Ty))) |
| return ABIArgInfo::getDirect(llvm::IntegerType::get(getVMContext(), 64)); |
| |
| return ABIArgInfo::getDirect(); |
| } |
| |
| |
| if (const EnumType *EnumTy = Ty->getAs<EnumType>()) |
| Ty = EnumTy->getDecl()->getIntegerType(); |
| |
| bool InReg = shouldPrimitiveUseInReg(Ty, State); |
| |
| if (isPromotableIntegerTypeForABI(Ty)) { |
| if (InReg) |
| return ABIArgInfo::getExtendInReg(Ty); |
| return ABIArgInfo::getExtend(Ty); |
| } |
| |
| if (const auto * EIT = Ty->getAs<ExtIntType>()) { |
| if (EIT->getNumBits() <= 64) { |
| if (InReg) |
| return ABIArgInfo::getDirectInReg(); |
| return ABIArgInfo::getDirect(); |
| } |
| return getIndirectResult(Ty, /*ByVal=*/false, State); |
| } |
| |
| if (InReg) |
| return ABIArgInfo::getDirectInReg(); |
| return ABIArgInfo::getDirect(); |
| } |
| |
| void X86_32ABIInfo::computeInfo(CGFunctionInfo &FI) const { |
| CCState State(FI); |
| if (IsMCUABI) |
| State.FreeRegs = 3; |
| else if (State.CC == llvm::CallingConv::X86_FastCall) { |
| State.FreeRegs = 2; |
| State.FreeSSERegs = 3; |
| } else if (State.CC == llvm::CallingConv::X86_VectorCall) { |
| State.FreeRegs = 2; |
| State.FreeSSERegs = 6; |
| } else if (FI.getHasRegParm()) |
| State.FreeRegs = FI.getRegParm(); |
| else if (State.CC == llvm::CallingConv::X86_RegCall) { |
| State.FreeRegs = 5; |
| State.FreeSSERegs = 8; |
| } else if (IsWin32StructABI) { |
| // Since MSVC 2015, the first three SSE vectors have been passed in |
| // registers. The rest are passed indirectly. |
| State.FreeRegs = DefaultNumRegisterParameters; |
| State.FreeSSERegs = 3; |
| } else |
| State.FreeRegs = DefaultNumRegisterParameters; |
| |
| if (!::classifyReturnType(getCXXABI(), FI, *this)) { |
| FI.getReturnInfo() = classifyReturnType(FI.getReturnType(), State); |
| } else if (FI.getReturnInfo().isIndirect()) { |
| // The C++ ABI is not aware of register usage, so we have to check if the |
| // return value was sret and put it in a register ourselves if appropriate. |
| if (State.FreeRegs) { |
| --State.FreeRegs; // The sret parameter consumes a register. |
| if (!IsMCUABI) |
| FI.getReturnInfo().setInReg(true); |
| } |
| } |
| |
| // The chain argument effectively gives us another free register. |
| if (FI.isChainCall()) |
| ++State.FreeRegs; |
| |
| // For vectorcall, do a first pass over the arguments, assigning FP and vector |
| // arguments to XMM registers as available. |
| if (State.CC == llvm::CallingConv::X86_VectorCall) |
| runVectorCallFirstPass(FI, State); |
| |
| bool UsedInAlloca = false; |
| MutableArrayRef<CGFunctionInfoArgInfo> Args = FI.arguments(); |
| for (int I = 0, E = Args.size(); I < E; ++I) { |
| // Skip arguments that have already been assigned. |
| if (State.IsPreassigned.test(I)) |
| continue; |
| |
| Args[I].info = classifyArgumentType(Args[I].type, State); |
| UsedInAlloca |= (Args[I].info.getKind() == ABIArgInfo::InAlloca); |
| } |
| |
| // If we needed to use inalloca for any argument, do a second pass and rewrite |
| // all the memory arguments to use inalloca. |
| if (UsedInAlloca) |
| rewriteWithInAlloca(FI); |
| } |
| |
| void |
| X86_32ABIInfo::addFieldToArgStruct(SmallVector<llvm::Type *, 6> &FrameFields, |
| CharUnits &StackOffset, ABIArgInfo &Info, |
| QualType Type) const { |
| // Arguments are always 4-byte-aligned. |
| CharUnits WordSize = CharUnits::fromQuantity(4); |
| assert(StackOffset.isMultipleOf(WordSize) && "unaligned inalloca struct"); |
| |
| // sret pointers and indirect things will require an extra pointer |
| // indirection, unless they are byval. Most things are byval, and will not |
| // require this indirection. |
| bool IsIndirect = false; |
| if (Info.isIndirect() && !Info.getIndirectByVal()) |
| IsIndirect = true; |
| Info = ABIArgInfo::getInAlloca(FrameFields.size(), IsIndirect); |
| llvm::Type *LLTy = CGT.ConvertTypeForMem(Type); |
| if (IsIndirect) |
| LLTy = LLTy->getPointerTo(0); |
| FrameFields.push_back(LLTy); |
| StackOffset += IsIndirect ? WordSize : getContext().getTypeSizeInChars(Type); |
| |
| // Insert padding bytes to respect alignment. |
| CharUnits FieldEnd = StackOffset; |
| StackOffset = FieldEnd.alignTo(WordSize); |
| if (StackOffset != FieldEnd) { |
| CharUnits NumBytes = StackOffset - FieldEnd; |
| llvm::Type *Ty = llvm::Type::getInt8Ty(getVMContext()); |
| Ty = llvm::ArrayType::get(Ty, NumBytes.getQuantity()); |
| FrameFields.push_back(Ty); |
| } |
| } |
| |
| static bool isArgInAlloca(const ABIArgInfo &Info) { |
| // Leave ignored and inreg arguments alone. |
| switch (Info.getKind()) { |
| case ABIArgInfo::InAlloca: |
| return true; |
| case ABIArgInfo::Ignore: |
| case ABIArgInfo::IndirectAliased: |
| return false; |
| case ABIArgInfo::Indirect: |
| case ABIArgInfo::Direct: |
| case ABIArgInfo::Extend: |
| return !Info.getInReg(); |
| case ABIArgInfo::Expand: |
| case ABIArgInfo::CoerceAndExpand: |
| // These are aggregate types which are never passed in registers when |
| // inalloca is involved. |
| return true; |
| } |
| llvm_unreachable("invalid enum"); |
| } |
| |
| void X86_32ABIInfo::rewriteWithInAlloca(CGFunctionInfo &FI) const { |
| assert(IsWin32StructABI && "inalloca only supported on win32"); |
| |
| // Build a packed struct type for all of the arguments in memory. |
| SmallVector<llvm::Type *, 6> FrameFields; |
| |
| // The stack alignment is always 4. |
| CharUnits StackAlign = CharUnits::fromQuantity(4); |
| |
| CharUnits StackOffset; |
| CGFunctionInfo::arg_iterator I = FI.arg_begin(), E = FI.arg_end(); |
| |
| // Put 'this' into the struct before 'sret', if necessary. |
| bool IsThisCall = |
| FI.getCallingConvention() == llvm::CallingConv::X86_ThisCall; |
| ABIArgInfo &Ret = FI.getReturnInfo(); |
| if (Ret.isIndirect() && Ret.isSRetAfterThis() && !IsThisCall && |
| isArgInAlloca(I->info)) { |
| addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type); |
| ++I; |
| } |
| |
| // Put the sret parameter into the inalloca struct if it's in memory. |
| if (Ret.isIndirect() && !Ret.getInReg()) { |
| addFieldToArgStruct(FrameFields, StackOffset, Ret, FI.getReturnType()); |
| // On Windows, the hidden sret parameter is always returned in eax. |
| Ret.setInAllocaSRet(IsWin32StructABI); |
| } |
| |
| // Skip the 'this' parameter in ecx. |
| if (IsThisCall) |
| ++I; |
| |
| // Put arguments passed in memory into the struct. |
| for (; I != E; ++I) { |
| if (isArgInAlloca(I->info)) |
| addFieldToArgStruct(FrameFields, StackOffset, I->info, I->type); |
| } |
| |
| FI.setArgStruct(llvm::StructType::get(getVMContext(), FrameFields, |
| /*isPacked=*/true), |
| StackAlign); |
| } |
| |
| Address X86_32ABIInfo::EmitVAArg(CodeGenFunction &CGF, |
| Address VAListAddr, QualType Ty) const { |
| |
| auto TypeInfo = getContext().getTypeInfoInChars(Ty); |
| |
| // x86-32 changes the alignment of certain arguments on the stack. |
| // |
| // Just messing with TypeInfo like this works because we never pass |
| // anything indirectly. |
| TypeInfo.Align = CharUnits::fromQuantity( |
| getTypeStackAlignInBytes(Ty, TypeInfo.Align.getQuantity())); |
| |
| return emitVoidPtrVAArg(CGF, VAListAddr, Ty, /*Indirect*/ false, |
| TypeInfo, CharUnits::fromQuantity(4), |
| /*AllowHigherAlign*/ true); |
| } |
| |
| bool X86_32TargetCodeGenInfo::isStructReturnInRegABI( |
| const llvm::Triple &Triple, const CodeGenOptions &Opts) { |
| assert(Triple.getArch() == llvm::Triple::x86); |
| |
| switch (Opts.getStructReturnConvention()) { |
| case CodeGenOptions::SRCK_Default: |
| break; |
| case CodeGenOptions::SRCK_OnStack: // -fpcc-struct-return |
| return false; |
| case CodeGenOptions::SRCK_InRegs: // -freg-struct-return |
| return true; |
| } |
| |
| if (Triple.isOSDarwin() || Triple.isOSIAMCU()) |
| return true; |
| |
| switch (Triple.getOS()) { |
| case llvm::Triple::DragonFly: |
| case llvm::Triple::FreeBSD: |
| case llvm::Triple::OpenBSD: |
| case llvm::Triple::Win32: |
| return true; |
| default: |
| return false; |
| } |
| } |
| |
| static void addX86InterruptAttrs(const FunctionDecl *FD, llvm::GlobalValue *GV, |
| CodeGen::CodeGenModule &CGM) { |
| if (!FD->hasAttr<AnyX86InterruptAttr>()) |
| return; |
| |
| llvm::Function *Fn = cast<llvm::Function>(GV); |
| Fn->setCallingConv(llvm::CallingConv::X86_INTR); |
| if (FD->getNumParams() == 0) |
| return; |
| |
| auto PtrTy = cast<PointerType>(FD->getParamDecl(0)->getType()); |
| llvm::Type *ByValTy = CGM.getTypes().ConvertType(PtrTy->getPointeeType()); |
| llvm::Attribute NewAttr = llvm::Attribute::getWithByValType( |
| Fn->getContext(), ByValTy); |
| Fn->addParamAttr(0, NewAttr); |
| } |
| |
| void X86_32TargetCodeGenInfo::setTargetAttributes( |
| const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const { |
| if (GV->isDeclaration()) |
| return; |
| if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) { |
| if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) { |
| llvm::Function *Fn = cast<llvm::Function>(GV); |
| Fn->addFnAttr("stackrealign"); |
| } |
| |
| addX86InterruptAttrs(FD, GV, CGM); |
| } |
| } |
| |
| bool X86_32TargetCodeGenInfo::initDwarfEHRegSizeTable( |
| CodeGen::CodeGenFunction &CGF, |
| llvm::Value *Address) const { |
| CodeGen::CGBuilderTy &Builder = CGF.Builder; |
| |
| llvm::Value *Four8 = llvm::ConstantInt::get(CGF.Int8Ty, 4); |
| |
| // 0-7 are the eight integer registers; the order is different |
| // on Darwin (for EH), but the range is the same. |
| // 8 is %eip. |
| AssignToArrayRange(Builder, Address, Four8, 0, 8); |
| |
| if (CGF.CGM.getTarget().getTriple().isOSDarwin()) { |
| // 12-16 are st(0..4). Not sure why we stop at 4. |
| // These have size 16, which is sizeof(long double) on |
| // platforms with 8-byte alignment for that type. |
| llvm::Value *Sixteen8 = llvm::ConstantInt::get(CGF.Int8Ty, 16); |
| AssignToArrayRange(Builder, Address, Sixteen8, 12, 16); |
| |
| } else { |
| // 9 is %eflags, which doesn't get a size on Darwin for some |
| // reason. |
| Builder.CreateAlignedStore( |
| Four8, Builder.CreateConstInBoundsGEP1_32(CGF.Int8Ty, Address, 9), |
| CharUnits::One()); |
| |
| // 11-16 are st(0..5). Not sure why we stop at 5. |
| // These have size 12, which is sizeof(long double) on |
| // platforms with 4-byte alignment for that type. |
| llvm::Value *Twelve8 = llvm::ConstantInt::get(CGF.Int8Ty, 12); |
| AssignToArrayRange(Builder, Address, Twelve8, 11, 16); |
| } |
| |
| return false; |
| } |
| |
| //===----------------------------------------------------------------------===// |
| // X86-64 ABI Implementation |
| //===----------------------------------------------------------------------===// |
| |
| |
| namespace { |
| /// The AVX ABI level for X86 targets. |
| enum class X86AVXABILevel { |
| None, |
| AVX, |
| AVX512 |
| }; |
| |
| /// \p returns the size in bits of the largest (native) vector for \p AVXLevel. |
| static unsigned getNativeVectorSizeForAVXABI(X86AVXABILevel AVXLevel) { |
| switch (AVXLevel) { |
| case X86AVXABILevel::AVX512: |
| return 512; |
| case X86AVXABILevel::AVX: |
| return 256; |
| case X86AVXABILevel::None: |
| return 128; |
| } |
| llvm_unreachable("Unknown AVXLevel"); |
| } |
| |
| /// X86_64ABIInfo - The X86_64 ABI information. |
| class X86_64ABIInfo : public SwiftABIInfo { |
| enum Class { |
| Integer = 0, |
| SSE, |
| SSEUp, |
| X87, |
| X87Up, |
| ComplexX87, |
| NoClass, |
| Memory |
| }; |
| |
| /// merge - Implement the X86_64 ABI merging algorithm. |
| /// |
| /// Merge an accumulating classification \arg Accum with a field |
| /// classification \arg Field. |
| /// |
| /// \param Accum - The accumulating classification. This should |
| /// always be either NoClass or the result of a previous merge |
| /// call. In addition, this should never be Memory (the caller |
| /// should just return Memory for the aggregate). |
| static Class merge(Class Accum, Class Field); |
| |
| /// postMerge - Implement the X86_64 ABI post merging algorithm. |
| /// |
| /// Post merger cleanup, reduces a malformed Hi and Lo pair to |
| /// final MEMORY or SSE classes when necessary. |
| /// |
| /// \param AggregateSize - The size of the current aggregate in |
| /// the classification process. |
| /// |
| /// \param Lo - The classification for the parts of the type |
| /// residing in the low word of the containing object. |
| /// |
| /// \param Hi - The classification for the parts of the type |
| /// residing in the higher words of the containing object. |
| /// |
| void postMerge(unsigned AggregateSize, Class &Lo, Class &Hi) const; |
| |
| /// classify - Determine the x86_64 register classes in which the |
| /// given type T should be passed. |
| /// |
| /// \param Lo - The classification for the parts of the type |
| /// residing in the low word of the containing object. |
| /// |
| /// \param Hi - The classification for the parts of the type |
| /// residing in the high word of the containing object. |
| /// |
| /// \param OffsetBase - The bit offset of this type in the |
| /// containing object. Some parameters are classified different |
| /// depending on whether they straddle an eightbyte boundary. |
| /// |
| /// \param isNamedArg - Whether the argument in question is a "named" |
| /// argument, as used in AMD64-ABI 3.5.7. |
| /// |
| /// If a word is unused its result will be NoClass; if a type should |
| /// be passed in Memory then at least the classification of \arg Lo |
| /// will be Memory. |
| /// |
| /// The \arg Lo class will be NoClass iff the argument is ignored. |
| /// |
| /// If the \arg Lo class is ComplexX87, then the \arg Hi class will |
| /// also be ComplexX87. |
| void classify(QualType T, uint64_t OffsetBase, Class &Lo, Class &Hi, |
| bool isNamedArg) const; |
| |
| llvm::Type *GetByteVectorType(QualType Ty) const; |
| llvm::Type *GetSSETypeAtOffset(llvm::Type *IRType, |
| unsigned IROffset, QualType SourceTy, |
| unsigned SourceOffset) const; |
| llvm::Type *GetINTEGERTypeAtOffset(llvm::Type *IRType, |
| unsigned IROffset, QualType SourceTy, |
| unsigned SourceOffset) const; |
| |
| /// getIndirectResult - Give a source type \arg Ty, return a suitable result |
| /// such that the argument will be returned in memory. |
| ABIArgInfo getIndirectReturnResult(QualType Ty) const; |
| |
| /// getIndirectResult - Give a source type \arg Ty, return a suitable result |
| /// such that the argument will be passed in memory. |
| /// |
| /// \param freeIntRegs - The number of free integer registers remaining |
| /// available. |
| ABIArgInfo getIndirectResult(QualType Ty, unsigned freeIntRegs) const; |
| |
| ABIArgInfo classifyReturnType(QualType RetTy) const; |
| |
| ABIArgInfo classifyArgumentType(QualType Ty, unsigned freeIntRegs, |
| unsigned &neededInt, unsigned &neededSSE, |
| bool isNamedArg) const; |
| |
| ABIArgInfo classifyRegCallStructType(QualType Ty, unsigned &NeededInt, |
| unsigned &NeededSSE) const; |
| |
| ABIArgInfo classifyRegCallStructTypeImpl(QualType Ty, unsigned &NeededInt, |
| unsigned &NeededSSE) const; |
| |
| bool IsIllegalVectorType(QualType Ty) const; |
| |
| /// The 0.98 ABI revision clarified a lot of ambiguities, |
| /// unfortunately in ways that were not always consistent with |
| /// certain previous compilers. In particular, platforms which |
| /// required strict binary compatibility with older versions of GCC |
| /// may need to exempt themselves. |
| bool honorsRevision0_98() const { |
| return !getTarget().getTriple().isOSDarwin(); |
| } |
| |
| /// GCC classifies <1 x long long> as SSE but some platform ABIs choose to |
| /// classify it as INTEGER (for compatibility with older clang compilers). |
| bool classifyIntegerMMXAsSSE() const { |
| // Clang <= 3.8 did not do this. |
| if (getContext().getLangOpts().getClangABICompat() <= |
| LangOptions::ClangABI::Ver3_8) |
| return false; |
| |
| const llvm::Triple &Triple = getTarget().getTriple(); |
| if (Triple.isOSDarwin() || Triple.getOS() == llvm::Triple::PS4) |
| return false; |
| if (Triple.isOSFreeBSD() && Triple.getOSMajorVersion() >= 10) |
| return false; |
| return true; |
| } |
| |
| // GCC classifies vectors of __int128 as memory. |
| bool passInt128VectorsInMem() const { |
| // Clang <= 9.0 did not do this. |
| if (getContext().getLangOpts().getClangABICompat() <= |
| LangOptions::ClangABI::Ver9) |
| return false; |
| |
| const llvm::Triple &T = getTarget().getTriple(); |
| return T.isOSLinux() || T.isOSNetBSD(); |
| } |
| |
| X86AVXABILevel AVXLevel; |
| // Some ABIs (e.g. X32 ABI and Native Client OS) use 32 bit pointers on |
| // 64-bit hardware. |
| bool Has64BitPointers; |
| |
| public: |
| X86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) : |
| SwiftABIInfo(CGT), AVXLevel(AVXLevel), |
| Has64BitPointers(CGT.getDataLayout().getPointerSize(0) == 8) { |
| } |
| |
| bool isPassedUsingAVXType(QualType type) const { |
| unsigned neededInt, neededSSE; |
| // The freeIntRegs argument doesn't matter here. |
| ABIArgInfo info = classifyArgumentType(type, 0, neededInt, neededSSE, |
| /*isNamedArg*/true); |
| if (info.isDirect()) { |
| llvm::Type *ty = info.getCoerceToType(); |
| if (llvm::VectorType *vectorTy = dyn_cast_or_null<llvm::VectorType>(ty)) |
| return vectorTy->getPrimitiveSizeInBits().getFixedSize() > 128; |
| } |
| return false; |
| } |
| |
| void computeInfo(CGFunctionInfo &FI) const override; |
| |
| Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, |
| QualType Ty) const override; |
| Address EmitMSVAArg(CodeGenFunction &CGF, Address VAListAddr, |
| QualType Ty) const override; |
| |
| bool has64BitPointers() const { |
| return Has64BitPointers; |
| } |
| |
| bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type*> scalars, |
| bool asReturnValue) const override { |
| return occupiesMoreThan(CGT, scalars, /*total*/ 4); |
| } |
| bool isSwiftErrorInRegister() const override { |
| return true; |
| } |
| }; |
| |
| /// WinX86_64ABIInfo - The Windows X86_64 ABI information. |
| class WinX86_64ABIInfo : public SwiftABIInfo { |
| public: |
| WinX86_64ABIInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) |
| : SwiftABIInfo(CGT), AVXLevel(AVXLevel), |
| IsMingw64(getTarget().getTriple().isWindowsGNUEnvironment()) {} |
| |
| void computeInfo(CGFunctionInfo &FI) const override; |
| |
| Address EmitVAArg(CodeGenFunction &CGF, Address VAListAddr, |
| QualType Ty) const override; |
| |
| bool isHomogeneousAggregateBaseType(QualType Ty) const override { |
| // FIXME: Assumes vectorcall is in use. |
| return isX86VectorTypeForVectorCall(getContext(), Ty); |
| } |
| |
| bool isHomogeneousAggregateSmallEnough(const Type *Ty, |
| uint64_t NumMembers) const override { |
| // FIXME: Assumes vectorcall is in use. |
| return isX86VectorCallAggregateSmallEnough(NumMembers); |
| } |
| |
| bool shouldPassIndirectlyForSwift(ArrayRef<llvm::Type *> scalars, |
| bool asReturnValue) const override { |
| return occupiesMoreThan(CGT, scalars, /*total*/ 4); |
| } |
| |
| bool isSwiftErrorInRegister() const override { |
| return true; |
| } |
| |
| private: |
| ABIArgInfo classify(QualType Ty, unsigned &FreeSSERegs, bool IsReturnType, |
| bool IsVectorCall, bool IsRegCall) const; |
| ABIArgInfo reclassifyHvaArgForVectorCall(QualType Ty, unsigned &FreeSSERegs, |
| const ABIArgInfo ¤t) const; |
| |
| X86AVXABILevel AVXLevel; |
| |
| bool IsMingw64; |
| }; |
| |
| class X86_64TargetCodeGenInfo : public TargetCodeGenInfo { |
| public: |
| X86_64TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, X86AVXABILevel AVXLevel) |
| : TargetCodeGenInfo(std::make_unique<X86_64ABIInfo>(CGT, AVXLevel)) {} |
| |
| const X86_64ABIInfo &getABIInfo() const { |
| return static_cast<const X86_64ABIInfo&>(TargetCodeGenInfo::getABIInfo()); |
| } |
| |
| /// Disable tail call on x86-64. The epilogue code before the tail jump blocks |
| /// autoreleaseRV/retainRV and autoreleaseRV/unsafeClaimRV optimizations. |
| bool markARCOptimizedReturnCallsAsNoTail() const override { return true; } |
| |
| int getDwarfEHStackPointer(CodeGen::CodeGenModule &CGM) const override { |
| return 7; |
| } |
| |
| bool initDwarfEHRegSizeTable(CodeGen::CodeGenFunction &CGF, |
| llvm::Value *Address) const override { |
| llvm::Value *Eight8 = llvm::ConstantInt::get(CGF.Int8Ty, 8); |
| |
| // 0-15 are the 16 integer registers. |
| // 16 is %rip. |
| AssignToArrayRange(CGF.Builder, Address, Eight8, 0, 16); |
| return false; |
| } |
| |
| llvm::Type* adjustInlineAsmType(CodeGen::CodeGenFunction &CGF, |
| StringRef Constraint, |
| llvm::Type* Ty) const override { |
| return X86AdjustInlineAsmType(CGF, Constraint, Ty); |
| } |
| |
| bool isNoProtoCallVariadic(const CallArgList &args, |
| const FunctionNoProtoType *fnType) const override { |
| // The default CC on x86-64 sets %al to the number of SSA |
| // registers used, and GCC sets this when calling an unprototyped |
| // function, so we override the default behavior. However, don't do |
| // that when AVX types are involved: the ABI explicitly states it is |
| // undefined, and it doesn't work in practice because of how the ABI |
| // defines varargs anyway. |
| if (fnType->getCallConv() == CC_C) { |
| bool HasAVXType = false; |
| for (CallArgList::const_iterator |
| it = args.begin(), ie = args.end(); it != ie; ++it) { |
| if (getABIInfo().isPassedUsingAVXType(it->Ty)) { |
| HasAVXType = true; |
| break; |
| } |
| } |
| |
| if (!HasAVXType) |
| return true; |
| } |
| |
| return TargetCodeGenInfo::isNoProtoCallVariadic(args, fnType); |
| } |
| |
| llvm::Constant * |
| getUBSanFunctionSignature(CodeGen::CodeGenModule &CGM) const override { |
| unsigned Sig = (0xeb << 0) | // jmp rel8 |
| (0x06 << 8) | // .+0x08 |
| ('v' << 16) | |
| ('2' << 24); |
| return llvm::ConstantInt::get(CGM.Int32Ty, Sig); |
| } |
| |
| void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, |
| CodeGen::CodeGenModule &CGM) const override { |
| if (GV->isDeclaration()) |
| return; |
| if (const FunctionDecl *FD = dyn_cast_or_null<FunctionDecl>(D)) { |
| if (FD->hasAttr<X86ForceAlignArgPointerAttr>()) { |
| llvm::Function *Fn = cast<llvm::Function>(GV); |
| Fn->addFnAttr("stackrealign"); |
| } |
| |
| addX86InterruptAttrs(FD, GV, CGM); |
| } |
| } |
| |
| void checkFunctionCallABI(CodeGenModule &CGM, SourceLocation CallLoc, |
| const FunctionDecl *Caller, |
| const FunctionDecl *Callee, |
| const CallArgList &Args) const override; |
| }; |
| |
| static void initFeatureMaps(const ASTContext &Ctx, |
| llvm::StringMap<bool> &CallerMap, |
| const FunctionDecl *Caller, |
| llvm::StringMap<bool> &CalleeMap, |
| const FunctionDecl *Callee) { |
| if (CalleeMap.empty() && CallerMap.empty()) { |
| // The caller is potentially nullptr in the case where the call isn't in a |
| // function. In this case, the getFunctionFeatureMap ensures we just get |
| // the TU level setting (since it cannot be modified by 'target'.. |
| Ctx.getFunctionFeatureMap(CallerMap, Caller); |
| Ctx.getFunctionFeatureMap(CalleeMap, Callee); |
| } |
| } |
| |
| static bool checkAVXParamFeature(DiagnosticsEngine &Diag, |
| SourceLocation CallLoc, |
| const llvm::StringMap<bool> &CallerMap, |
| const llvm::StringMap<bool> &CalleeMap, |
| QualType Ty, StringRef Feature, |
| bool IsArgument) { |
| bool CallerHasFeat = CallerMap.lookup(Feature); |
| bool CalleeHasFeat = CalleeMap.lookup(Feature); |
| if (!CallerHasFeat && !CalleeHasFeat) |
| return Diag.Report(CallLoc, diag::warn_avx_calling_convention) |
| << IsArgument << Ty << Feature; |
| |
| // Mixing calling conventions here is very clearly an error. |
| if (!CallerHasFeat || !CalleeHasFeat) |
| return Diag.Report(CallLoc, diag::err_avx_calling_convention) |
| << IsArgument << Ty << Feature; |
| |
| // Else, both caller and callee have the required feature, so there is no need |
| // to diagnose. |
| return false; |
| } |
| |
| static bool checkAVXParam(DiagnosticsEngine &Diag, ASTContext &Ctx, |
| SourceLocation CallLoc, |
| const llvm::StringMap<bool> &CallerMap, |
| const llvm::StringMap<bool> &CalleeMap, QualType Ty, |
| bool IsArgument) { |
| uint64_t Size = Ctx.getTypeSize(Ty); |
| if (Size > 256) |
| return checkAVXParamFeature(Diag, CallLoc, CallerMap, CalleeMap, Ty, |
| "avx512f", IsArgument); |
| |
| if (Size > 128) |
| return checkAVXParamFeature(Diag, CallLoc, CallerMap, CalleeMap, Ty, "avx", |
| IsArgument); |
| |
| return false; |
| } |
| |
| void X86_64TargetCodeGenInfo::checkFunctionCallABI( |
| CodeGenModule &CGM, SourceLocation CallLoc, const FunctionDecl *Caller, |
| const FunctionDecl *Callee, const CallArgList &Args) const { |
| llvm::StringMap<bool> CallerMap; |
| llvm::StringMap<bool> CalleeMap; |
| unsigned ArgIndex = 0; |
| |
| // We need to loop through the actual call arguments rather than the the |
| // function's parameters, in case this variadic. |
| for (const CallArg &Arg : Args) { |
| // The "avx" feature changes how vectors >128 in size are passed. "avx512f" |
| // additionally changes how vectors >256 in size are passed. Like GCC, we |
| // warn when a function is called with an argument where this will change. |
| // Unlike GCC, we also error when it is an obvious ABI mismatch, that is, |
| // the caller and callee features are mismatched. |
| // Unfortunately, we cannot do this diagnostic in SEMA, since the callee can |
| // change its ABI with attribute-target after this call. |
| if (Arg.getType()->isVectorType() && |
| CGM.getContext().getTypeSize(Arg.getType()) > 128) { |
| initFeatureMaps(CGM.getContext(), CallerMap, Caller, CalleeMap, Callee); |
| QualType Ty = Arg.getType(); |
| // The CallArg seems to have desugared the type already, so for clearer |
| // diagnostics, replace it with the type in the FunctionDecl if possible. |
| if (ArgIndex < Callee->getNumParams()) |
| Ty = Callee->getParamDecl(ArgIndex)->getType(); |
| |
| if (checkAVXParam(CGM.getDiags(), CGM.getContext(), CallLoc, CallerMap, |
| CalleeMap, Ty, /*IsArgument*/ true)) |
| return; |
| } |
| ++ArgIndex; |
| } |
| |
| // Check return always, as we don't have a good way of knowing in codegen |
| // whether this value is used, tail-called, etc. |
| if (Callee->getReturnType()->isVectorType() && |
| CGM.getContext().getTypeSize(Callee->getReturnType()) > 128) { |
| initFeatureMaps(CGM.getContext(), CallerMap, Caller, CalleeMap, Callee); |
| checkAVXParam(CGM.getDiags(), CGM.getContext(), CallLoc, CallerMap, |
| CalleeMap, Callee->getReturnType(), |
| /*IsArgument*/ false); |
| } |
| } |
| |
| static std::string qualifyWindowsLibrary(llvm::StringRef Lib) { |
| // If the argument does not end in .lib, automatically add the suffix. |
| // If the argument contains a space, enclose it in quotes. |
| // This matches the behavior of MSVC. |
| bool Quote = Lib.contains(' '); |
| std::string ArgStr = Quote ? "\"" : ""; |
| ArgStr += Lib; |
| if (!Lib.endswith_insensitive(".lib") && !Lib.endswith_insensitive(".a")) |
| ArgStr += ".lib"; |
| ArgStr += Quote ? "\"" : ""; |
| return ArgStr; |
| } |
| |
| class WinX86_32TargetCodeGenInfo : public X86_32TargetCodeGenInfo { |
| public: |
| WinX86_32TargetCodeGenInfo(CodeGen::CodeGenTypes &CGT, |
| bool DarwinVectorABI, bool RetSmallStructInRegABI, bool Win32StructABI, |
| unsigned NumRegisterParameters) |
| : X86_32TargetCodeGenInfo(CGT, DarwinVectorABI, RetSmallStructInRegABI, |
| Win32StructABI, NumRegisterParameters, false) {} |
| |
| void setTargetAttributes(const Decl *D, llvm::GlobalValue *GV, |
| CodeGen::CodeGenModule &CGM) const override; |
| |
| void getDependentLibraryOption(llvm::StringRef Lib, |
| llvm::SmallString<24> &Opt) const override { |
| Opt = "/DEFAULTLIB:"; |
| Opt += qualifyWindowsLibrary(Lib); |
| } |
| |
| void getDetectMismatchOption(llvm::StringRef Name, |
| llvm::StringRef Value, |
| llvm::SmallString<32> &Opt) const override { |
| Opt = "/FAILIFMISMATCH:\"" + Name.str() + "=" + Value.str() + "\""; |
| } |
| }; |
| |
| static void addStackProbeTargetAttributes(const Decl *D, llvm::GlobalValue *GV, |
| CodeGen::CodeGenModule &CGM) { |
| if (llvm::Function *Fn = dyn_cast_or_null<llvm::Function>(GV)) { |
| |
| if (CGM.getCodeGenOpts().StackProbeSize != 4096) |
| Fn->addFnAttr("stack-probe-size", |
| llvm::utostr(CGM.getCodeGenOpts().StackProbeSize)); |
| if (CGM.getCodeGenOpts().NoStackArgProbe) |
| Fn->addFnAttr("no-stack-arg-probe"); |
| } |
| } |
| |
| void WinX86_32TargetCodeGenInfo::setTargetAttributes( |
| const Decl *D, llvm::GlobalValue *GV, CodeGen::CodeGenModule &CGM) const { |
| X86_32TargetCodeGenInfo::setTargetAttributes(D, GV, CGM); |
|