commit 3f0c9c1634237834af6b74e9319cb15f6ab89d11
author Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> Tue Jun 16 10:21:09 2020 -0700
committer Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> Tue Jun 16 11:15:09 2020 -0700
tree c65ed284e576f4b148712a9bd31feb3aaf367e4a
parent 6bc2b042f4a9e8d912901679bd4614d46f6fafed

Fix ubsan error in tblgen with signed left shift

UBSAN complains when tblgen performs SHL of a negative
value.

Differential Revision: https://reviews.llvm.org/D81952

llvm/lib/TableGen/Record.cpp

diff --git a/llvm/lib/TableGen/Record.cpp b/llvm/lib/TableGen/Record.cpp
index 50df5da..d3db004 100644
--- a/llvm/lib/TableGen/Record.cpp
+++ b/llvm/lib/TableGen/Record.cpp
@@ -1030,7 +1030,7 @@
       case MUL: Result = LHSv *  RHSv; break;
       case AND: Result = LHSv &  RHSv; break;
       case OR: Result = LHSv | RHSv; break;
-      case SHL: Result = LHSv << RHSv; break;
+      case SHL: Result = (uint64_t)LHSv << (uint64_t)RHSv; break;
       case SRA: Result = LHSv >> RHSv; break;
       case SRL: Result = (uint64_t)LHSv >> (uint64_t)RHSv; break;
       }

llvm/lib/Target/AMDGPU/SMInstructions.td

diff --git a/llvm/lib/Target/AMDGPU/SMInstructions.td b/llvm/lib/Target/AMDGPU/SMInstructions.td
index df21c86..252f191 100644
--- a/llvm/lib/Target/AMDGPU/SMInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SMInstructions.td
@@ -860,7 +860,7 @@
 def : GCNPat <
   (i64 (readcyclecounter)),
   (REG_SEQUENCE SReg_64,
-    (S_GETREG_B32 -26595), sub0,
+    (S_GETREG_B32 getHwRegImm<HWREG.SHADER_CYCLES, 0, -12>.ret), sub0,
     (S_MOV_B32 (i32 0)), sub1)
 >;
 } // let OtherPredicates = [HasNoSMemTimeInst]