| InstructionEmulationState={ |
| assembly_string="ldr.w r10,[ pc, #4]" |
| triple=thumb-apple-darwin |
| opcode=0xf8dfa004 |
| before_state={ |
| memory={ |
| address=0x3000 |
| data_encoding=uint32_t |
| data=[ |
| 0x2fe01000 |
| ] |
| } |
| registers={ |
| r0=0x2fdffe48 |
| r1=0x2fdffe58 |
| r2=0x2fdffe68 |
| r3=0x2fdffe78 |
| r4=0x2fdffe88 |
| r5=0x2fdffe98 |
| r6=0x2fdffea8 |
| r7=0x2fdffe48 |
| r8=0x2fdffec8 |
| r9=0x2fdffed8 |
| r10=0x2fdffee8 |
| r11=0x2fdffef8 |
| r12=0x2fdfff08 |
| r13=0x2fdffe48 |
| r14=0x00002f80 |
| r15=0x00002ff8 |
| cpsr=0x60000030 |
| s0=0x00000000 |
| s1=0x00000000 |
| s2=0x00000000 |
| s3=0x00000000 |
| s4=0x00000000 |
| s5=0x00000000 |
| s6=0x00000000 |
| s7=0x00000000 |
| s8=0x00000000 |
| s9=0x00000000 |
| s10=0x00000000 |
| s11=0x00000000 |
| s12=0x00000000 |
| s13=0x00000000 |
| s14=0x00000000 |
| s15=0x00000000 |
| s16=0x00000000 |
| s17=0x00000000 |
| s18=0x00000000 |
| s19=0x00000000 |
| s20=0x00000000 |
| s21=0x00000000 |
| s22=0x00000000 |
| s23=0x00000000 |
| s24=0x00000000 |
| s25=0x00000000 |
| s26=0x00000000 |
| s27=0x00000000 |
| s28=0x00000000 |
| s29=0x00000000 |
| s30=0x00000000 |
| s31=0x00000000 |
| } |
| } |
| after_state={ |
| registers={ |
| r0=0x2fdffe48 |
| r1=0x2fdffe58 |
| r2=0x2fdffe68 |
| r3=0x2fdffe78 |
| r4=0x2fdffe88 |
| r5=0x2fdffe98 |
| r6=0x2fdffea8 |
| r7=0x2fdffe48 |
| r8=0x2fdffec8 |
| r9=0x2fdffed8 |
| r10=0x2fe01000 |
| r11=0x2fdffef8 |
| r12=0x2fdfff08 |
| r13=0x2fdffe48 |
| r14=0x00002f80 |
| r15=0x00002ffc |
| cpsr=0x60000030 |
| s0=0x00000000 |
| s1=0x00000000 |
| s2=0x00000000 |
| s3=0x00000000 |
| s4=0x00000000 |
| s5=0x00000000 |
| s6=0x00000000 |
| s7=0x00000000 |
| s8=0x00000000 |
| s9=0x00000000 |
| s10=0x00000000 |
| s11=0x00000000 |
| s12=0x00000000 |
| s13=0x00000000 |
| s14=0x00000000 |
| s15=0x00000000 |
| s16=0x00000000 |
| s17=0x00000000 |
| s18=0x00000000 |
| s19=0x00000000 |
| s20=0x00000000 |
| s21=0x00000000 |
| s22=0x00000000 |
| s23=0x00000000 |
| s24=0x00000000 |
| s25=0x00000000 |
| s26=0x00000000 |
| s27=0x00000000 |
| s28=0x00000000 |
| s29=0x00000000 |
| s30=0x00000000 |
| s31=0x00000000 |
| } |
| } |
| } |
