| //===- MipsMSAInstrInfo.td - MSA ASE instructions -*- tablegen ------------*-=// |
| // |
| // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| // See https://llvm.org/LICENSE.txt for license information. |
| // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| // |
| //===----------------------------------------------------------------------===// |
| // |
| // This file describes Mips MSA ASE instructions. |
| // |
| //===----------------------------------------------------------------------===// |
| |
| def SDT_MipsVecCond : SDTypeProfile<1, 1, [SDTCisInt<0>, SDTCisVec<1>]>; |
| def SDT_VSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, |
| SDTCisInt<1>, |
| SDTCisSameAs<1, 2>, |
| SDTCisVT<3, OtherVT>]>; |
| def SDT_VFSetCC : SDTypeProfile<1, 3, [SDTCisInt<0>, |
| SDTCisFP<1>, |
| SDTCisSameAs<1, 2>, |
| SDTCisVT<3, OtherVT>]>; |
| def SDT_VSHF : SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisVec<0>, |
| SDTCisInt<1>, SDTCisVec<1>, |
| SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>]>; |
| def SDT_SHF : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, |
| SDTCisVT<1, i32>, SDTCisSameAs<0, 2>]>; |
| def SDT_ILV : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisVec<0>, |
| SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>]>; |
| def SDT_INSVE : SDTypeProfile<1, 4, [SDTCisVec<0>, SDTCisSameAs<0, 1>, |
| SDTCisVT<2, i32>, SDTCisSameAs<0, 3>, |
| SDTCisVT<4, i32>]>; |
| |
| def MipsVAllNonZero : SDNode<"MipsISD::VALL_NONZERO", SDT_MipsVecCond>; |
| def MipsVAnyNonZero : SDNode<"MipsISD::VANY_NONZERO", SDT_MipsVecCond>; |
| def MipsVAllZero : SDNode<"MipsISD::VALL_ZERO", SDT_MipsVecCond>; |
| def MipsVAnyZero : SDNode<"MipsISD::VANY_ZERO", SDT_MipsVecCond>; |
| def MipsVNOR : SDNode<"MipsISD::VNOR", SDTIntBinOp, |
| [SDNPCommutative, SDNPAssociative]>; |
| def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>; |
| def MipsSHF : SDNode<"MipsISD::SHF", SDT_SHF>; |
| def MipsILVEV : SDNode<"MipsISD::ILVEV", SDT_ILV>; |
| def MipsILVOD : SDNode<"MipsISD::ILVOD", SDT_ILV>; |
| def MipsILVL : SDNode<"MipsISD::ILVL", SDT_ILV>; |
| def MipsILVR : SDNode<"MipsISD::ILVR", SDT_ILV>; |
| def MipsPCKEV : SDNode<"MipsISD::PCKEV", SDT_ILV>; |
| def MipsPCKOD : SDNode<"MipsISD::PCKOD", SDT_ILV>; |
| def MipsINSVE : SDNode<"MipsISD::INSVE", SDT_INSVE>; |
| def MipsFMS : SDNode<"MipsISD::FMS", SDTFPTernaryOp>; |
| |
| def vsetcc : SDNode<"ISD::SETCC", SDT_VSetCC>; |
| def vfsetcc : SDNode<"ISD::SETCC", SDT_VFSetCC>; |
| |
| def MipsVExtractSExt : SDNode<"MipsISD::VEXTRACT_SEXT_ELT", |
| SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; |
| def MipsVExtractZExt : SDNode<"MipsISD::VEXTRACT_ZEXT_ELT", |
| SDTypeProfile<1, 3, [SDTCisPtrTy<2>]>, []>; |
| |
| def immZExt1Ptr : ImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>; |
| def immZExt2Ptr : ImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>; |
| def immZExt3Ptr : ImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>; |
| def immZExt4Ptr : ImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>; |
| |
| def timmZExt1Ptr : TImmLeaf<iPTR, [{return isUInt<1>(Imm);}]>; |
| def timmZExt2Ptr : TImmLeaf<iPTR, [{return isUInt<2>(Imm);}]>; |
| def timmZExt3Ptr : TImmLeaf<iPTR, [{return isUInt<3>(Imm);}]>; |
| def timmZExt4Ptr : TImmLeaf<iPTR, [{return isUInt<4>(Imm);}]>; |
| |
| // Operands |
| |
| def immZExt2Lsa : ImmLeaf<i32, [{return isUInt<2>(Imm - 1);}]>; |
| |
| // Pattern fragments |
| def vextract_sext_i8 : PatFrag<(ops node:$vec, node:$idx), |
| (MipsVExtractSExt node:$vec, node:$idx, i8)>; |
| def vextract_sext_i16 : PatFrag<(ops node:$vec, node:$idx), |
| (MipsVExtractSExt node:$vec, node:$idx, i16)>; |
| def vextract_sext_i32 : PatFrag<(ops node:$vec, node:$idx), |
| (MipsVExtractSExt node:$vec, node:$idx, i32)>; |
| def vextract_sext_i64 : PatFrag<(ops node:$vec, node:$idx), |
| (MipsVExtractSExt node:$vec, node:$idx, i64)>; |
| |
| def vextract_zext_i8 : PatFrag<(ops node:$vec, node:$idx), |
| (MipsVExtractZExt node:$vec, node:$idx, i8)>; |
| def vextract_zext_i16 : PatFrag<(ops node:$vec, node:$idx), |
| (MipsVExtractZExt node:$vec, node:$idx, i16)>; |
| def vextract_zext_i32 : PatFrag<(ops node:$vec, node:$idx), |
| (MipsVExtractZExt node:$vec, node:$idx, i32)>; |
| def vextract_zext_i64 : PatFrag<(ops node:$vec, node:$idx), |
| (MipsVExtractZExt node:$vec, node:$idx, i64)>; |
| |
| def vinsert_v16i8 : PatFrag<(ops node:$vec, node:$val, node:$idx), |
| (v16i8 (vector_insert node:$vec, node:$val, node:$idx))>; |
| def vinsert_v8i16 : PatFrag<(ops node:$vec, node:$val, node:$idx), |
| (v8i16 (vector_insert node:$vec, node:$val, node:$idx))>; |
| def vinsert_v4i32 : PatFrag<(ops node:$vec, node:$val, node:$idx), |
| (v4i32 (vector_insert node:$vec, node:$val, node:$idx))>; |
| def vinsert_v2i64 : PatFrag<(ops node:$vec, node:$val, node:$idx), |
| (v2i64 (vector_insert node:$vec, node:$val, node:$idx))>; |
| |
| def insve_v16i8 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), |
| (v16i8 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; |
| def insve_v8i16 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), |
| (v8i16 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; |
| def insve_v4i32 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), |
| (v4i32 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; |
| def insve_v2i64 : PatFrag<(ops node:$v1, node:$i1, node:$v2, node:$i2), |
| (v2i64 (MipsINSVE node:$v1, node:$i1, node:$v2, node:$i2))>; |
| |
| class vfsetcc_type<ValueType ResTy, ValueType OpTy, CondCode CC> : |
| PatFrag<(ops node:$lhs, node:$rhs), |
| (ResTy (vfsetcc (OpTy node:$lhs), (OpTy node:$rhs), CC))>; |
| |
| // ISD::SETFALSE cannot occur |
| def vfseteq_v4f32 : vfsetcc_type<v4i32, v4f32, SETEQ>; |
| def vfseteq_v2f64 : vfsetcc_type<v2i64, v2f64, SETEQ>; |
| def vfsetge_v4f32 : vfsetcc_type<v4i32, v4f32, SETGE>; |
| def vfsetge_v2f64 : vfsetcc_type<v2i64, v2f64, SETGE>; |
| def vfsetgt_v4f32 : vfsetcc_type<v4i32, v4f32, SETGT>; |
| def vfsetgt_v2f64 : vfsetcc_type<v2i64, v2f64, SETGT>; |
| def vfsetle_v4f32 : vfsetcc_type<v4i32, v4f32, SETLE>; |
| def vfsetle_v2f64 : vfsetcc_type<v2i64, v2f64, SETLE>; |
| def vfsetlt_v4f32 : vfsetcc_type<v4i32, v4f32, SETLT>; |
| def vfsetlt_v2f64 : vfsetcc_type<v2i64, v2f64, SETLT>; |
| def vfsetne_v4f32 : vfsetcc_type<v4i32, v4f32, SETNE>; |
| def vfsetne_v2f64 : vfsetcc_type<v2i64, v2f64, SETNE>; |
| def vfsetoeq_v4f32 : vfsetcc_type<v4i32, v4f32, SETOEQ>; |
| def vfsetoeq_v2f64 : vfsetcc_type<v2i64, v2f64, SETOEQ>; |
| def vfsetoge_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGE>; |
| def vfsetoge_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGE>; |
| def vfsetogt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOGT>; |
| def vfsetogt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOGT>; |
| def vfsetole_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLE>; |
| def vfsetole_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLE>; |
| def vfsetolt_v4f32 : vfsetcc_type<v4i32, v4f32, SETOLT>; |
| def vfsetolt_v2f64 : vfsetcc_type<v2i64, v2f64, SETOLT>; |
| def vfsetone_v4f32 : vfsetcc_type<v4i32, v4f32, SETONE>; |
| def vfsetone_v2f64 : vfsetcc_type<v2i64, v2f64, SETONE>; |
| def vfsetord_v4f32 : vfsetcc_type<v4i32, v4f32, SETO>; |
| def vfsetord_v2f64 : vfsetcc_type<v2i64, v2f64, SETO>; |
| def vfsetun_v4f32 : vfsetcc_type<v4i32, v4f32, SETUO>; |
| def vfsetun_v2f64 : vfsetcc_type<v2i64, v2f64, SETUO>; |
| def vfsetueq_v4f32 : vfsetcc_type<v4i32, v4f32, SETUEQ>; |
| def vfsetueq_v2f64 : vfsetcc_type<v2i64, v2f64, SETUEQ>; |
| def vfsetuge_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGE>; |
| def vfsetuge_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGE>; |
| def vfsetugt_v4f32 : vfsetcc_type<v4i32, v4f32, SETUGT>; |
| def vfsetugt_v2f64 : vfsetcc_type<v2i64, v2f64, SETUGT>; |
| def vfsetule_v4f32 : vfsetcc_type<v4i32, v4f32, SETULE>; |
| def vfsetule_v2f64 : vfsetcc_type<v2i64, v2f64, SETULE>; |
| def vfsetult_v4f32 : vfsetcc_type<v4i32, v4f32, SETULT>; |
| def vfsetult_v2f64 : vfsetcc_type<v2i64, v2f64, SETULT>; |
| def vfsetune_v4f32 : vfsetcc_type<v4i32, v4f32, SETUNE>; |
| def vfsetune_v2f64 : vfsetcc_type<v2i64, v2f64, SETUNE>; |
| // ISD::SETTRUE cannot occur |
| // ISD::SETFALSE2 cannot occur |
| // ISD::SETTRUE2 cannot occur |
| |
| class vsetcc_type<ValueType ResTy, CondCode CC> : |
| PatFrag<(ops node:$lhs, node:$rhs), |
| (ResTy (vsetcc node:$lhs, node:$rhs, CC))>; |
| |
| def vseteq_v16i8 : vsetcc_type<v16i8, SETEQ>; |
| def vseteq_v8i16 : vsetcc_type<v8i16, SETEQ>; |
| def vseteq_v4i32 : vsetcc_type<v4i32, SETEQ>; |
| def vseteq_v2i64 : vsetcc_type<v2i64, SETEQ>; |
| def vsetle_v16i8 : vsetcc_type<v16i8, SETLE>; |
| def vsetle_v8i16 : vsetcc_type<v8i16, SETLE>; |
| def vsetle_v4i32 : vsetcc_type<v4i32, SETLE>; |
| def vsetle_v2i64 : vsetcc_type<v2i64, SETLE>; |
| def vsetlt_v16i8 : vsetcc_type<v16i8, SETLT>; |
| def vsetlt_v8i16 : vsetcc_type<v8i16, SETLT>; |
| def vsetlt_v4i32 : vsetcc_type<v4i32, SETLT>; |
| def vsetlt_v2i64 : vsetcc_type<v2i64, SETLT>; |
| def vsetule_v16i8 : vsetcc_type<v16i8, SETULE>; |
| def vsetule_v8i16 : vsetcc_type<v8i16, SETULE>; |
| def vsetule_v4i32 : vsetcc_type<v4i32, SETULE>; |
| def vsetule_v2i64 : vsetcc_type<v2i64, SETULE>; |
| def vsetult_v16i8 : vsetcc_type<v16i8, SETULT>; |
| def vsetult_v8i16 : vsetcc_type<v8i16, SETULT>; |
| def vsetult_v4i32 : vsetcc_type<v4i32, SETULT>; |
| def vsetult_v2i64 : vsetcc_type<v2i64, SETULT>; |
| |
| def vsplati8 : PatFrag<(ops node:$e0), |
| (v16i8 (build_vector node:$e0, node:$e0, |
| node:$e0, node:$e0, |
| node:$e0, node:$e0, |
| node:$e0, node:$e0, |
| node:$e0, node:$e0, |
| node:$e0, node:$e0, |
| node:$e0, node:$e0, |
| node:$e0, node:$e0))>; |
| def vsplati16 : PatFrag<(ops node:$e0), |
| (v8i16 (build_vector node:$e0, node:$e0, |
| node:$e0, node:$e0, |
| node:$e0, node:$e0, |
| node:$e0, node:$e0))>; |
| def vsplati32 : PatFrag<(ops node:$e0), |
| (v4i32 (build_vector node:$e0, node:$e0, |
| node:$e0, node:$e0))>; |
| |
| def vsplati64_imm_eq_1 : PatLeaf<(bitconvert (v4i32 (build_vector))), [{ |
| APInt Imm; |
| SDNode *BV = N->getOperand(0).getNode(); |
| EVT EltTy = N->getValueType(0).getVectorElementType(); |
| |
| return selectVSplat(BV, Imm, EltTy.getSizeInBits()) && |
| Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; |
| }]>; |
| |
| def vsplati64 : PatFrag<(ops node:$e0), |
| (v2i64 (build_vector node:$e0, node:$e0))>; |
| |
| def vsplati64_splat_d : PatFrag<(ops node:$e0), |
| (v2i64 (bitconvert |
| (v4i32 (and |
| (v4i32 (build_vector node:$e0, |
| node:$e0, |
| node:$e0, |
| node:$e0)), |
| vsplati64_imm_eq_1))))>; |
| |
| def vsplatf32 : PatFrag<(ops node:$e0), |
| (v4f32 (build_vector node:$e0, node:$e0, |
| node:$e0, node:$e0))>; |
| def vsplatf64 : PatFrag<(ops node:$e0), |
| (v2f64 (build_vector node:$e0, node:$e0))>; |
| |
| def vsplati8_elt : PatFrag<(ops node:$v, node:$i), |
| (MipsVSHF (vsplati8 node:$i), node:$v, node:$v)>; |
| def vsplati16_elt : PatFrag<(ops node:$v, node:$i), |
| (MipsVSHF (vsplati16 node:$i), node:$v, node:$v)>; |
| def vsplati32_elt : PatFrag<(ops node:$v, node:$i), |
| (MipsVSHF (vsplati32 node:$i), node:$v, node:$v)>; |
| def vsplati64_elt : PatFrag<(ops node:$v, node:$i), |
| (MipsVSHF (vsplati64_splat_d node:$i), |
| node:$v, node:$v)>; |
| |
| class SplatPatLeaf<Operand opclass, dag frag, code pred = [{}], |
| SDNodeXForm xform = NOOP_SDNodeXForm> |
| : PatLeaf<frag, pred, xform> { |
| Operand OpClass = opclass; |
| } |
| |
| class SplatComplexPattern<Operand opclass, ValueType ty, int numops, string fn, |
| list<SDNode> roots = [], |
| list<SDNodeProperty> props = []> : |
| ComplexPattern<ty, numops, fn, roots, props> { |
| Operand OpClass = opclass; |
| } |
| |
| def vsplati8_uimm3 : SplatComplexPattern<vsplat_uimm3, v16i8, 1, |
| "selectVSplatUimm3", |
| [build_vector, bitconvert]>; |
| |
| def vsplati8_uimm4 : SplatComplexPattern<vsplat_uimm4, v16i8, 1, |
| "selectVSplatUimm4", |
| [build_vector, bitconvert]>; |
| |
| def vsplati8_uimm5 : SplatComplexPattern<vsplat_uimm5, v16i8, 1, |
| "selectVSplatUimm5", |
| [build_vector, bitconvert]>; |
| |
| def vsplati8_uimm8 : SplatComplexPattern<vsplat_uimm8, v16i8, 1, |
| "selectVSplatUimm8", |
| [build_vector, bitconvert]>; |
| |
| def vsplati8_simm5 : SplatComplexPattern<vsplat_simm5, v16i8, 1, |
| "selectVSplatSimm5", |
| [build_vector, bitconvert]>; |
| |
| def vsplati16_uimm3 : SplatComplexPattern<vsplat_uimm3, v8i16, 1, |
| "selectVSplatUimm3", |
| [build_vector, bitconvert]>; |
| |
| def vsplati16_uimm4 : SplatComplexPattern<vsplat_uimm4, v8i16, 1, |
| "selectVSplatUimm4", |
| [build_vector, bitconvert]>; |
| |
| def vsplati16_uimm5 : SplatComplexPattern<vsplat_uimm5, v8i16, 1, |
| "selectVSplatUimm5", |
| [build_vector, bitconvert]>; |
| |
| def vsplati16_simm5 : SplatComplexPattern<vsplat_simm5, v8i16, 1, |
| "selectVSplatSimm5", |
| [build_vector, bitconvert]>; |
| |
| def vsplati32_uimm2 : SplatComplexPattern<vsplat_uimm2, v4i32, 1, |
| "selectVSplatUimm2", |
| [build_vector, bitconvert]>; |
| |
| def vsplati32_uimm5 : SplatComplexPattern<vsplat_uimm5, v4i32, 1, |
| "selectVSplatUimm5", |
| [build_vector, bitconvert]>; |
| |
| def vsplati32_simm5 : SplatComplexPattern<vsplat_simm5, v4i32, 1, |
| "selectVSplatSimm5", |
| [build_vector, bitconvert]>; |
| |
| def vsplati64_uimm1 : SplatComplexPattern<vsplat_uimm1, v2i64, 1, |
| "selectVSplatUimm1", |
| [build_vector, bitconvert]>; |
| |
| def vsplati64_uimm5 : SplatComplexPattern<vsplat_uimm5, v2i64, 1, |
| "selectVSplatUimm5", |
| [build_vector, bitconvert]>; |
| |
| def vsplati64_uimm6 : SplatComplexPattern<vsplat_uimm6, v2i64, 1, |
| "selectVSplatUimm6", |
| [build_vector, bitconvert]>; |
| |
| def vsplati64_simm5 : SplatComplexPattern<vsplat_simm5, v2i64, 1, |
| "selectVSplatSimm5", |
| [build_vector, bitconvert]>; |
| |
| // Any build_vector that is a constant splat with a value that is an exact |
| // power of 2 |
| def vsplat_uimm_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmPow2", |
| [build_vector, bitconvert]>; |
| |
| // Any build_vector that is a constant splat with a value that is the bitwise |
| // inverse of an exact power of 2 |
| def vsplat_uimm_inv_pow2 : ComplexPattern<vAny, 1, "selectVSplatUimmInvPow2", |
| [build_vector, bitconvert]>; |
| |
| // Any build_vector that is a constant splat with only a consecutive sequence |
| // of left-most bits set. |
| def vsplat_maskl_bits_uimm3 |
| : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskL", |
| [build_vector, bitconvert]>; |
| def vsplat_maskl_bits_uimm4 |
| : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskL", |
| [build_vector, bitconvert]>; |
| def vsplat_maskl_bits_uimm5 |
| : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskL", |
| [build_vector, bitconvert]>; |
| def vsplat_maskl_bits_uimm6 |
| : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskL", |
| [build_vector, bitconvert]>; |
| |
| // Any build_vector that is a constant splat with only a consecutive sequence |
| // of right-most bits set. |
| def vsplat_maskr_bits_uimm3 |
| : SplatComplexPattern<vsplat_uimm3, vAny, 1, "selectVSplatMaskR", |
| [build_vector, bitconvert]>; |
| def vsplat_maskr_bits_uimm4 |
| : SplatComplexPattern<vsplat_uimm4, vAny, 1, "selectVSplatMaskR", |
| [build_vector, bitconvert]>; |
| def vsplat_maskr_bits_uimm5 |
| : SplatComplexPattern<vsplat_uimm5, vAny, 1, "selectVSplatMaskR", |
| [build_vector, bitconvert]>; |
| def vsplat_maskr_bits_uimm6 |
| : SplatComplexPattern<vsplat_uimm6, vAny, 1, "selectVSplatMaskR", |
| [build_vector, bitconvert]>; |
| |
| // Any build_vector that is a constant splat with a value that equals 1 |
| // FIXME: These should be a ComplexPattern but we can't use them because the |
| // ISel generator requires the uses to have a name, but providing a name |
| // causes other errors ("used in pattern but not operand list") |
| def vsplat_imm_eq_1 : PatLeaf<(build_vector), [{ |
| APInt Imm; |
| EVT EltTy = N->getValueType(0).getVectorElementType(); |
| |
| return selectVSplat(N, Imm, EltTy.getSizeInBits()) && |
| Imm.getBitWidth() == EltTy.getSizeInBits() && Imm == 1; |
| }]>; |
| |
| def vbclr_b : PatFrag<(ops node:$ws, node:$wt), |
| (and node:$ws, (vnot (shl vsplat_imm_eq_1, node:$wt)))>; |
| def vbclr_h : PatFrag<(ops node:$ws, node:$wt), |
| (and node:$ws, (vnot (shl vsplat_imm_eq_1, node:$wt)))>; |
| def vbclr_w : PatFrag<(ops node:$ws, node:$wt), |
| (and node:$ws, (vnot (shl vsplat_imm_eq_1, node:$wt)))>; |
| def vbclr_d : PatFrag<(ops node:$ws, node:$wt), |
| (and node:$ws, (vnot (shl (v2i64 vsplati64_imm_eq_1), |
| node:$wt)))>; |
| |
| def vbneg_b : PatFrag<(ops node:$ws, node:$wt), |
| (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; |
| def vbneg_h : PatFrag<(ops node:$ws, node:$wt), |
| (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; |
| def vbneg_w : PatFrag<(ops node:$ws, node:$wt), |
| (xor node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; |
| def vbneg_d : PatFrag<(ops node:$ws, node:$wt), |
| (xor node:$ws, (shl (v2i64 vsplati64_imm_eq_1), |
| node:$wt))>; |
| |
| def vbset_b : PatFrag<(ops node:$ws, node:$wt), |
| (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; |
| def vbset_h : PatFrag<(ops node:$ws, node:$wt), |
| (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; |
| def vbset_w : PatFrag<(ops node:$ws, node:$wt), |
| (or node:$ws, (shl vsplat_imm_eq_1, node:$wt))>; |
| def vbset_d : PatFrag<(ops node:$ws, node:$wt), |
| (or node:$ws, (shl (v2i64 vsplati64_imm_eq_1), |
| node:$wt))>; |
| |
| def muladd : PatFrag<(ops node:$wd, node:$ws, node:$wt), |
| (add node:$wd, (mul node:$ws, node:$wt))>; |
| |
| def mulsub : PatFrag<(ops node:$wd, node:$ws, node:$wt), |
| (sub node:$wd, (mul node:$ws, node:$wt))>; |
| |
| def mul_fexp2 : PatFrag<(ops node:$ws, node:$wt), |
| (fmul node:$ws, (fexp2 node:$wt))>; |
| |
| // Instruction encoding. |
| class ADD_A_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010000>; |
| class ADD_A_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010000>; |
| class ADD_A_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010000>; |
| class ADD_A_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010000>; |
| |
| class ADDS_A_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010000>; |
| class ADDS_A_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010000>; |
| class ADDS_A_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010000>; |
| class ADDS_A_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010000>; |
| |
| class ADDS_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010000>; |
| class ADDS_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010000>; |
| class ADDS_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010000>; |
| class ADDS_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010000>; |
| |
| class ADDS_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010000>; |
| class ADDS_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010000>; |
| class ADDS_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010000>; |
| class ADDS_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010000>; |
| |
| class ADDV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001110>; |
| class ADDV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001110>; |
| class ADDV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001110>; |
| class ADDV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001110>; |
| |
| class ADDVI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000110>; |
| class ADDVI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000110>; |
| class ADDVI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000110>; |
| class ADDVI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000110>; |
| |
| class AND_V_ENC : MSA_VEC_FMT<0b00000, 0b011110>; |
| |
| class ANDI_B_ENC : MSA_I8_FMT<0b00, 0b000000>; |
| |
| class ASUB_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010001>; |
| class ASUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010001>; |
| class ASUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010001>; |
| class ASUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010001>; |
| |
| class ASUB_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010001>; |
| class ASUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010001>; |
| class ASUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010001>; |
| class ASUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010001>; |
| |
| class AVE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010000>; |
| class AVE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010000>; |
| class AVE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010000>; |
| class AVE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010000>; |
| |
| class AVE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010000>; |
| class AVE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010000>; |
| class AVE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010000>; |
| class AVE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010000>; |
| |
| class AVER_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010000>; |
| class AVER_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010000>; |
| class AVER_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010000>; |
| class AVER_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010000>; |
| |
| class AVER_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010000>; |
| class AVER_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010000>; |
| class AVER_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010000>; |
| class AVER_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010000>; |
| |
| class BCLR_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001101>; |
| class BCLR_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001101>; |
| class BCLR_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001101>; |
| class BCLR_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001101>; |
| |
| class BCLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001001>; |
| class BCLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001001>; |
| class BCLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001001>; |
| class BCLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001001>; |
| |
| class BINSL_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001101>; |
| class BINSL_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001101>; |
| class BINSL_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001101>; |
| class BINSL_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001101>; |
| |
| class BINSLI_B_ENC : MSA_BIT_B_FMT<0b110, 0b001001>; |
| class BINSLI_H_ENC : MSA_BIT_H_FMT<0b110, 0b001001>; |
| class BINSLI_W_ENC : MSA_BIT_W_FMT<0b110, 0b001001>; |
| class BINSLI_D_ENC : MSA_BIT_D_FMT<0b110, 0b001001>; |
| |
| class BINSR_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001101>; |
| class BINSR_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001101>; |
| class BINSR_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001101>; |
| class BINSR_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001101>; |
| |
| class BINSRI_B_ENC : MSA_BIT_B_FMT<0b111, 0b001001>; |
| class BINSRI_H_ENC : MSA_BIT_H_FMT<0b111, 0b001001>; |
| class BINSRI_W_ENC : MSA_BIT_W_FMT<0b111, 0b001001>; |
| class BINSRI_D_ENC : MSA_BIT_D_FMT<0b111, 0b001001>; |
| |
| class BMNZ_V_ENC : MSA_VEC_FMT<0b00100, 0b011110>; |
| |
| class BMNZI_B_ENC : MSA_I8_FMT<0b00, 0b000001>; |
| |
| class BMZ_V_ENC : MSA_VEC_FMT<0b00101, 0b011110>; |
| |
| class BMZI_B_ENC : MSA_I8_FMT<0b01, 0b000001>; |
| |
| class BNEG_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001101>; |
| class BNEG_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001101>; |
| class BNEG_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001101>; |
| class BNEG_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001101>; |
| |
| class BNEGI_B_ENC : MSA_BIT_B_FMT<0b101, 0b001001>; |
| class BNEGI_H_ENC : MSA_BIT_H_FMT<0b101, 0b001001>; |
| class BNEGI_W_ENC : MSA_BIT_W_FMT<0b101, 0b001001>; |
| class BNEGI_D_ENC : MSA_BIT_D_FMT<0b101, 0b001001>; |
| |
| class BNZ_B_ENC : MSA_CBRANCH_FMT<0b111, 0b00>; |
| class BNZ_H_ENC : MSA_CBRANCH_FMT<0b111, 0b01>; |
| class BNZ_W_ENC : MSA_CBRANCH_FMT<0b111, 0b10>; |
| class BNZ_D_ENC : MSA_CBRANCH_FMT<0b111, 0b11>; |
| |
| class BNZ_V_ENC : MSA_CBRANCH_V_FMT<0b01111>; |
| |
| class BSEL_V_ENC : MSA_VEC_FMT<0b00110, 0b011110>; |
| |
| class BSELI_B_ENC : MSA_I8_FMT<0b10, 0b000001>; |
| |
| class BSET_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001101>; |
| class BSET_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001101>; |
| class BSET_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001101>; |
| class BSET_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001101>; |
| |
| class BSETI_B_ENC : MSA_BIT_B_FMT<0b100, 0b001001>; |
| class BSETI_H_ENC : MSA_BIT_H_FMT<0b100, 0b001001>; |
| class BSETI_W_ENC : MSA_BIT_W_FMT<0b100, 0b001001>; |
| class BSETI_D_ENC : MSA_BIT_D_FMT<0b100, 0b001001>; |
| |
| class BZ_B_ENC : MSA_CBRANCH_FMT<0b110, 0b00>; |
| class BZ_H_ENC : MSA_CBRANCH_FMT<0b110, 0b01>; |
| class BZ_W_ENC : MSA_CBRANCH_FMT<0b110, 0b10>; |
| class BZ_D_ENC : MSA_CBRANCH_FMT<0b110, 0b11>; |
| |
| class BZ_V_ENC : MSA_CBRANCH_V_FMT<0b01011>; |
| |
| class CEQ_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001111>; |
| class CEQ_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001111>; |
| class CEQ_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001111>; |
| class CEQ_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001111>; |
| |
| class CEQI_B_ENC : MSA_I5_FMT<0b000, 0b00, 0b000111>; |
| class CEQI_H_ENC : MSA_I5_FMT<0b000, 0b01, 0b000111>; |
| class CEQI_W_ENC : MSA_I5_FMT<0b000, 0b10, 0b000111>; |
| class CEQI_D_ENC : MSA_I5_FMT<0b000, 0b11, 0b000111>; |
| |
| class CFCMSA_ENC : MSA_ELM_CFCMSA_FMT<0b0001111110, 0b011001>; |
| |
| class CLE_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001111>; |
| class CLE_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001111>; |
| class CLE_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001111>; |
| class CLE_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001111>; |
| |
| class CLE_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001111>; |
| class CLE_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001111>; |
| class CLE_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001111>; |
| class CLE_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001111>; |
| |
| class CLEI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000111>; |
| class CLEI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000111>; |
| class CLEI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000111>; |
| class CLEI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000111>; |
| |
| class CLEI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000111>; |
| class CLEI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000111>; |
| class CLEI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000111>; |
| class CLEI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000111>; |
| |
| class CLT_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001111>; |
| class CLT_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001111>; |
| class CLT_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001111>; |
| class CLT_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001111>; |
| |
| class CLT_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001111>; |
| class CLT_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001111>; |
| class CLT_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001111>; |
| class CLT_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001111>; |
| |
| class CLTI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000111>; |
| class CLTI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000111>; |
| class CLTI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000111>; |
| class CLTI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000111>; |
| |
| class CLTI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000111>; |
| class CLTI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000111>; |
| class CLTI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000111>; |
| class CLTI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000111>; |
| |
| class COPY_S_B_ENC : MSA_ELM_COPY_B_FMT<0b0010, 0b011001>; |
| class COPY_S_H_ENC : MSA_ELM_COPY_H_FMT<0b0010, 0b011001>; |
| class COPY_S_W_ENC : MSA_ELM_COPY_W_FMT<0b0010, 0b011001>; |
| class COPY_S_D_ENC : MSA_ELM_COPY_D_FMT<0b0010, 0b011001>; |
| |
| class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>; |
| class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>; |
| class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>; |
| |
| class CTCMSA_ENC : MSA_ELM_CTCMSA_FMT<0b0000111110, 0b011001>; |
| |
| class DIV_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010010>; |
| class DIV_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010010>; |
| class DIV_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010010>; |
| class DIV_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010010>; |
| |
| class DIV_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010010>; |
| class DIV_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010010>; |
| class DIV_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010010>; |
| class DIV_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010010>; |
| |
| class DOTP_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010011>; |
| class DOTP_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010011>; |
| class DOTP_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010011>; |
| |
| class DOTP_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010011>; |
| class DOTP_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010011>; |
| class DOTP_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010011>; |
| |
| class DPADD_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010011>; |
| class DPADD_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010011>; |
| class DPADD_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010011>; |
| |
| class DPADD_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010011>; |
| class DPADD_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010011>; |
| class DPADD_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010011>; |
| |
| class DPSUB_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010011>; |
| class DPSUB_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010011>; |
| class DPSUB_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010011>; |
| |
| class DPSUB_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010011>; |
| class DPSUB_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010011>; |
| class DPSUB_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010011>; |
| |
| class FADD_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011011>; |
| class FADD_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011011>; |
| |
| class FCAF_W_ENC : MSA_3RF_FMT<0b0000, 0b0, 0b011010>; |
| class FCAF_D_ENC : MSA_3RF_FMT<0b0000, 0b1, 0b011010>; |
| |
| class FCEQ_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011010>; |
| class FCEQ_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011010>; |
| |
| class FCLASS_W_ENC : MSA_2RF_FMT<0b110010000, 0b0, 0b011110>; |
| class FCLASS_D_ENC : MSA_2RF_FMT<0b110010000, 0b1, 0b011110>; |
| |
| class FCLE_W_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011010>; |
| class FCLE_D_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011010>; |
| |
| class FCLT_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011010>; |
| class FCLT_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011010>; |
| |
| class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>; |
| class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>; |
| |
| class FCOR_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011100>; |
| class FCOR_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011100>; |
| |
| class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>; |
| class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>; |
| |
| class FCULE_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011010>; |
| class FCULE_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011010>; |
| |
| class FCULT_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011010>; |
| class FCULT_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011010>; |
| |
| class FCUN_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011010>; |
| class FCUN_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011010>; |
| |
| class FCUNE_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011100>; |
| class FCUNE_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011100>; |
| |
| class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>; |
| class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>; |
| |
| class FEXDO_H_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011011>; |
| class FEXDO_W_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011011>; |
| |
| class FEXP2_W_ENC : MSA_3RF_FMT<0b0111, 0b0, 0b011011>; |
| class FEXP2_D_ENC : MSA_3RF_FMT<0b0111, 0b1, 0b011011>; |
| |
| class FEXUPL_W_ENC : MSA_2RF_FMT<0b110011000, 0b0, 0b011110>; |
| class FEXUPL_D_ENC : MSA_2RF_FMT<0b110011000, 0b1, 0b011110>; |
| |
| class FEXUPR_W_ENC : MSA_2RF_FMT<0b110011001, 0b0, 0b011110>; |
| class FEXUPR_D_ENC : MSA_2RF_FMT<0b110011001, 0b1, 0b011110>; |
| |
| class FFINT_S_W_ENC : MSA_2RF_FMT<0b110011110, 0b0, 0b011110>; |
| class FFINT_S_D_ENC : MSA_2RF_FMT<0b110011110, 0b1, 0b011110>; |
| |
| class FFINT_U_W_ENC : MSA_2RF_FMT<0b110011111, 0b0, 0b011110>; |
| class FFINT_U_D_ENC : MSA_2RF_FMT<0b110011111, 0b1, 0b011110>; |
| |
| class FFQL_W_ENC : MSA_2RF_FMT<0b110011010, 0b0, 0b011110>; |
| class FFQL_D_ENC : MSA_2RF_FMT<0b110011010, 0b1, 0b011110>; |
| |
| class FFQR_W_ENC : MSA_2RF_FMT<0b110011011, 0b0, 0b011110>; |
| class FFQR_D_ENC : MSA_2RF_FMT<0b110011011, 0b1, 0b011110>; |
| |
| class FILL_B_ENC : MSA_2R_FILL_FMT<0b11000000, 0b00, 0b011110>; |
| class FILL_H_ENC : MSA_2R_FILL_FMT<0b11000000, 0b01, 0b011110>; |
| class FILL_W_ENC : MSA_2R_FILL_FMT<0b11000000, 0b10, 0b011110>; |
| class FILL_D_ENC : MSA_2R_FILL_D_FMT<0b11000000, 0b11, 0b011110>; |
| |
| class FLOG2_W_ENC : MSA_2RF_FMT<0b110010111, 0b0, 0b011110>; |
| class FLOG2_D_ENC : MSA_2RF_FMT<0b110010111, 0b1, 0b011110>; |
| |
| class FMADD_W_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011011>; |
| class FMADD_D_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011011>; |
| |
| class FMAX_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011011>; |
| class FMAX_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011011>; |
| |
| class FMAX_A_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011011>; |
| class FMAX_A_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011011>; |
| |
| class FMIN_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011011>; |
| class FMIN_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011011>; |
| |
| class FMIN_A_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011011>; |
| class FMIN_A_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011011>; |
| |
| class FMSUB_W_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011011>; |
| class FMSUB_D_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011011>; |
| |
| class FMUL_W_ENC : MSA_3RF_FMT<0b0010, 0b0, 0b011011>; |
| class FMUL_D_ENC : MSA_3RF_FMT<0b0010, 0b1, 0b011011>; |
| |
| class FRINT_W_ENC : MSA_2RF_FMT<0b110010110, 0b0, 0b011110>; |
| class FRINT_D_ENC : MSA_2RF_FMT<0b110010110, 0b1, 0b011110>; |
| |
| class FRCP_W_ENC : MSA_2RF_FMT<0b110010101, 0b0, 0b011110>; |
| class FRCP_D_ENC : MSA_2RF_FMT<0b110010101, 0b1, 0b011110>; |
| |
| class FRSQRT_W_ENC : MSA_2RF_FMT<0b110010100, 0b0, 0b011110>; |
| class FRSQRT_D_ENC : MSA_2RF_FMT<0b110010100, 0b1, 0b011110>; |
| |
| class FSAF_W_ENC : MSA_3RF_FMT<0b1000, 0b0, 0b011010>; |
| class FSAF_D_ENC : MSA_3RF_FMT<0b1000, 0b1, 0b011010>; |
| |
| class FSEQ_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011010>; |
| class FSEQ_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011010>; |
| |
| class FSLE_W_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011010>; |
| class FSLE_D_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011010>; |
| |
| class FSLT_W_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011010>; |
| class FSLT_D_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011010>; |
| |
| class FSNE_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011100>; |
| class FSNE_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011100>; |
| |
| class FSOR_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011100>; |
| class FSOR_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011100>; |
| |
| class FSQRT_W_ENC : MSA_2RF_FMT<0b110010011, 0b0, 0b011110>; |
| class FSQRT_D_ENC : MSA_2RF_FMT<0b110010011, 0b1, 0b011110>; |
| |
| class FSUB_W_ENC : MSA_3RF_FMT<0b0001, 0b0, 0b011011>; |
| class FSUB_D_ENC : MSA_3RF_FMT<0b0001, 0b1, 0b011011>; |
| |
| class FSUEQ_W_ENC : MSA_3RF_FMT<0b1011, 0b0, 0b011010>; |
| class FSUEQ_D_ENC : MSA_3RF_FMT<0b1011, 0b1, 0b011010>; |
| |
| class FSULE_W_ENC : MSA_3RF_FMT<0b1111, 0b0, 0b011010>; |
| class FSULE_D_ENC : MSA_3RF_FMT<0b1111, 0b1, 0b011010>; |
| |
| class FSULT_W_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011010>; |
| class FSULT_D_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011010>; |
| |
| class FSUN_W_ENC : MSA_3RF_FMT<0b1001, 0b0, 0b011010>; |
| class FSUN_D_ENC : MSA_3RF_FMT<0b1001, 0b1, 0b011010>; |
| |
| class FSUNE_W_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011100>; |
| class FSUNE_D_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011100>; |
| |
| class FTINT_S_W_ENC : MSA_2RF_FMT<0b110011100, 0b0, 0b011110>; |
| class FTINT_S_D_ENC : MSA_2RF_FMT<0b110011100, 0b1, 0b011110>; |
| |
| class FTINT_U_W_ENC : MSA_2RF_FMT<0b110011101, 0b0, 0b011110>; |
| class FTINT_U_D_ENC : MSA_2RF_FMT<0b110011101, 0b1, 0b011110>; |
| |
| class FTQ_H_ENC : MSA_3RF_FMT<0b1010, 0b0, 0b011011>; |
| class FTQ_W_ENC : MSA_3RF_FMT<0b1010, 0b1, 0b011011>; |
| |
| class FTRUNC_S_W_ENC : MSA_2RF_FMT<0b110010001, 0b0, 0b011110>; |
| class FTRUNC_S_D_ENC : MSA_2RF_FMT<0b110010001, 0b1, 0b011110>; |
| |
| class FTRUNC_U_W_ENC : MSA_2RF_FMT<0b110010010, 0b0, 0b011110>; |
| class FTRUNC_U_D_ENC : MSA_2RF_FMT<0b110010010, 0b1, 0b011110>; |
| |
| class HADD_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010101>; |
| class HADD_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010101>; |
| class HADD_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010101>; |
| |
| class HADD_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010101>; |
| class HADD_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010101>; |
| class HADD_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010101>; |
| |
| class HSUB_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010101>; |
| class HSUB_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010101>; |
| class HSUB_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010101>; |
| |
| class HSUB_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010101>; |
| class HSUB_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010101>; |
| class HSUB_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010101>; |
| |
| class ILVEV_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010100>; |
| class ILVEV_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010100>; |
| class ILVEV_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010100>; |
| class ILVEV_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010100>; |
| |
| class ILVL_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b010100>; |
| class ILVL_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b010100>; |
| class ILVL_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b010100>; |
| class ILVL_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b010100>; |
| |
| class ILVOD_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010100>; |
| class ILVOD_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010100>; |
| class ILVOD_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010100>; |
| class ILVOD_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010100>; |
| |
| class ILVR_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b010100>; |
| class ILVR_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b010100>; |
| class ILVR_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b010100>; |
| class ILVR_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b010100>; |
| |
| class INSERT_B_ENC : MSA_ELM_INSERT_B_FMT<0b0100, 0b011001>; |
| class INSERT_H_ENC : MSA_ELM_INSERT_H_FMT<0b0100, 0b011001>; |
| class INSERT_W_ENC : MSA_ELM_INSERT_W_FMT<0b0100, 0b011001>; |
| class INSERT_D_ENC : MSA_ELM_INSERT_D_FMT<0b0100, 0b011001>; |
| |
| class INSVE_B_ENC : MSA_ELM_B_FMT<0b0101, 0b011001>; |
| class INSVE_H_ENC : MSA_ELM_H_FMT<0b0101, 0b011001>; |
| class INSVE_W_ENC : MSA_ELM_W_FMT<0b0101, 0b011001>; |
| class INSVE_D_ENC : MSA_ELM_D_FMT<0b0101, 0b011001>; |
| |
| class LD_B_ENC : MSA_MI10_FMT<0b00, 0b1000>; |
| class LD_H_ENC : MSA_MI10_FMT<0b01, 0b1000>; |
| class LD_W_ENC : MSA_MI10_FMT<0b10, 0b1000>; |
| class LD_D_ENC : MSA_MI10_FMT<0b11, 0b1000>; |
| |
| class LDI_B_ENC : MSA_I10_FMT<0b110, 0b00, 0b000111>; |
| class LDI_H_ENC : MSA_I10_FMT<0b110, 0b01, 0b000111>; |
| class LDI_W_ENC : MSA_I10_FMT<0b110, 0b10, 0b000111>; |
| class LDI_D_ENC : MSA_I10_FMT<0b110, 0b11, 0b000111>; |
| |
| class LSA_ENC : SPECIAL_LSA_FMT<0b000101>; |
| class DLSA_ENC : SPECIAL_DLSA_FMT<0b010101>; |
| |
| class MADD_Q_H_ENC : MSA_3RF_FMT<0b0101, 0b0, 0b011100>; |
| class MADD_Q_W_ENC : MSA_3RF_FMT<0b0101, 0b1, 0b011100>; |
| |
| class MADDR_Q_H_ENC : MSA_3RF_FMT<0b1101, 0b0, 0b011100>; |
| class MADDR_Q_W_ENC : MSA_3RF_FMT<0b1101, 0b1, 0b011100>; |
| |
| class MADDV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010010>; |
| class MADDV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010010>; |
| class MADDV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010010>; |
| class MADDV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010010>; |
| |
| class MAX_A_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b001110>; |
| class MAX_A_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b001110>; |
| class MAX_A_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b001110>; |
| class MAX_A_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b001110>; |
| |
| class MAX_S_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001110>; |
| class MAX_S_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001110>; |
| class MAX_S_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001110>; |
| class MAX_S_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001110>; |
| |
| class MAX_U_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b001110>; |
| class MAX_U_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b001110>; |
| class MAX_U_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b001110>; |
| class MAX_U_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b001110>; |
| |
| class MAXI_S_B_ENC : MSA_I5_FMT<0b010, 0b00, 0b000110>; |
| class MAXI_S_H_ENC : MSA_I5_FMT<0b010, 0b01, 0b000110>; |
| class MAXI_S_W_ENC : MSA_I5_FMT<0b010, 0b10, 0b000110>; |
| class MAXI_S_D_ENC : MSA_I5_FMT<0b010, 0b11, 0b000110>; |
| |
| class MAXI_U_B_ENC : MSA_I5_FMT<0b011, 0b00, 0b000110>; |
| class MAXI_U_H_ENC : MSA_I5_FMT<0b011, 0b01, 0b000110>; |
| class MAXI_U_W_ENC : MSA_I5_FMT<0b011, 0b10, 0b000110>; |
| class MAXI_U_D_ENC : MSA_I5_FMT<0b011, 0b11, 0b000110>; |
| |
| class MIN_A_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b001110>; |
| class MIN_A_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b001110>; |
| class MIN_A_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b001110>; |
| class MIN_A_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b001110>; |
| |
| class MIN_S_B_ENC : MSA_3R_FMT<0b100, 0b00, 0b001110>; |
| class MIN_S_H_ENC : MSA_3R_FMT<0b100, 0b01, 0b001110>; |
| class MIN_S_W_ENC : MSA_3R_FMT<0b100, 0b10, 0b001110>; |
| class MIN_S_D_ENC : MSA_3R_FMT<0b100, 0b11, 0b001110>; |
| |
| class MIN_U_B_ENC : MSA_3R_FMT<0b101, 0b00, 0b001110>; |
| class MIN_U_H_ENC : MSA_3R_FMT<0b101, 0b01, 0b001110>; |
| class MIN_U_W_ENC : MSA_3R_FMT<0b101, 0b10, 0b001110>; |
| class MIN_U_D_ENC : MSA_3R_FMT<0b101, 0b11, 0b001110>; |
| |
| class MINI_S_B_ENC : MSA_I5_FMT<0b100, 0b00, 0b000110>; |
| class MINI_S_H_ENC : MSA_I5_FMT<0b100, 0b01, 0b000110>; |
| class MINI_S_W_ENC : MSA_I5_FMT<0b100, 0b10, 0b000110>; |
| class MINI_S_D_ENC : MSA_I5_FMT<0b100, 0b11, 0b000110>; |
| |
| class MINI_U_B_ENC : MSA_I5_FMT<0b101, 0b00, 0b000110>; |
| class MINI_U_H_ENC : MSA_I5_FMT<0b101, 0b01, 0b000110>; |
| class MINI_U_W_ENC : MSA_I5_FMT<0b101, 0b10, 0b000110>; |
| class MINI_U_D_ENC : MSA_I5_FMT<0b101, 0b11, 0b000110>; |
| |
| class MOD_S_B_ENC : MSA_3R_FMT<0b110, 0b00, 0b010010>; |
| class MOD_S_H_ENC : MSA_3R_FMT<0b110, 0b01, 0b010010>; |
| class MOD_S_W_ENC : MSA_3R_FMT<0b110, 0b10, 0b010010>; |
| class MOD_S_D_ENC : MSA_3R_FMT<0b110, 0b11, 0b010010>; |
| |
| class MOD_U_B_ENC : MSA_3R_FMT<0b111, 0b00, 0b010010>; |
| class MOD_U_H_ENC : MSA_3R_FMT<0b111, 0b01, 0b010010>; |
| class MOD_U_W_ENC : MSA_3R_FMT<0b111, 0b10, 0b010010>; |
| class MOD_U_D_ENC : MSA_3R_FMT<0b111, 0b11, 0b010010>; |
| |
| class MOVE_V_ENC : MSA_ELM_FMT<0b0010111110, 0b011001>; |
| |
| class MSUB_Q_H_ENC : MSA_3RF_FMT<0b0110, 0b0, 0b011100>; |
| class MSUB_Q_W_ENC : MSA_3RF_FMT<0b0110, 0b1, 0b011100>; |
| |
| class MSUBR_Q_H_ENC : MSA_3RF_FMT<0b1110, 0b0, 0b011100>; |
| class MSUBR_Q_W_ENC : MSA_3RF_FMT<0b1110, 0b1, 0b011100>; |
| |
| class MSUBV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010010>; |
| class MSUBV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010010>; |
| class MSUBV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010010>; |
| class MSUBV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010010>; |
| |
| class MUL_Q_H_ENC : MSA_3RF_FMT<0b0100, 0b0, 0b011100>; |
| class MUL_Q_W_ENC : MSA_3RF_FMT<0b0100, 0b1, 0b011100>; |
| |
| class MULR_Q_H_ENC : MSA_3RF_FMT<0b1100, 0b0, 0b011100>; |
| class MULR_Q_W_ENC : MSA_3RF_FMT<0b1100, 0b1, 0b011100>; |
| |
| class MULV_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010010>; |
| class MULV_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010010>; |
| class MULV_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010010>; |
| class MULV_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010010>; |
| |
| class NLOC_B_ENC : MSA_2R_FMT<0b11000010, 0b00, 0b011110>; |
| class NLOC_H_ENC : MSA_2R_FMT<0b11000010, 0b01, 0b011110>; |
| class NLOC_W_ENC : MSA_2R_FMT<0b11000010, 0b10, 0b011110>; |
| class NLOC_D_ENC : MSA_2R_FMT<0b11000010, 0b11, 0b011110>; |
| |
| class NLZC_B_ENC : MSA_2R_FMT<0b11000011, 0b00, 0b011110>; |
| class NLZC_H_ENC : MSA_2R_FMT<0b11000011, 0b01, 0b011110>; |
| class NLZC_W_ENC : MSA_2R_FMT<0b11000011, 0b10, 0b011110>; |
| class NLZC_D_ENC : MSA_2R_FMT<0b11000011, 0b11, 0b011110>; |
| |
| class NOR_V_ENC : MSA_VEC_FMT<0b00010, 0b011110>; |
| |
| class NORI_B_ENC : MSA_I8_FMT<0b10, 0b000000>; |
| |
| class OR_V_ENC : MSA_VEC_FMT<0b00001, 0b011110>; |
| |
| class ORI_B_ENC : MSA_I8_FMT<0b01, 0b000000>; |
| |
| class PCKEV_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010100>; |
| class PCKEV_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010100>; |
| class PCKEV_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010100>; |
| class PCKEV_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010100>; |
| |
| class PCKOD_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010100>; |
| class PCKOD_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010100>; |
| class PCKOD_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010100>; |
| class PCKOD_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010100>; |
| |
| class PCNT_B_ENC : MSA_2R_FMT<0b11000001, 0b00, 0b011110>; |
| class PCNT_H_ENC : MSA_2R_FMT<0b11000001, 0b01, 0b011110>; |
| class PCNT_W_ENC : MSA_2R_FMT<0b11000001, 0b10, 0b011110>; |
| class PCNT_D_ENC : MSA_2R_FMT<0b11000001, 0b11, 0b011110>; |
| |
| class SAT_S_B_ENC : MSA_BIT_B_FMT<0b000, 0b001010>; |
| class SAT_S_H_ENC : MSA_BIT_H_FMT<0b000, 0b001010>; |
| class SAT_S_W_ENC : MSA_BIT_W_FMT<0b000, 0b001010>; |
| class SAT_S_D_ENC : MSA_BIT_D_FMT<0b000, 0b001010>; |
| |
| class SAT_U_B_ENC : MSA_BIT_B_FMT<0b001, 0b001010>; |
| class SAT_U_H_ENC : MSA_BIT_H_FMT<0b001, 0b001010>; |
| class SAT_U_W_ENC : MSA_BIT_W_FMT<0b001, 0b001010>; |
| class SAT_U_D_ENC : MSA_BIT_D_FMT<0b001, 0b001010>; |
| |
| class SHF_B_ENC : MSA_I8_FMT<0b00, 0b000010>; |
| class SHF_H_ENC : MSA_I8_FMT<0b01, 0b000010>; |
| class SHF_W_ENC : MSA_I8_FMT<0b10, 0b000010>; |
| |
| class SLD_B_ENC : MSA_3R_INDEX_FMT<0b000, 0b00, 0b010100>; |
| class SLD_H_ENC : MSA_3R_INDEX_FMT<0b000, 0b01, 0b010100>; |
| class SLD_W_ENC : MSA_3R_INDEX_FMT<0b000, 0b10, 0b010100>; |
| class SLD_D_ENC : MSA_3R_INDEX_FMT<0b000, 0b11, 0b010100>; |
| |
| class SLDI_B_ENC : MSA_ELM_B_FMT<0b0000, 0b011001>; |
| class SLDI_H_ENC : MSA_ELM_H_FMT<0b0000, 0b011001>; |
| class SLDI_W_ENC : MSA_ELM_W_FMT<0b0000, 0b011001>; |
| class SLDI_D_ENC : MSA_ELM_D_FMT<0b0000, 0b011001>; |
| |
| class SLL_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b001101>; |
| class SLL_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b001101>; |
| class SLL_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b001101>; |
| class SLL_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b001101>; |
| |
| class SLLI_B_ENC : MSA_BIT_B_FMT<0b000, 0b001001>; |
| class SLLI_H_ENC : MSA_BIT_H_FMT<0b000, 0b001001>; |
| class SLLI_W_ENC : MSA_BIT_W_FMT<0b000, 0b001001>; |
| class SLLI_D_ENC : MSA_BIT_D_FMT<0b000, 0b001001>; |
| |
| class SPLAT_B_ENC : MSA_3R_INDEX_FMT<0b001, 0b00, 0b010100>; |
| class SPLAT_H_ENC : MSA_3R_INDEX_FMT<0b001, 0b01, 0b010100>; |
| class SPLAT_W_ENC : MSA_3R_INDEX_FMT<0b001, 0b10, 0b010100>; |
| class SPLAT_D_ENC : MSA_3R_INDEX_FMT<0b001, 0b11, 0b010100>; |
| |
| class SPLATI_B_ENC : MSA_ELM_B_FMT<0b0001, 0b011001>; |
| class SPLATI_H_ENC : MSA_ELM_H_FMT<0b0001, 0b011001>; |
| class SPLATI_W_ENC : MSA_ELM_W_FMT<0b0001, 0b011001>; |
| class SPLATI_D_ENC : MSA_ELM_D_FMT<0b0001, 0b011001>; |
| |
| class SRA_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001101>; |
| class SRA_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001101>; |
| class SRA_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001101>; |
| class SRA_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001101>; |
| |
| class SRAI_B_ENC : MSA_BIT_B_FMT<0b001, 0b001001>; |
| class SRAI_H_ENC : MSA_BIT_H_FMT<0b001, 0b001001>; |
| class SRAI_W_ENC : MSA_BIT_W_FMT<0b001, 0b001001>; |
| class SRAI_D_ENC : MSA_BIT_D_FMT<0b001, 0b001001>; |
| |
| class SRAR_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010101>; |
| class SRAR_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010101>; |
| class SRAR_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010101>; |
| class SRAR_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010101>; |
| |
| class SRARI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001010>; |
| class SRARI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001010>; |
| class SRARI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001010>; |
| class SRARI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001010>; |
| |
| class SRL_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b001101>; |
| class SRL_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b001101>; |
| class SRL_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b001101>; |
| class SRL_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b001101>; |
| |
| class SRLI_B_ENC : MSA_BIT_B_FMT<0b010, 0b001001>; |
| class SRLI_H_ENC : MSA_BIT_H_FMT<0b010, 0b001001>; |
| class SRLI_W_ENC : MSA_BIT_W_FMT<0b010, 0b001001>; |
| class SRLI_D_ENC : MSA_BIT_D_FMT<0b010, 0b001001>; |
| |
| class SRLR_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010101>; |
| class SRLR_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010101>; |
| class SRLR_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010101>; |
| class SRLR_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010101>; |
| |
| class SRLRI_B_ENC : MSA_BIT_B_FMT<0b011, 0b001010>; |
| class SRLRI_H_ENC : MSA_BIT_H_FMT<0b011, 0b001010>; |
| class SRLRI_W_ENC : MSA_BIT_W_FMT<0b011, 0b001010>; |
| class SRLRI_D_ENC : MSA_BIT_D_FMT<0b011, 0b001010>; |
| |
| class ST_B_ENC : MSA_MI10_FMT<0b00, 0b1001>; |
| class ST_H_ENC : MSA_MI10_FMT<0b01, 0b1001>; |
| class ST_W_ENC : MSA_MI10_FMT<0b10, 0b1001>; |
| class ST_D_ENC : MSA_MI10_FMT<0b11, 0b1001>; |
| |
| class SUBS_S_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010001>; |
| class SUBS_S_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010001>; |
| class SUBS_S_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010001>; |
| class SUBS_S_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010001>; |
| |
| class SUBS_U_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b010001>; |
| class SUBS_U_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b010001>; |
| class SUBS_U_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b010001>; |
| class SUBS_U_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b010001>; |
| |
| class SUBSUS_U_B_ENC : MSA_3R_FMT<0b010, 0b00, 0b010001>; |
| class SUBSUS_U_H_ENC : MSA_3R_FMT<0b010, 0b01, 0b010001>; |
| class SUBSUS_U_W_ENC : MSA_3R_FMT<0b010, 0b10, 0b010001>; |
| class SUBSUS_U_D_ENC : MSA_3R_FMT<0b010, 0b11, 0b010001>; |
| |
| class SUBSUU_S_B_ENC : MSA_3R_FMT<0b011, 0b00, 0b010001>; |
| class SUBSUU_S_H_ENC : MSA_3R_FMT<0b011, 0b01, 0b010001>; |
| class SUBSUU_S_W_ENC : MSA_3R_FMT<0b011, 0b10, 0b010001>; |
| class SUBSUU_S_D_ENC : MSA_3R_FMT<0b011, 0b11, 0b010001>; |
| |
| class SUBV_B_ENC : MSA_3R_FMT<0b001, 0b00, 0b001110>; |
| class SUBV_H_ENC : MSA_3R_FMT<0b001, 0b01, 0b001110>; |
| class SUBV_W_ENC : MSA_3R_FMT<0b001, 0b10, 0b001110>; |
| class SUBV_D_ENC : MSA_3R_FMT<0b001, 0b11, 0b001110>; |
| |
| class SUBVI_B_ENC : MSA_I5_FMT<0b001, 0b00, 0b000110>; |
| class SUBVI_H_ENC : MSA_I5_FMT<0b001, 0b01, 0b000110>; |
| class SUBVI_W_ENC : MSA_I5_FMT<0b001, 0b10, 0b000110>; |
| class SUBVI_D_ENC : MSA_I5_FMT<0b001, 0b11, 0b000110>; |
| |
| class VSHF_B_ENC : MSA_3R_FMT<0b000, 0b00, 0b010101>; |
| class VSHF_H_ENC : MSA_3R_FMT<0b000, 0b01, 0b010101>; |
| class VSHF_W_ENC : MSA_3R_FMT<0b000, 0b10, 0b010101>; |
| class VSHF_D_ENC : MSA_3R_FMT<0b000, 0b11, 0b010101>; |
| |
| class XOR_V_ENC : MSA_VEC_FMT<0b00011, 0b011110>; |
| |
| class XORI_B_ENC : MSA_I8_FMT<0b11, 0b000000>; |
| |
| // Instruction desc. |
| class MSA_BIT_B_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| ComplexPattern Imm, RegisterOperand ROWD, |
| RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWS:$ws, vsplat_uimm3:$m); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_BIT_H_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| ComplexPattern Imm, RegisterOperand ROWD, |
| RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWS:$ws, vsplat_uimm4:$m); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_BIT_W_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| ComplexPattern Imm, RegisterOperand ROWD, |
| RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWS:$ws, vsplat_uimm5:$m); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_BIT_D_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| ComplexPattern Imm, RegisterOperand ROWD, |
| RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWS:$ws, vsplat_uimm6:$m); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_BIT_X_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, |
| RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWS:$ws, ImmOp:$m); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, Imm:$m))]; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_BIT_BINSXI_DESC_BASE<string instr_asm, ValueType Ty, |
| SplatComplexPattern Mask, RegisterOperand ROWD, |
| RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, Mask.OpClass:$m); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); |
| // Note that binsxi and vselect treat the condition operand the opposite |
| // way to each other. |
| // (vselect cond, if_set, if_clear) |
| // (BSEL_V cond, if_clear, if_set) |
| list<dag> Pattern = [(set ROWD:$wd, (vselect (Ty Mask:$m), (Ty ROWD:$ws), |
| ROWS:$wd_in))]; |
| InstrItinClass Itinerary = itin; |
| string Constraints = "$wd = $wd_in"; |
| } |
| |
| class MSA_BIT_BINSLI_DESC_BASE<string instr_asm, ValueType Ty, |
| SplatComplexPattern ImmOp, RegisterOperand ROWD, |
| RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> : |
| MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; |
| |
| class MSA_BIT_BINSRI_DESC_BASE<string instr_asm, ValueType Ty, |
| SplatComplexPattern ImmOp, RegisterOperand ROWD, |
| RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> : |
| MSA_BIT_BINSXI_DESC_BASE<instr_asm, Ty, ImmOp, ROWD, ROWS, itin>; |
| |
| class MSA_BIT_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| SplatComplexPattern SplatImm, |
| RegisterOperand ROWD, RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$m); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $m"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$m))]; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_COPY_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| ValueType VecTy, Operand ImmOp, ImmLeaf Imm, |
| RegisterOperand ROD, RegisterOperand ROWS, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROD:$rd); |
| dag InOperandList = (ins ROWS:$ws, ImmOp:$n); |
| string AsmString = !strconcat(instr_asm, "\t$rd, $ws[$n]"); |
| list<dag> Pattern = [(set ROD:$rd, (OpNode (VecTy ROWS:$ws), Imm:$n))]; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_ELM_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| RegisterOperand ROWD, RegisterOperand ROWS, |
| Operand ImmOp, ImmLeaf Imm, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ImmOp:$n); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, |
| Imm:$n))]; |
| string Constraints = "$wd = $wd_in"; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_COPY_PSEUDO_BASE<SDPatternOperator OpNode, ValueType VecTy, |
| Operand ImmOp, ImmLeaf Imm, RegisterClass RCD, |
| RegisterClass RCWS> : |
| MSAPseudo<(outs RCD:$wd), (ins RCWS:$ws, ImmOp:$n), |
| [(set RCD:$wd, (OpNode (VecTy RCWS:$ws), Imm:$n))]> { |
| bit usesCustomInserter = 1; |
| bit hasNoSchedulingInfo = 1; |
| } |
| |
| class MSA_I5_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| SplatComplexPattern SplatImm, RegisterOperand ROWD, |
| RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$imm); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $imm"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$imm))]; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_I8_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| SplatComplexPattern SplatImm, RegisterOperand ROWD, |
| RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$u8); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, SplatImm:$u8))]; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_I8_SHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, |
| RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWS:$ws, uimm8:$u8); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $u8"); |
| list<dag> Pattern = [(set ROWD:$wd, (MipsSHF timmZExt8:$u8, ROWS:$ws))]; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_I10_LDI_DESC_BASE<string instr_asm, RegisterOperand ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins vsplat_simm10:$s10); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $s10"); |
| // LDI is matched using custom matching code in MipsSEISelDAGToDAG.cpp |
| list<dag> Pattern = []; |
| bit hasSideEffects = 0; |
| bit isReMaterializable = 1; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_2R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| RegisterOperand ROWD, RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWS:$ws); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_2R_FILL_DESC_BASE<string instr_asm, ValueType VT, |
| SDPatternOperator OpNode, RegisterOperand ROWD, |
| RegisterOperand ROS = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROS:$rs); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $rs"); |
| list<dag> Pattern = [(set ROWD:$wd, (VT (OpNode ROS:$rs)))]; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_2R_FILL_PSEUDO_BASE<SDPatternOperator OpNode, |
| RegisterClass RCWD, RegisterClass RCWS> : |
| MSAPseudo<(outs RCWD:$wd), (ins RCWS:$fs), |
| [(set RCWD:$wd, (OpNode RCWS:$fs))]> { |
| let usesCustomInserter = 1; |
| } |
| |
| class MSA_2RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| RegisterOperand ROWD, RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWS:$ws); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws))]; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_3R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| RegisterOperand ROWD, RegisterOperand ROWS = ROWD, |
| RegisterOperand ROWT = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWS:$ws, ROWT:$wt); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_3R_BINSX_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| RegisterOperand ROWD, RegisterOperand ROWS = ROWD, |
| RegisterOperand ROWT = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, |
| ROWT:$wt))]; |
| string Constraints = "$wd = $wd_in"; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_3R_SPLAT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| RegisterOperand ROWD, RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWS:$ws, GPR32Opnd:$rt); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, GPR32Opnd:$rt))]; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_3R_VSHF_DESC_BASE<string instr_asm, RegisterOperand ROWD, |
| RegisterOperand ROWS = ROWD, |
| RegisterOperand ROWT = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); |
| list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF ROWD:$wd_in, ROWS:$ws, |
| ROWT:$wt))]; |
| string Constraints = "$wd = $wd_in"; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_3R_SLD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| RegisterOperand ROWD, RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, GPR32Opnd:$rt); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$rt]"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, |
| GPR32Opnd:$rt))]; |
| InstrItinClass Itinerary = itin; |
| string Constraints = "$wd = $wd_in"; |
| } |
| |
| class MSA_3R_4R_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| RegisterOperand ROWD, RegisterOperand ROWS = ROWD, |
| RegisterOperand ROWT = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWD:$wd_in, ROWS:$ws, ROWT:$wt); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROWS:$ws, |
| ROWT:$wt))]; |
| InstrItinClass Itinerary = itin; |
| string Constraints = "$wd = $wd_in"; |
| } |
| |
| class MSA_3RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| RegisterOperand ROWD, RegisterOperand ROWS = ROWD, |
| RegisterOperand ROWT = ROWD, |
| InstrItinClass itin = NoItinerary> : |
| MSA_3R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; |
| |
| class MSA_3RF_4RF_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| RegisterOperand ROWD, RegisterOperand ROWS = ROWD, |
| RegisterOperand ROWT = ROWD, |
| InstrItinClass itin = NoItinerary> : |
| MSA_3R_4R_DESC_BASE<instr_asm, OpNode, ROWD, ROWS, ROWT, itin>; |
| |
| class MSA_CBRANCH_DESC_BASE<string instr_asm, RegisterOperand ROWD> { |
| dag OutOperandList = (outs); |
| dag InOperandList = (ins ROWD:$wt, brtarget:$offset); |
| string AsmString = !strconcat(instr_asm, "\t$wt, $offset"); |
| list<dag> Pattern = []; |
| InstrItinClass Itinerary = NoItinerary; |
| bit isBranch = 1; |
| bit isTerminator = 1; |
| bit hasDelaySlot = 1; |
| list<Register> Defs = [AT]; |
| } |
| |
| class MSA_INSERT_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, |
| RegisterOperand ROS, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWD:$wd_in, ROS:$rs, ImmOp:$n); |
| string AsmString = !strconcat(instr_asm, "\t$wd[$n], $rs"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, ROS:$rs, Imm:$n))]; |
| InstrItinClass Itinerary = itin; |
| string Constraints = "$wd = $wd_in"; |
| } |
| |
| class MSA_INSERT_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, |
| Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, |
| RegisterOperand ROFS> : |
| MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ImmOp:$n, ROFS:$fs), |
| [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, Imm:$n))]> { |
| bit usesCustomInserter = 1; |
| string Constraints = "$wd = $wd_in"; |
| } |
| |
| class MSA_INSERT_VIDX_PSEUDO_BASE<SDPatternOperator OpNode, ValueType Ty, |
| RegisterOperand ROWD, RegisterOperand ROFS, |
| RegisterOperand ROIdx> : |
| MSAPseudo<(outs ROWD:$wd), (ins ROWD:$wd_in, ROIdx:$n, ROFS:$fs), |
| [(set ROWD:$wd, (OpNode (Ty ROWD:$wd_in), ROFS:$fs, |
| ROIdx:$n))]> { |
| bit usesCustomInserter = 1; |
| bit hasNoSchedulingInfo = 1; |
| string Constraints = "$wd = $wd_in"; |
| } |
| |
| class MSA_INSVE_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| Operand ImmOp, ImmLeaf Imm, RegisterOperand ROWD, |
| RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWD:$wd_in, ImmOp:$n, ROWS:$ws, uimmz:$n2); |
| string AsmString = !strconcat(instr_asm, "\t$wd[$n], $ws[$n2]"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWD:$wd_in, |
| Imm:$n, |
| ROWS:$ws, |
| immz:$n2))]; |
| InstrItinClass Itinerary = itin; |
| string Constraints = "$wd = $wd_in"; |
| } |
| |
| class MSA_VEC_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| RegisterOperand ROWD, RegisterOperand ROWS = ROWD, |
| RegisterOperand ROWT = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWS:$ws, ROWT:$wt); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws, $wt"); |
| list<dag> Pattern = [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_ELM_SPLAT_DESC_BASE<string instr_asm, SplatComplexPattern SplatImm, |
| RegisterOperand ROWD, |
| RegisterOperand ROWS = ROWD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins ROWS:$ws, SplatImm.OpClass:$n); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $ws[$n]"); |
| list<dag> Pattern = [(set ROWD:$wd, (MipsVSHF SplatImm:$n, ROWS:$ws, |
| ROWS:$ws))]; |
| InstrItinClass Itinerary = itin; |
| } |
| |
| class MSA_VEC_PSEUDO_BASE<SDPatternOperator OpNode, RegisterOperand ROWD, |
| RegisterOperand ROWS = ROWD, |
| RegisterOperand ROWT = ROWD> : |
| MSAPseudo<(outs ROWD:$wd), (ins ROWS:$ws, ROWT:$wt), |
| [(set ROWD:$wd, (OpNode ROWS:$ws, ROWT:$wt))]>; |
| |
| class ADD_A_B_DESC : MSA_3R_DESC_BASE<"add_a.b", int_mips_add_a_b, MSA128BOpnd>, |
| IsCommutable; |
| class ADD_A_H_DESC : MSA_3R_DESC_BASE<"add_a.h", int_mips_add_a_h, MSA128HOpnd>, |
| IsCommutable; |
| class ADD_A_W_DESC : MSA_3R_DESC_BASE<"add_a.w", int_mips_add_a_w, MSA128WOpnd>, |
| IsCommutable; |
| class ADD_A_D_DESC : MSA_3R_DESC_BASE<"add_a.d", int_mips_add_a_d, MSA128DOpnd>, |
| IsCommutable; |
| |
| class ADDS_A_B_DESC : MSA_3R_DESC_BASE<"adds_a.b", int_mips_adds_a_b, |
| MSA128BOpnd>, IsCommutable; |
| class ADDS_A_H_DESC : MSA_3R_DESC_BASE<"adds_a.h", int_mips_adds_a_h, |
| MSA128HOpnd>, IsCommutable; |
| class ADDS_A_W_DESC : MSA_3R_DESC_BASE<"adds_a.w", int_mips_adds_a_w, |
| MSA128WOpnd>, IsCommutable; |
| class ADDS_A_D_DESC : MSA_3R_DESC_BASE<"adds_a.d", int_mips_adds_a_d, |
| MSA128DOpnd>, IsCommutable; |
| |
| class ADDS_S_B_DESC : MSA_3R_DESC_BASE<"adds_s.b", int_mips_adds_s_b, |
| MSA128BOpnd>, IsCommutable; |
| class ADDS_S_H_DESC : MSA_3R_DESC_BASE<"adds_s.h", int_mips_adds_s_h, |
| MSA128HOpnd>, IsCommutable; |
| class ADDS_S_W_DESC : MSA_3R_DESC_BASE<"adds_s.w", int_mips_adds_s_w, |
| MSA128WOpnd>, IsCommutable; |
| class ADDS_S_D_DESC : MSA_3R_DESC_BASE<"adds_s.d", int_mips_adds_s_d, |
| MSA128DOpnd>, IsCommutable; |
| |
| class ADDS_U_B_DESC : MSA_3R_DESC_BASE<"adds_u.b", int_mips_adds_u_b, |
| MSA128BOpnd>, IsCommutable; |
| class ADDS_U_H_DESC : MSA_3R_DESC_BASE<"adds_u.h", int_mips_adds_u_h, |
| MSA128HOpnd>, IsCommutable; |
| class ADDS_U_W_DESC : MSA_3R_DESC_BASE<"adds_u.w", int_mips_adds_u_w, |
| MSA128WOpnd>, IsCommutable; |
| class ADDS_U_D_DESC : MSA_3R_DESC_BASE<"adds_u.d", int_mips_adds_u_d, |
| MSA128DOpnd>, IsCommutable; |
| |
| class ADDV_B_DESC : MSA_3R_DESC_BASE<"addv.b", add, MSA128BOpnd>, IsCommutable; |
| class ADDV_H_DESC : MSA_3R_DESC_BASE<"addv.h", add, MSA128HOpnd>, IsCommutable; |
| class ADDV_W_DESC : MSA_3R_DESC_BASE<"addv.w", add, MSA128WOpnd>, IsCommutable; |
| class ADDV_D_DESC : MSA_3R_DESC_BASE<"addv.d", add, MSA128DOpnd>, IsCommutable; |
| |
| class ADDVI_B_DESC : MSA_I5_DESC_BASE<"addvi.b", add, vsplati8_uimm5, |
| MSA128BOpnd>; |
| class ADDVI_H_DESC : MSA_I5_DESC_BASE<"addvi.h", add, vsplati16_uimm5, |
| MSA128HOpnd>; |
| class ADDVI_W_DESC : MSA_I5_DESC_BASE<"addvi.w", add, vsplati32_uimm5, |
| MSA128WOpnd>; |
| class ADDVI_D_DESC : MSA_I5_DESC_BASE<"addvi.d", add, vsplati64_uimm5, |
| MSA128DOpnd>; |
| |
| class AND_V_DESC : MSA_VEC_DESC_BASE<"and.v", and, MSA128BOpnd>; |
| class AND_V_H_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128HOpnd>; |
| class AND_V_W_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128WOpnd>; |
| class AND_V_D_PSEUDO_DESC : MSA_VEC_PSEUDO_BASE<and, MSA128DOpnd>; |
| |
| class ANDI_B_DESC : MSA_I8_DESC_BASE<"andi.b", and, vsplati8_uimm8, |
| MSA128BOpnd>; |
| |
| class ASUB_S_B_DESC : MSA_3R_DESC_BASE<"asub_s.b", int_mips_asub_s_b, |
| MSA128BOpnd>; |
| class ASUB_S_H_DESC : MSA_3R_DESC_BASE<"asub_s.h", int_mips_asub_s_h, |
| MSA128HOpnd>; |
| class ASUB_S_W_DESC : MSA_3R_DESC_BASE<"asub_s.w", int_mips_asub_s_w, |
| MSA128WOpnd>; |
| class ASUB_S_D_DESC : MSA_3R_DESC_BASE<"asub_s.d", int_mips_asub_s_d, |
| MSA128DOpnd>; |
| |
| class ASUB_U_B_DESC : MSA_3R_DESC_BASE<"asub_u.b", int_mips_asub_u_b, |
| MSA128BOpnd>; |
| class ASUB_U_H_DESC : MSA_3R_DESC_BASE<"asub_u.h", int_mips_asub_u_h, |
| MSA128HOpnd>; |
| class ASUB_U_W_DESC : MSA_3R_DESC_BASE<"asub_u.w", int_mips_asub_u_w, |
| MSA128WOpnd>; |
| class ASUB_U_D_DESC : MSA_3R_DESC_BASE<"asub_u.d", int_mips_asub_u_d, |
| MSA128DOpnd>; |
| |
| class AVE_S_B_DESC : MSA_3R_DESC_BASE<"ave_s.b", int_mips_ave_s_b, MSA128BOpnd>, |
| IsCommutable; |
| class AVE_S_H_DESC : MSA_3R_DESC_BASE<"ave_s.h", int_mips_ave_s_h, MSA128HOpnd>, |
| IsCommutable; |
| class AVE_S_W_DESC : MSA_3R_DESC_BASE<"ave_s.w", int_mips_ave_s_w, MSA128WOpnd>, |
| IsCommutable; |
| class AVE_S_D_DESC : MSA_3R_DESC_BASE<"ave_s.d", int_mips_ave_s_d, MSA128DOpnd>, |
| IsCommutable; |
| |
| class AVE_U_B_DESC : MSA_3R_DESC_BASE<"ave_u.b", int_mips_ave_u_b, MSA128BOpnd>, |
| IsCommutable; |
| class AVE_U_H_DESC : MSA_3R_DESC_BASE<"ave_u.h", int_mips_ave_u_h, MSA128HOpnd>, |
| IsCommutable; |
| class AVE_U_W_DESC : MSA_3R_DESC_BASE<"ave_u.w", int_mips_ave_u_w, MSA128WOpnd>, |
| IsCommutable; |
| class AVE_U_D_DESC : MSA_3R_DESC_BASE<"ave_u.d", int_mips_ave_u_d, MSA128DOpnd>, |
| IsCommutable; |
| |
| class AVER_S_B_DESC : MSA_3R_DESC_BASE<"aver_s.b", int_mips_aver_s_b, |
| MSA128BOpnd>, IsCommutable; |
| class AVER_S_H_DESC : MSA_3R_DESC_BASE<"aver_s.h", int_mips_aver_s_h, |
| MSA128HOpnd>, IsCommutable; |
| class AVER_S_W_DESC : MSA_3R_DESC_BASE<"aver_s.w", int_mips_aver_s_w, |
| MSA128WOpnd>, IsCommutable; |
| class AVER_S_D_DESC : MSA_3R_DESC_BASE<"aver_s.d", int_mips_aver_s_d, |
| MSA128DOpnd>, IsCommutable; |
| |
| class AVER_U_B_DESC : MSA_3R_DESC_BASE<"aver_u.b", int_mips_aver_u_b, |
| MSA128BOpnd>, IsCommutable; |
| class AVER_U_H_DESC : MSA_3R_DESC_BASE<"aver_u.h", int_mips_aver_u_h, |
| MSA128HOpnd>, IsCommutable; |
| class AVER_U_W_DESC : MSA_3R_DESC_BASE<"aver_u.w", int_mips_aver_u_w, |
| MSA128WOpnd>, IsCommutable; |
| class AVER_U_D_DESC : MSA_3R_DESC_BASE<"aver_u.d", int_mips_aver_u_d, |
| MSA128DOpnd>, IsCommutable; |
| |
| class BCLR_B_DESC : MSA_3R_DESC_BASE<"bclr.b", vbclr_b, MSA128BOpnd>; |
| class BCLR_H_DESC : MSA_3R_DESC_BASE<"bclr.h", vbclr_h, MSA128HOpnd>; |
| class BCLR_W_DESC : MSA_3R_DESC_BASE<"bclr.w", vbclr_w, MSA128WOpnd>; |
| class BCLR_D_DESC : MSA_3R_DESC_BASE<"bclr.d", vbclr_d, MSA128DOpnd>; |
| |
| class BCLRI_B_DESC : MSA_BIT_B_DESC_BASE<"bclri.b", and, vsplat_uimm_inv_pow2, |
| MSA128BOpnd>; |
| class BCLRI_H_DESC : MSA_BIT_H_DESC_BASE<"bclri.h", and, vsplat_uimm_inv_pow2, |
| MSA128HOpnd>; |
| class BCLRI_W_DESC : MSA_BIT_W_DESC_BASE<"bclri.w", and, vsplat_uimm_inv_pow2, |
| MSA128WOpnd>; |
| class BCLRI_D_DESC : MSA_BIT_D_DESC_BASE<"bclri.d", and, vsplat_uimm_inv_pow2, |
| MSA128DOpnd>; |
| |
| class BINSL_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.b", int_mips_binsl_b, |
| MSA128BOpnd>; |
| class BINSL_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.h", int_mips_binsl_h, |
| MSA128HOpnd>; |
| class BINSL_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.w", int_mips_binsl_w, |
| MSA128WOpnd>; |
| class BINSL_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsl.d", int_mips_binsl_d, |
| MSA128DOpnd>; |
| |
| class BINSLI_B_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.b", v16i8, vsplat_maskl_bits_uimm3, MSA128BOpnd>; |
| class BINSLI_H_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.h", v8i16, vsplat_maskl_bits_uimm4, MSA128HOpnd>; |
| class BINSLI_W_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.w", v4i32, vsplat_maskl_bits_uimm5, MSA128WOpnd>; |
| class BINSLI_D_DESC : MSA_BIT_BINSLI_DESC_BASE<"binsli.d", v2i64, vsplat_maskl_bits_uimm6, MSA128DOpnd>; |
| |
| class BINSR_B_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.b", int_mips_binsr_b, |
| MSA128BOpnd>; |
| class BINSR_H_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.h", int_mips_binsr_h, |
| MSA128HOpnd>; |
| class BINSR_W_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.w", int_mips_binsr_w, |
| MSA128WOpnd>; |
| class BINSR_D_DESC : MSA_3R_BINSX_DESC_BASE<"binsr.d", int_mips_binsr_d, |
| MSA128DOpnd>; |
| |
| class BINSRI_B_DESC |
| : MSA_BIT_BINSRI_DESC_BASE<"binsri.b", v16i8, vsplat_maskr_bits_uimm3, |
| MSA128BOpnd>; |
| class BINSRI_H_DESC |
| : MSA_BIT_BINSRI_DESC_BASE<"binsri.h", v8i16, vsplat_maskr_bits_uimm4, |
| MSA128HOpnd>; |
| class BINSRI_W_DESC |
| : MSA_BIT_BINSRI_DESC_BASE<"binsri.w", v4i32, vsplat_maskr_bits_uimm5, |
| MSA128WOpnd>; |
| class BINSRI_D_DESC |
| : MSA_BIT_BINSRI_DESC_BASE<"binsri.d", v2i64, vsplat_maskr_bits_uimm6, |
| MSA128DOpnd>; |
| |
| class BMNZ_V_DESC { |
| dag OutOperandList = (outs MSA128BOpnd:$wd); |
| dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, |
| MSA128BOpnd:$wt); |
| string AsmString = "bmnz.v\t$wd, $ws, $wt"; |
| list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, |
| MSA128BOpnd:$ws, |
| MSA128BOpnd:$wd_in))]; |
| InstrItinClass Itinerary = NoItinerary; |
| string Constraints = "$wd = $wd_in"; |
| } |
| |
| class BMNZI_B_DESC { |
| dag OutOperandList = (outs MSA128BOpnd:$wd); |
| dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, |
| vsplat_uimm8:$u8); |
| string AsmString = "bmnzi.b\t$wd, $ws, $u8"; |
| list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, |
| MSA128BOpnd:$ws, |
| MSA128BOpnd:$wd_in))]; |
| InstrItinClass Itinerary = NoItinerary; |
| string Constraints = "$wd = $wd_in"; |
| } |
| |
| class BMZ_V_DESC { |
| dag OutOperandList = (outs MSA128BOpnd:$wd); |
| dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, |
| MSA128BOpnd:$wt); |
| string AsmString = "bmz.v\t$wd, $ws, $wt"; |
| list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wt, |
| MSA128BOpnd:$wd_in, |
| MSA128BOpnd:$ws))]; |
| InstrItinClass Itinerary = NoItinerary; |
| string Constraints = "$wd = $wd_in"; |
| } |
| |
| class BMZI_B_DESC { |
| dag OutOperandList = (outs MSA128BOpnd:$wd); |
| dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, |
| vsplat_uimm8:$u8); |
| string AsmString = "bmzi.b\t$wd, $ws, $u8"; |
| list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect vsplati8_uimm8:$u8, |
| MSA128BOpnd:$wd_in, |
| MSA128BOpnd:$ws))]; |
| InstrItinClass Itinerary = NoItinerary; |
| string Constraints = "$wd = $wd_in"; |
| } |
| |
| class BNEG_B_DESC : MSA_3R_DESC_BASE<"bneg.b", vbneg_b, MSA128BOpnd>; |
| class BNEG_H_DESC : MSA_3R_DESC_BASE<"bneg.h", vbneg_h, MSA128HOpnd>; |
| class BNEG_W_DESC : MSA_3R_DESC_BASE<"bneg.w", vbneg_w, MSA128WOpnd>; |
| class BNEG_D_DESC : MSA_3R_DESC_BASE<"bneg.d", vbneg_d, MSA128DOpnd>; |
| |
| class BNEGI_B_DESC : MSA_BIT_B_DESC_BASE<"bnegi.b", xor, vsplat_uimm_pow2, |
| MSA128BOpnd>; |
| class BNEGI_H_DESC : MSA_BIT_H_DESC_BASE<"bnegi.h", xor, vsplat_uimm_pow2, |
| MSA128HOpnd>; |
| class BNEGI_W_DESC : MSA_BIT_W_DESC_BASE<"bnegi.w", xor, vsplat_uimm_pow2, |
| MSA128WOpnd>; |
| class BNEGI_D_DESC : MSA_BIT_D_DESC_BASE<"bnegi.d", xor, vsplat_uimm_pow2, |
| MSA128DOpnd>; |
| |
| class BNZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bnz.b", MSA128BOpnd>; |
| class BNZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bnz.h", MSA128HOpnd>; |
| class BNZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bnz.w", MSA128WOpnd>; |
| class BNZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bnz.d", MSA128DOpnd>; |
| |
| class BNZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bnz.v", MSA128BOpnd>; |
| |
| class BSEL_V_DESC { |
| dag OutOperandList = (outs MSA128BOpnd:$wd); |
| dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, |
| MSA128BOpnd:$wt); |
| string AsmString = "bsel.v\t$wd, $ws, $wt"; |
| // Note that vselect and BSEL_V treat the condition operand the opposite way |
| // from each other. |
| // (vselect cond, if_set, if_clear) |
| // (BSEL_V cond, if_clear, if_set) |
| list<dag> Pattern = [(set MSA128BOpnd:$wd, |
| (vselect MSA128BOpnd:$wd_in, MSA128BOpnd:$wt, |
| MSA128BOpnd:$ws))]; |
| InstrItinClass Itinerary = NoItinerary; |
| string Constraints = "$wd = $wd_in"; |
| } |
| |
| class BSELI_B_DESC { |
| dag OutOperandList = (outs MSA128BOpnd:$wd); |
| dag InOperandList = (ins MSA128BOpnd:$wd_in, MSA128BOpnd:$ws, |
| vsplat_uimm8:$u8); |
| string AsmString = "bseli.b\t$wd, $ws, $u8"; |
| // Note that vselect and BSEL_V treat the condition operand the opposite way |
| // from each other. |
| // (vselect cond, if_set, if_clear) |
| // (BSEL_V cond, if_clear, if_set) |
| list<dag> Pattern = [(set MSA128BOpnd:$wd, (vselect MSA128BOpnd:$wd_in, |
| vsplati8_uimm8:$u8, |
| MSA128BOpnd:$ws))]; |
| InstrItinClass Itinerary = NoItinerary; |
| string Constraints = "$wd = $wd_in"; |
| } |
| |
| class BSET_B_DESC : MSA_3R_DESC_BASE<"bset.b", vbset_b, MSA128BOpnd>; |
| class BSET_H_DESC : MSA_3R_DESC_BASE<"bset.h", vbset_h, MSA128HOpnd>; |
| class BSET_W_DESC : MSA_3R_DESC_BASE<"bset.w", vbset_w, MSA128WOpnd>; |
| class BSET_D_DESC : MSA_3R_DESC_BASE<"bset.d", vbset_d, MSA128DOpnd>; |
| |
| class BSETI_B_DESC : MSA_BIT_B_DESC_BASE<"bseti.b", or, vsplat_uimm_pow2, |
| MSA128BOpnd>; |
| class BSETI_H_DESC : MSA_BIT_H_DESC_BASE<"bseti.h", or, vsplat_uimm_pow2, |
| MSA128HOpnd>; |
| class BSETI_W_DESC : MSA_BIT_W_DESC_BASE<"bseti.w", or, vsplat_uimm_pow2, |
| MSA128WOpnd>; |
| class BSETI_D_DESC : MSA_BIT_D_DESC_BASE<"bseti.d", or, vsplat_uimm_pow2, |
| MSA128DOpnd>; |
| |
| class BZ_B_DESC : MSA_CBRANCH_DESC_BASE<"bz.b", MSA128BOpnd>; |
| class BZ_H_DESC : MSA_CBRANCH_DESC_BASE<"bz.h", MSA128HOpnd>; |
| class BZ_W_DESC : MSA_CBRANCH_DESC_BASE<"bz.w", MSA128WOpnd>; |
| class BZ_D_DESC : MSA_CBRANCH_DESC_BASE<"bz.d", MSA128DOpnd>; |
| |
| class BZ_V_DESC : MSA_CBRANCH_DESC_BASE<"bz.v", MSA128BOpnd>; |
| |
| class CEQ_B_DESC : MSA_3R_DESC_BASE<"ceq.b", vseteq_v16i8, MSA128BOpnd>, |
| IsCommutable; |
| class CEQ_H_DESC : MSA_3R_DESC_BASE<"ceq.h", vseteq_v8i16, MSA128HOpnd>, |
| IsCommutable; |
| class CEQ_W_DESC : MSA_3R_DESC_BASE<"ceq.w", vseteq_v4i32, MSA128WOpnd>, |
| IsCommutable; |
| class CEQ_D_DESC : MSA_3R_DESC_BASE<"ceq.d", vseteq_v2i64, MSA128DOpnd>, |
| IsCommutable; |
| |
| class CEQI_B_DESC : MSA_I5_DESC_BASE<"ceqi.b", vseteq_v16i8, vsplati8_simm5, |
| MSA128BOpnd>; |
| class CEQI_H_DESC : MSA_I5_DESC_BASE<"ceqi.h", vseteq_v8i16, vsplati16_simm5, |
| MSA128HOpnd>; |
| class CEQI_W_DESC : MSA_I5_DESC_BASE<"ceqi.w", vseteq_v4i32, vsplati32_simm5, |
| MSA128WOpnd>; |
| class CEQI_D_DESC : MSA_I5_DESC_BASE<"ceqi.d", vseteq_v2i64, vsplati64_simm5, |
| MSA128DOpnd>; |
| |
| class CFCMSA_DESC { |
| dag OutOperandList = (outs GPR32Opnd:$rd); |
| dag InOperandList = (ins MSA128CROpnd:$cs); |
| string AsmString = "cfcmsa\t$rd, $cs"; |
| InstrItinClass Itinerary = NoItinerary; |
| bit hasSideEffects = 1; |
| bit isMoveReg = 1; |
| } |
| |
| class CLE_S_B_DESC : MSA_3R_DESC_BASE<"cle_s.b", vsetle_v16i8, MSA128BOpnd>; |
| class CLE_S_H_DESC : MSA_3R_DESC_BASE<"cle_s.h", vsetle_v8i16, MSA128HOpnd>; |
| class CLE_S_W_DESC : MSA_3R_DESC_BASE<"cle_s.w", vsetle_v4i32, MSA128WOpnd>; |
| class CLE_S_D_DESC : MSA_3R_DESC_BASE<"cle_s.d", vsetle_v2i64, MSA128DOpnd>; |
| |
| class CLE_U_B_DESC : MSA_3R_DESC_BASE<"cle_u.b", vsetule_v16i8, MSA128BOpnd>; |
| class CLE_U_H_DESC : MSA_3R_DESC_BASE<"cle_u.h", vsetule_v8i16, MSA128HOpnd>; |
| class CLE_U_W_DESC : MSA_3R_DESC_BASE<"cle_u.w", vsetule_v4i32, MSA128WOpnd>; |
| class CLE_U_D_DESC : MSA_3R_DESC_BASE<"cle_u.d", vsetule_v2i64, MSA128DOpnd>; |
| |
| class CLEI_S_B_DESC : MSA_I5_DESC_BASE<"clei_s.b", vsetle_v16i8, |
| vsplati8_simm5, MSA128BOpnd>; |
| class CLEI_S_H_DESC : MSA_I5_DESC_BASE<"clei_s.h", vsetle_v8i16, |
| vsplati16_simm5, MSA128HOpnd>; |
| class CLEI_S_W_DESC : MSA_I5_DESC_BASE<"clei_s.w", vsetle_v4i32, |
| vsplati32_simm5, MSA128WOpnd>; |
| class CLEI_S_D_DESC : MSA_I5_DESC_BASE<"clei_s.d", vsetle_v2i64, |
| vsplati64_simm5, MSA128DOpnd>; |
| |
| class CLEI_U_B_DESC : MSA_I5_DESC_BASE<"clei_u.b", vsetule_v16i8, |
| vsplati8_uimm5, MSA128BOpnd>; |
| class CLEI_U_H_DESC : MSA_I5_DESC_BASE<"clei_u.h", vsetule_v8i16, |
| vsplati16_uimm5, MSA128HOpnd>; |
| class CLEI_U_W_DESC : MSA_I5_DESC_BASE<"clei_u.w", vsetule_v4i32, |
| vsplati32_uimm5, MSA128WOpnd>; |
| class CLEI_U_D_DESC : MSA_I5_DESC_BASE<"clei_u.d", vsetule_v2i64, |
| vsplati64_uimm5, MSA128DOpnd>; |
| |
| class CLT_S_B_DESC : MSA_3R_DESC_BASE<"clt_s.b", vsetlt_v16i8, MSA128BOpnd>; |
| class CLT_S_H_DESC : MSA_3R_DESC_BASE<"clt_s.h", vsetlt_v8i16, MSA128HOpnd>; |
| class CLT_S_W_DESC : MSA_3R_DESC_BASE<"clt_s.w", vsetlt_v4i32, MSA128WOpnd>; |
| class CLT_S_D_DESC : MSA_3R_DESC_BASE<"clt_s.d", vsetlt_v2i64, MSA128DOpnd>; |
| |
| class CLT_U_B_DESC : MSA_3R_DESC_BASE<"clt_u.b", vsetult_v16i8, MSA128BOpnd>; |
| class CLT_U_H_DESC : MSA_3R_DESC_BASE<"clt_u.h", vsetult_v8i16, MSA128HOpnd>; |
| class CLT_U_W_DESC : MSA_3R_DESC_BASE<"clt_u.w", vsetult_v4i32, MSA128WOpnd>; |
| class CLT_U_D_DESC : MSA_3R_DESC_BASE<"clt_u.d", vsetult_v2i64, MSA128DOpnd>; |
| |
| class CLTI_S_B_DESC : MSA_I5_DESC_BASE<"clti_s.b", vsetlt_v16i8, |
| vsplati8_simm5, MSA128BOpnd>; |
| class CLTI_S_H_DESC : MSA_I5_DESC_BASE<"clti_s.h", vsetlt_v8i16, |
| vsplati16_simm5, MSA128HOpnd>; |
| class CLTI_S_W_DESC : MSA_I5_DESC_BASE<"clti_s.w", vsetlt_v4i32, |
| vsplati32_simm5, MSA128WOpnd>; |
| class CLTI_S_D_DESC : MSA_I5_DESC_BASE<"clti_s.d", vsetlt_v2i64, |
| vsplati64_simm5, MSA128DOpnd>; |
| |
| class CLTI_U_B_DESC : MSA_I5_DESC_BASE<"clti_u.b", vsetult_v16i8, |
| vsplati8_uimm5, MSA128BOpnd>; |
| class CLTI_U_H_DESC : MSA_I5_DESC_BASE<"clti_u.h", vsetult_v8i16, |
| vsplati16_uimm5, MSA128HOpnd>; |
| class CLTI_U_W_DESC : MSA_I5_DESC_BASE<"clti_u.w", vsetult_v4i32, |
| vsplati32_uimm5, MSA128WOpnd>; |
| class CLTI_U_D_DESC : MSA_I5_DESC_BASE<"clti_u.d", vsetult_v2i64, |
| vsplati64_uimm5, MSA128DOpnd>; |
| |
| class COPY_S_B_DESC : MSA_COPY_DESC_BASE<"copy_s.b", vextract_sext_i8, v16i8, |
| uimm4_ptr, immZExt4Ptr, GPR32Opnd, |
| MSA128BOpnd>; |
| class COPY_S_H_DESC : MSA_COPY_DESC_BASE<"copy_s.h", vextract_sext_i16, v8i16, |
| uimm3_ptr, immZExt3Ptr, GPR32Opnd, |
| MSA128HOpnd>; |
| class COPY_S_W_DESC : MSA_COPY_DESC_BASE<"copy_s.w", vextract_sext_i32, v4i32, |
| uimm2_ptr, immZExt2Ptr, GPR32Opnd, |
| MSA128WOpnd>; |
| class COPY_S_D_DESC : MSA_COPY_DESC_BASE<"copy_s.d", vextract_sext_i64, v2i64, |
| uimm1_ptr, immZExt1Ptr, GPR64Opnd, |
| MSA128DOpnd>; |
| |
| class COPY_U_B_DESC : MSA_COPY_DESC_BASE<"copy_u.b", vextract_zext_i8, v16i8, |
| uimm4_ptr, immZExt4Ptr, GPR32Opnd, |
| MSA128BOpnd>; |
| class COPY_U_H_DESC : MSA_COPY_DESC_BASE<"copy_u.h", vextract_zext_i16, v8i16, |
| uimm3_ptr, immZExt3Ptr, GPR32Opnd, |
| MSA128HOpnd>; |
| class COPY_U_W_DESC : MSA_COPY_DESC_BASE<"copy_u.w", vextract_zext_i32, v4i32, |
| uimm2_ptr, immZExt2Ptr, GPR32Opnd, |
| MSA128WOpnd>; |
| |
| class COPY_FW_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v4f32, |
| uimm2_ptr, immZExt2Ptr, FGR32, |
| MSA128W>; |
| class COPY_FD_PSEUDO_DESC : MSA_COPY_PSEUDO_BASE<vector_extract, v2f64, |
| uimm1_ptr, immZExt1Ptr, FGR64, |
| MSA128D>; |
| |
| class CTCMSA_DESC { |
| dag OutOperandList = (outs); |
| dag InOperandList = (ins MSA128CROpnd:$cd, GPR32Opnd:$rs); |
| string AsmString = "ctcmsa\t$cd, $rs"; |
| InstrItinClass Itinerary = NoItinerary; |
| bit hasSideEffects = 1; |
| bit isMoveReg = 1; |
| } |
| |
| class DIV_S_B_DESC : MSA_3R_DESC_BASE<"div_s.b", sdiv, MSA128BOpnd>; |
| class DIV_S_H_DESC : MSA_3R_DESC_BASE<"div_s.h", sdiv, MSA128HOpnd>; |
| class DIV_S_W_DESC : MSA_3R_DESC_BASE<"div_s.w", sdiv, MSA128WOpnd>; |
| class DIV_S_D_DESC : MSA_3R_DESC_BASE<"div_s.d", sdiv, MSA128DOpnd>; |
| |
| class DIV_U_B_DESC : MSA_3R_DESC_BASE<"div_u.b", udiv, MSA128BOpnd>; |
| class DIV_U_H_DESC : MSA_3R_DESC_BASE<"div_u.h", udiv, MSA128HOpnd>; |
| class DIV_U_W_DESC : MSA_3R_DESC_BASE<"div_u.w", udiv, MSA128WOpnd>; |
| class DIV_U_D_DESC : MSA_3R_DESC_BASE<"div_u.d", udiv, MSA128DOpnd>; |
| |
| class DOTP_S_H_DESC : MSA_3R_DESC_BASE<"dotp_s.h", int_mips_dotp_s_h, |
| MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, |
| IsCommutable; |
| class DOTP_S_W_DESC : MSA_3R_DESC_BASE<"dotp_s.w", int_mips_dotp_s_w, |
| MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, |
| IsCommutable; |
| class DOTP_S_D_DESC : MSA_3R_DESC_BASE<"dotp_s.d", int_mips_dotp_s_d, |
| MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, |
| IsCommutable; |
| |
| class DOTP_U_H_DESC : MSA_3R_DESC_BASE<"dotp_u.h", int_mips_dotp_u_h, |
| MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>, |
| IsCommutable; |
| class DOTP_U_W_DESC : MSA_3R_DESC_BASE<"dotp_u.w", int_mips_dotp_u_w, |
| MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>, |
| IsCommutable; |
| class DOTP_U_D_DESC : MSA_3R_DESC_BASE<"dotp_u.d", int_mips_dotp_u_d, |
| MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>, |
| IsCommutable; |
| |
| class DPADD_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.h", int_mips_dpadd_s_h, |
| MSA128HOpnd, MSA128BOpnd, |
| MSA128BOpnd>, IsCommutable; |
| class DPADD_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.w", int_mips_dpadd_s_w, |
| MSA128WOpnd, MSA128HOpnd, |
| MSA128HOpnd>, IsCommutable; |
| class DPADD_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_s.d", int_mips_dpadd_s_d, |
| MSA128DOpnd, MSA128WOpnd, |
| MSA128WOpnd>, IsCommutable; |
| |
| class DPADD_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.h", int_mips_dpadd_u_h, |
| MSA128HOpnd, MSA128BOpnd, |
| MSA128BOpnd>, IsCommutable; |
| class DPADD_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.w", int_mips_dpadd_u_w, |
| MSA128WOpnd, MSA128HOpnd, |
| MSA128HOpnd>, IsCommutable; |
| class DPADD_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpadd_u.d", int_mips_dpadd_u_d, |
| MSA128DOpnd, MSA128WOpnd, |
| MSA128WOpnd>, IsCommutable; |
| |
| class DPSUB_S_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.h", int_mips_dpsub_s_h, |
| MSA128HOpnd, MSA128BOpnd, |
| MSA128BOpnd>; |
| class DPSUB_S_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.w", int_mips_dpsub_s_w, |
| MSA128WOpnd, MSA128HOpnd, |
| MSA128HOpnd>; |
| class DPSUB_S_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_s.d", int_mips_dpsub_s_d, |
| MSA128DOpnd, MSA128WOpnd, |
| MSA128WOpnd>; |
| |
| class DPSUB_U_H_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.h", int_mips_dpsub_u_h, |
| MSA128HOpnd, MSA128BOpnd, |
| MSA128BOpnd>; |
| class DPSUB_U_W_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.w", int_mips_dpsub_u_w, |
| MSA128WOpnd, MSA128HOpnd, |
| MSA128HOpnd>; |
| class DPSUB_U_D_DESC : MSA_3R_4R_DESC_BASE<"dpsub_u.d", int_mips_dpsub_u_d, |
| MSA128DOpnd, MSA128WOpnd, |
| MSA128WOpnd>; |
| |
| class FADD_W_DESC : MSA_3RF_DESC_BASE<"fadd.w", fadd, MSA128WOpnd>, |
| IsCommutable; |
| class FADD_D_DESC : MSA_3RF_DESC_BASE<"fadd.d", fadd, MSA128DOpnd>, |
| IsCommutable; |
| |
| class FCAF_W_DESC : MSA_3RF_DESC_BASE<"fcaf.w", int_mips_fcaf_w, MSA128WOpnd>, |
| IsCommutable; |
| class FCAF_D_DESC : MSA_3RF_DESC_BASE<"fcaf.d", int_mips_fcaf_d, MSA128DOpnd>, |
| IsCommutable; |
| |
| class FCEQ_W_DESC : MSA_3RF_DESC_BASE<"fceq.w", vfsetoeq_v4f32, MSA128WOpnd>, |
| IsCommutable; |
| class FCEQ_D_DESC : MSA_3RF_DESC_BASE<"fceq.d", vfsetoeq_v2f64, MSA128DOpnd>, |
| IsCommutable; |
| |
| class FCLASS_W_DESC : MSA_2RF_DESC_BASE<"fclass.w", int_mips_fclass_w, |
| MSA128WOpnd>; |
| class FCLASS_D_DESC : MSA_2RF_DESC_BASE<"fclass.d", int_mips_fclass_d, |
| MSA128DOpnd>; |
| |
| class FCLE_W_DESC : MSA_3RF_DESC_BASE<"fcle.w", vfsetole_v4f32, MSA128WOpnd>; |
| class FCLE_D_DESC : MSA_3RF_DESC_BASE<"fcle.d", vfsetole_v2f64, MSA128DOpnd>; |
| |
| class FCLT_W_DESC : MSA_3RF_DESC_BASE<"fclt.w", vfsetolt_v4f32, MSA128WOpnd>; |
| class FCLT_D_DESC : MSA_3RF_DESC_BASE<"fclt.d", vfsetolt_v2f64, MSA128DOpnd>; |
| |
| class FCNE_W_DESC : MSA_3RF_DESC_BASE<"fcne.w", vfsetone_v4f32, MSA128WOpnd>, |
| IsCommutable; |
| class FCNE_D_DESC : MSA_3RF_DESC_BASE<"fcne.d", vfsetone_v2f64, MSA128DOpnd>, |
| IsCommutable; |
| |
| class FCOR_W_DESC : MSA_3RF_DESC_BASE<"fcor.w", vfsetord_v4f32, MSA128WOpnd>, |
| IsCommutable; |
| class FCOR_D_DESC : MSA_3RF_DESC_BASE<"fcor.d", vfsetord_v2f64, MSA128DOpnd>, |
| IsCommutable; |
| |
| class FCUEQ_W_DESC : MSA_3RF_DESC_BASE<"fcueq.w", vfsetueq_v4f32, MSA128WOpnd>, |
| IsCommutable; |
| class FCUEQ_D_DESC : MSA_3RF_DESC_BASE<"fcueq.d", vfsetueq_v2f64, MSA128DOpnd>, |
| IsCommutable; |
| |
| class FCULE_W_DESC : MSA_3RF_DESC_BASE<"fcule.w", vfsetule_v4f32, MSA128WOpnd>, |
| IsCommutable; |
| class FCULE_D_DESC : MSA_3RF_DESC_BASE<"fcule.d", vfsetule_v2f64, MSA128DOpnd>, |
| IsCommutable; |
| |
| class FCULT_W_DESC : MSA_3RF_DESC_BASE<"fcult.w", vfsetult_v4f32, MSA128WOpnd>, |
| IsCommutable; |
| class FCULT_D_DESC : MSA_3RF_DESC_BASE<"fcult.d", vfsetult_v2f64, MSA128DOpnd>, |
| IsCommutable; |
| |
| class FCUN_W_DESC : MSA_3RF_DESC_BASE<"fcun.w", vfsetun_v4f32, MSA128WOpnd>, |
| IsCommutable; |
| class FCUN_D_DESC : MSA_3RF_DESC_BASE<"fcun.d", vfsetun_v2f64, MSA128DOpnd>, |
| IsCommutable; |
| |
| class FCUNE_W_DESC : MSA_3RF_DESC_BASE<"fcune.w", vfsetune_v4f32, MSA128WOpnd>, |
| IsCommutable; |
| class FCUNE_D_DESC : MSA_3RF_DESC_BASE<"fcune.d", vfsetune_v2f64, MSA128DOpnd>, |
| IsCommutable; |
| |
| class FDIV_W_DESC : MSA_3RF_DESC_BASE<"fdiv.w", fdiv, MSA128WOpnd>; |
| class FDIV_D_DESC : MSA_3RF_DESC_BASE<"fdiv.d", fdiv, MSA128DOpnd>; |
| |
| class FEXDO_H_DESC : MSA_3RF_DESC_BASE<"fexdo.h", int_mips_fexdo_h, |
| MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; |
| class FEXDO_W_DESC : MSA_3RF_DESC_BASE<"fexdo.w", int_mips_fexdo_w, |
| MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; |
| |
| // The fexp2.df instruction multiplies the first operand by 2 to the power of |
| // the second operand. We therefore need a pseudo-insn in order to invent the |
| // 1.0 when we only need to match ISD::FEXP2. |
| class FEXP2_W_DESC : MSA_3RF_DESC_BASE<"fexp2.w", mul_fexp2, MSA128WOpnd>; |
| class FEXP2_D_DESC : MSA_3RF_DESC_BASE<"fexp2.d", mul_fexp2, MSA128DOpnd>; |
| let usesCustomInserter = 1, hasNoSchedulingInfo = 1 in { |
| class FEXP2_W_1_PSEUDO_DESC : |
| MSAPseudo<(outs MSA128W:$wd), (ins MSA128W:$ws), |
| [(set MSA128W:$wd, (fexp2 MSA128W:$ws))]>; |
| class FEXP2_D_1_PSEUDO_DESC : |
| MSAPseudo<(outs MSA128D:$wd), (ins MSA128D:$ws), |
| [(set MSA128D:$wd, (fexp2 MSA128D:$ws))]>; |
| } |
| |
| class FEXUPL_W_DESC : MSA_2RF_DESC_BASE<"fexupl.w", int_mips_fexupl_w, |
| MSA128WOpnd, MSA128HOpnd>; |
| class FEXUPL_D_DESC : MSA_2RF_DESC_BASE<"fexupl.d", int_mips_fexupl_d, |
| MSA128DOpnd, MSA128WOpnd>; |
| |
| class FEXUPR_W_DESC : MSA_2RF_DESC_BASE<"fexupr.w", int_mips_fexupr_w, |
| MSA128WOpnd, MSA128HOpnd>; |
| class FEXUPR_D_DESC : MSA_2RF_DESC_BASE<"fexupr.d", int_mips_fexupr_d, |
| MSA128DOpnd, MSA128WOpnd>; |
| |
| class FFINT_S_W_DESC : MSA_2RF_DESC_BASE<"ffint_s.w", sint_to_fp, MSA128WOpnd>; |
| class FFINT_S_D_DESC : MSA_2RF_DESC_BASE<"ffint_s.d", sint_to_fp, MSA128DOpnd>; |
| |
| class FFINT_U_W_DESC : MSA_2RF_DESC_BASE<"ffint_u.w", uint_to_fp, MSA128WOpnd>; |
| class FFINT_U_D_DESC : MSA_2RF_DESC_BASE<"ffint_u.d", uint_to_fp, MSA128DOpnd>; |
| |
| class FFQL_W_DESC : MSA_2RF_DESC_BASE<"ffql.w", int_mips_ffql_w, |
| MSA128WOpnd, MSA128HOpnd>; |
| class FFQL_D_DESC : MSA_2RF_DESC_BASE<"ffql.d", int_mips_ffql_d, |
| MSA128DOpnd, MSA128WOpnd>; |
| |
| class FFQR_W_DESC : MSA_2RF_DESC_BASE<"ffqr.w", int_mips_ffqr_w, |
| MSA128WOpnd, MSA128HOpnd>; |
| class FFQR_D_DESC : MSA_2RF_DESC_BASE<"ffqr.d", int_mips_ffqr_d, |
| MSA128DOpnd, MSA128WOpnd>; |
| |
| class FILL_B_DESC : MSA_2R_FILL_DESC_BASE<"fill.b", v16i8, vsplati8, |
| MSA128BOpnd, GPR32Opnd>; |
| class FILL_H_DESC : MSA_2R_FILL_DESC_BASE<"fill.h", v8i16, vsplati16, |
| MSA128HOpnd, GPR32Opnd>; |
| class FILL_W_DESC : MSA_2R_FILL_DESC_BASE<"fill.w", v4i32, vsplati32, |
| MSA128WOpnd, GPR32Opnd>; |
| class FILL_D_DESC : MSA_2R_FILL_DESC_BASE<"fill.d", v2i64, vsplati64, |
| MSA128DOpnd, GPR64Opnd>; |
| |
| class FILL_FW_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<vsplatf32, MSA128W, FGR32>; |
| class FILL_FD_PSEUDO_DESC : MSA_2R_FILL_PSEUDO_BASE<vsplatf64, MSA128D, FGR64>; |
| |
| class FLOG2_W_DESC : MSA_2RF_DESC_BASE<"flog2.w", flog2, MSA128WOpnd>; |
| class FLOG2_D_DESC : MSA_2RF_DESC_BASE<"flog2.d", flog2, MSA128DOpnd>; |
| |
| class FMADD_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.w", fma, MSA128WOpnd>; |
| class FMADD_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmadd.d", fma, MSA128DOpnd>; |
| |
| class FMAX_W_DESC : MSA_3RF_DESC_BASE<"fmax.w", int_mips_fmax_w, MSA128WOpnd>; |
| class FMAX_D_DESC : MSA_3RF_DESC_BASE<"fmax.d", int_mips_fmax_d, MSA128DOpnd>; |
| |
| class FMAX_A_W_DESC : MSA_3RF_DESC_BASE<"fmax_a.w", int_mips_fmax_a_w, |
| MSA128WOpnd>; |
| class FMAX_A_D_DESC : MSA_3RF_DESC_BASE<"fmax_a.d", int_mips_fmax_a_d, |
| MSA128DOpnd>; |
| |
| class FMIN_W_DESC : MSA_3RF_DESC_BASE<"fmin.w", int_mips_fmin_w, MSA128WOpnd>; |
| class FMIN_D_DESC : MSA_3RF_DESC_BASE<"fmin.d", int_mips_fmin_d, MSA128DOpnd>; |
| |
| class FMIN_A_W_DESC : MSA_3RF_DESC_BASE<"fmin_a.w", int_mips_fmin_a_w, |
| MSA128WOpnd>; |
| class FMIN_A_D_DESC : MSA_3RF_DESC_BASE<"fmin_a.d", int_mips_fmin_a_d, |
| MSA128DOpnd>; |
| |
| class FMSUB_W_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.w", MipsFMS, MSA128WOpnd>; |
| class FMSUB_D_DESC : MSA_3RF_4RF_DESC_BASE<"fmsub.d", MipsFMS, MSA128DOpnd>; |
| |
| class FMUL_W_DESC : MSA_3RF_DESC_BASE<"fmul.w", fmul, MSA128WOpnd>; |
| class FMUL_D_DESC : MSA_3RF_DESC_BASE<"fmul.d", fmul, MSA128DOpnd>; |
| |
| class FRINT_W_DESC : MSA_2RF_DESC_BASE<"frint.w", frint, MSA128WOpnd>; |
| class FRINT_D_DESC : MSA_2RF_DESC_BASE<"frint.d", frint, MSA128DOpnd>; |
| |
| class FRCP_W_DESC : MSA_2RF_DESC_BASE<"frcp.w", int_mips_frcp_w, MSA128WOpnd>; |
| class FRCP_D_DESC : MSA_2RF_DESC_BASE<"frcp.d", int_mips_frcp_d, MSA128DOpnd>; |
| |
| class FRSQRT_W_DESC : MSA_2RF_DESC_BASE<"frsqrt.w", int_mips_frsqrt_w, |
| MSA128WOpnd>; |
| class FRSQRT_D_DESC : MSA_2RF_DESC_BASE<"frsqrt.d", int_mips_frsqrt_d, |
| MSA128DOpnd>; |
| |
| class FSAF_W_DESC : MSA_3RF_DESC_BASE<"fsaf.w", int_mips_fsaf_w, MSA128WOpnd>; |
| class FSAF_D_DESC : MSA_3RF_DESC_BASE<"fsaf.d", int_mips_fsaf_d, MSA128DOpnd>; |
| |
| class FSEQ_W_DESC : MSA_3RF_DESC_BASE<"fseq.w", int_mips_fseq_w, MSA128WOpnd>; |
| class FSEQ_D_DESC : MSA_3RF_DESC_BASE<"fseq.d", int_mips_fseq_d, MSA128DOpnd>; |
| |
| class FSLE_W_DESC : MSA_3RF_DESC_BASE<"fsle.w", int_mips_fsle_w, MSA128WOpnd>; |
| class FSLE_D_DESC : MSA_3RF_DESC_BASE<"fsle.d", int_mips_fsle_d, MSA128DOpnd>; |
| |
| class FSLT_W_DESC : MSA_3RF_DESC_BASE<"fslt.w", int_mips_fslt_w, MSA128WOpnd>; |
| class FSLT_D_DESC : MSA_3RF_DESC_BASE<"fslt.d", int_mips_fslt_d, MSA128DOpnd>; |
| |
| class FSNE_W_DESC : MSA_3RF_DESC_BASE<"fsne.w", int_mips_fsne_w, MSA128WOpnd>; |
| class FSNE_D_DESC : MSA_3RF_DESC_BASE<"fsne.d", int_mips_fsne_d, MSA128DOpnd>; |
| |
| class FSOR_W_DESC : MSA_3RF_DESC_BASE<"fsor.w", int_mips_fsor_w, MSA128WOpnd>; |
| class FSOR_D_DESC : MSA_3RF_DESC_BASE<"fsor.d", int_mips_fsor_d, MSA128DOpnd>; |
| |
| class FSQRT_W_DESC : MSA_2RF_DESC_BASE<"fsqrt.w", fsqrt, MSA128WOpnd>; |
| class FSQRT_D_DESC : MSA_2RF_DESC_BASE<"fsqrt.d", fsqrt, MSA128DOpnd>; |
| |
| class FSUB_W_DESC : MSA_3RF_DESC_BASE<"fsub.w", fsub, MSA128WOpnd>; |
| class FSUB_D_DESC : MSA_3RF_DESC_BASE<"fsub.d", fsub, MSA128DOpnd>; |
| |
| class FSUEQ_W_DESC : MSA_3RF_DESC_BASE<"fsueq.w", int_mips_fsueq_w, |
| MSA128WOpnd>; |
| class FSUEQ_D_DESC : MSA_3RF_DESC_BASE<"fsueq.d", int_mips_fsueq_d, |
| MSA128DOpnd>; |
| |
| class FSULE_W_DESC : MSA_3RF_DESC_BASE<"fsule.w", int_mips_fsule_w, |
| MSA128WOpnd>; |
| class FSULE_D_DESC : MSA_3RF_DESC_BASE<"fsule.d", int_mips_fsule_d, |
| MSA128DOpnd>; |
| |
| class FSULT_W_DESC : MSA_3RF_DESC_BASE<"fsult.w", int_mips_fsult_w, |
| MSA128WOpnd>; |
| class FSULT_D_DESC : MSA_3RF_DESC_BASE<"fsult.d", int_mips_fsult_d, |
| MSA128DOpnd>; |
| |
| class FSUN_W_DESC : MSA_3RF_DESC_BASE<"fsun.w", int_mips_fsun_w, |
| MSA128WOpnd>; |
| class FSUN_D_DESC : MSA_3RF_DESC_BASE<"fsun.d", int_mips_fsun_d, |
| MSA128DOpnd>; |
| |
| class FSUNE_W_DESC : MSA_3RF_DESC_BASE<"fsune.w", int_mips_fsune_w, |
| MSA128WOpnd>; |
| class FSUNE_D_DESC : MSA_3RF_DESC_BASE<"fsune.d", int_mips_fsune_d, |
| MSA128DOpnd>; |
| |
| class FTINT_S_W_DESC : MSA_2RF_DESC_BASE<"ftint_s.w", int_mips_ftint_s_w, |
| MSA128WOpnd>; |
| class FTINT_S_D_DESC : MSA_2RF_DESC_BASE<"ftint_s.d", int_mips_ftint_s_d, |
| MSA128DOpnd>; |
| |
| class FTINT_U_W_DESC : MSA_2RF_DESC_BASE<"ftint_u.w", int_mips_ftint_u_w, |
| MSA128WOpnd>; |
| class FTINT_U_D_DESC : MSA_2RF_DESC_BASE<"ftint_u.d", int_mips_ftint_u_d, |
| MSA128DOpnd>; |
| |
| class FTQ_H_DESC : MSA_3RF_DESC_BASE<"ftq.h", int_mips_ftq_h, |
| MSA128HOpnd, MSA128WOpnd, MSA128WOpnd>; |
| class FTQ_W_DESC : MSA_3RF_DESC_BASE<"ftq.w", int_mips_ftq_w, |
| MSA128WOpnd, MSA128DOpnd, MSA128DOpnd>; |
| |
| class FTRUNC_S_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.w", fp_to_sint, |
| MSA128WOpnd>; |
| class FTRUNC_S_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_s.d", fp_to_sint, |
| MSA128DOpnd>; |
| |
| class FTRUNC_U_W_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.w", fp_to_uint, |
| MSA128WOpnd>; |
| class FTRUNC_U_D_DESC : MSA_2RF_DESC_BASE<"ftrunc_u.d", fp_to_uint, |
| MSA128DOpnd>; |
| |
| class HADD_S_H_DESC : MSA_3R_DESC_BASE<"hadd_s.h", int_mips_hadd_s_h, |
| MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; |
| class HADD_S_W_DESC : MSA_3R_DESC_BASE<"hadd_s.w", int_mips_hadd_s_w, |
| MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; |
| class HADD_S_D_DESC : MSA_3R_DESC_BASE<"hadd_s.d", int_mips_hadd_s_d, |
| MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; |
| |
| class HADD_U_H_DESC : MSA_3R_DESC_BASE<"hadd_u.h", int_mips_hadd_u_h, |
| MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; |
| class HADD_U_W_DESC : MSA_3R_DESC_BASE<"hadd_u.w", int_mips_hadd_u_w, |
| MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; |
| class HADD_U_D_DESC : MSA_3R_DESC_BASE<"hadd_u.d", int_mips_hadd_u_d, |
| MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; |
| |
| class HSUB_S_H_DESC : MSA_3R_DESC_BASE<"hsub_s.h", int_mips_hsub_s_h, |
| MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; |
| class HSUB_S_W_DESC : MSA_3R_DESC_BASE<"hsub_s.w", int_mips_hsub_s_w, |
| MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; |
| class HSUB_S_D_DESC : MSA_3R_DESC_BASE<"hsub_s.d", int_mips_hsub_s_d, |
| MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; |
| |
| class HSUB_U_H_DESC : MSA_3R_DESC_BASE<"hsub_u.h", int_mips_hsub_u_h, |
| MSA128HOpnd, MSA128BOpnd, MSA128BOpnd>; |
| class HSUB_U_W_DESC : MSA_3R_DESC_BASE<"hsub_u.w", int_mips_hsub_u_w, |
| MSA128WOpnd, MSA128HOpnd, MSA128HOpnd>; |
| class HSUB_U_D_DESC : MSA_3R_DESC_BASE<"hsub_u.d", int_mips_hsub_u_d, |
| MSA128DOpnd, MSA128WOpnd, MSA128WOpnd>; |
| |
| class ILVEV_B_DESC : MSA_3R_DESC_BASE<"ilvev.b", MipsILVEV, MSA128BOpnd>; |
| class ILVEV_H_DESC : MSA_3R_DESC_BASE<"ilvev.h", MipsILVEV, MSA128HOpnd>; |
| class ILVEV_W_DESC : MSA_3R_DESC_BASE<"ilvev.w", MipsILVEV, MSA128WOpnd>; |
| class ILVEV_D_DESC : MSA_3R_DESC_BASE<"ilvev.d", MipsILVEV, MSA128DOpnd>; |
| |
| class ILVL_B_DESC : MSA_3R_DESC_BASE<"ilvl.b", MipsILVL, MSA128BOpnd>; |
| class ILVL_H_DESC : MSA_3R_DESC_BASE<"ilvl.h", MipsILVL, MSA128HOpnd>; |
| class ILVL_W_DESC : MSA_3R_DESC_BASE<"ilvl.w", MipsILVL, MSA128WOpnd>; |
| class ILVL_D_DESC : MSA_3R_DESC_BASE<"ilvl.d", MipsILVL, MSA128DOpnd>; |
| |
| class ILVOD_B_DESC : MSA_3R_DESC_BASE<"ilvod.b", MipsILVOD, MSA128BOpnd>; |
| class ILVOD_H_DESC : MSA_3R_DESC_BASE<"ilvod.h", MipsILVOD, MSA128HOpnd>; |
| class ILVOD_W_DESC : MSA_3R_DESC_BASE<"ilvod.w", MipsILVOD, MSA128WOpnd>; |
| class ILVOD_D_DESC : MSA_3R_DESC_BASE<"ilvod.d", MipsILVOD, MSA128DOpnd>; |
| |
| class ILVR_B_DESC : MSA_3R_DESC_BASE<"ilvr.b", MipsILVR, MSA128BOpnd>; |
| class ILVR_H_DESC : MSA_3R_DESC_BASE<"ilvr.h", MipsILVR, MSA128HOpnd>; |
| class ILVR_W_DESC : MSA_3R_DESC_BASE<"ilvr.w", MipsILVR, MSA128WOpnd>; |
| class ILVR_D_DESC : MSA_3R_DESC_BASE<"ilvr.d", MipsILVR, MSA128DOpnd>; |
| |
| class INSERT_B_DESC : MSA_INSERT_DESC_BASE<"insert.b", vinsert_v16i8, uimm4, |
| immZExt4Ptr, MSA128BOpnd, GPR32Opnd>; |
| class INSERT_H_DESC : MSA_INSERT_DESC_BASE<"insert.h", vinsert_v8i16, uimm3, |
| immZExt3Ptr, MSA128HOpnd, GPR32Opnd>; |
| class INSERT_W_DESC : MSA_INSERT_DESC_BASE<"insert.w", vinsert_v4i32, uimm2, |
| immZExt2Ptr, MSA128WOpnd, GPR32Opnd>; |
| class INSERT_D_DESC : MSA_INSERT_DESC_BASE<"insert.d", vinsert_v2i64, uimm1, |
| immZExt1Ptr, MSA128DOpnd, GPR64Opnd>; |
| |
| class INSERT_B_VIDX_PSEUDO_DESC : |
| MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR32Opnd>; |
| class INSERT_H_VIDX_PSEUDO_DESC : |
| MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR32Opnd>; |
| class INSERT_W_VIDX_PSEUDO_DESC : |
| MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR32Opnd>; |
| class INSERT_D_VIDX_PSEUDO_DESC : |
| MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR32Opnd>; |
| |
| class INSERT_FW_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v4f32, |
| uimm2, immZExt2Ptr, |
| MSA128WOpnd, FGR32Opnd>; |
| class INSERT_FD_PSEUDO_DESC : MSA_INSERT_PSEUDO_BASE<vector_insert, v2f64, |
| uimm1, immZExt1Ptr, |
| MSA128DOpnd, FGR64Opnd>; |
| |
| class INSERT_FW_VIDX_PSEUDO_DESC : |
| MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR32Opnd>; |
| class INSERT_FD_VIDX_PSEUDO_DESC : |
| MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR32Opnd>; |
| |
| class INSERT_B_VIDX64_PSEUDO_DESC : |
| MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v16i8, MSA128BOpnd, GPR32Opnd, GPR64Opnd>; |
| class INSERT_H_VIDX64_PSEUDO_DESC : |
| MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v8i16, MSA128HOpnd, GPR32Opnd, GPR64Opnd>; |
| class INSERT_W_VIDX64_PSEUDO_DESC : |
| MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4i32, MSA128WOpnd, GPR32Opnd, GPR64Opnd>; |
| class INSERT_D_VIDX64_PSEUDO_DESC : |
| MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2i64, MSA128DOpnd, GPR64Opnd, GPR64Opnd>; |
| |
| class INSERT_FW_VIDX64_PSEUDO_DESC : |
| MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v4f32, MSA128WOpnd, FGR32Opnd, GPR64Opnd>; |
| class INSERT_FD_VIDX64_PSEUDO_DESC : |
| MSA_INSERT_VIDX_PSEUDO_BASE<vector_insert, v2f64, MSA128DOpnd, FGR64Opnd, GPR64Opnd>; |
| |
| class INSVE_B_DESC : MSA_INSVE_DESC_BASE<"insve.b", insve_v16i8, uimm4, timmZExt4, |
| MSA128BOpnd>; |
| class INSVE_H_DESC : MSA_INSVE_DESC_BASE<"insve.h", insve_v8i16, uimm3, timmZExt3, |
| MSA128HOpnd>; |
| class INSVE_W_DESC : MSA_INSVE_DESC_BASE<"insve.w", insve_v4i32, uimm2, timmZExt2, |
| MSA128WOpnd>; |
| class INSVE_D_DESC : MSA_INSVE_DESC_BASE<"insve.d", insve_v2i64, uimm1, timmZExt1, |
| MSA128DOpnd>; |
| |
| class LD_DESC_BASE<string instr_asm, SDPatternOperator OpNode, |
| ValueType TyNode, RegisterOperand ROWD, |
| Operand MemOpnd, ComplexPattern Addr = addrimm10, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs ROWD:$wd); |
| dag InOperandList = (ins MemOpnd:$addr); |
| string AsmString = !strconcat(instr_asm, "\t$wd, $addr"); |
| list<dag> Pattern = [(set ROWD:$wd, (TyNode (OpNode Addr:$addr)))]; |
| InstrItinClass Itinerary = itin; |
| string DecoderMethod = "DecodeMSA128Mem"; |
| } |
| |
| class LD_B_DESC : LD_DESC_BASE<"ld.b", load, v16i8, MSA128BOpnd, mem_simm10>; |
| class LD_H_DESC : LD_DESC_BASE<"ld.h", load, v8i16, MSA128HOpnd, |
| mem_simm10_lsl1, addrimm10lsl1>; |
| class LD_W_DESC : LD_DESC_BASE<"ld.w", load, v4i32, MSA128WOpnd, |
| mem_simm10_lsl2, addrimm10lsl2>; |
| class LD_D_DESC : LD_DESC_BASE<"ld.d", load, v2i64, MSA128DOpnd, |
| mem_simm10_lsl3, addrimm10lsl3>; |
| |
| class LDI_B_DESC : MSA_I10_LDI_DESC_BASE<"ldi.b", MSA128BOpnd>; |
| class LDI_H_DESC : MSA_I10_LDI_DESC_BASE<"ldi.h", MSA128HOpnd>; |
| class LDI_W_DESC : MSA_I10_LDI_DESC_BASE<"ldi.w", MSA128WOpnd>; |
| class LDI_D_DESC : MSA_I10_LDI_DESC_BASE<"ldi.d", MSA128DOpnd>; |
| |
| class MSA_LOAD_PSEUDO_BASE<SDPatternOperator intrinsic, RegisterOperand RO> : |
| PseudoSE<(outs RO:$dst), (ins PtrRC:$ptr, GPR32:$imm), |
| [(set RO:$dst, (intrinsic iPTR:$ptr, GPR32:$imm))]> { |
| let hasNoSchedulingInfo = 1; |
| let usesCustomInserter = 1; |
| } |
| |
| def LDR_D : MSA_LOAD_PSEUDO_BASE<int_mips_ldr_d, MSA128DOpnd>; |
| def LDR_W : MSA_LOAD_PSEUDO_BASE<int_mips_ldr_w, MSA128WOpnd>; |
| |
| class LSA_DESC_BASE<string instr_asm, RegisterOperand RORD, |
| InstrItinClass itin = NoItinerary> { |
| dag OutOperandList = (outs RORD:$rd); |
| dag InOperandList = (ins RORD:$rs, RORD:$rt, uimm2_plus1:$sa); |
| string AsmString = !strconcat(instr_asm, "\t$rd, $rs, $rt, $sa"); |
| list<dag> Pattern = [(set RORD:$rd, (add RORD:$rt, |
| (shl RORD:$rs, |
| |