)]}'
{
  "commit": "34b985f635a734e7e513ea2196f3010b9c3cc6ae",
  "tree": "b3ebcaf70c9c96f2f0154ee4710d8602557d8eaa",
  "parents": [
    "0123ee51ef3290466c6d743aac2932b23655aa04"
  ],
  "author": {
    "name": "Sudharsan Veeravalli",
    "email": "quic_svs@quicinc.com",
    "time": "Tue Jun 10 09:38:01 2025 +0530"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Jun 10 09:38:01 2025 +0530"
  },
  "message": "[RISCV] Select unsigned bitfield extract for Xqcibm (#143354)\n\nThe Xqcibm Bit Manipulation extension has the `qc.extu` instruction that\ncan extract a subset of bits from the source register to the destination\nregister.\n\nUnlike the corresponding instructions in XTHeadbb and XAndesPerf which\nextract the bits between `Msb` and `Lsb`, the `qc.extu` instruction\nextracts `width` bits from an offset that is determined by the `shamt`.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "52b2e0f02f057d6e06a3528e40809a73d762212d",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp",
      "new_id": "babc0d7ab27e2307a6ee692f4babc96e98c9c4de",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp"
    },
    {
      "type": "modify",
      "old_id": "3f5b949585fa3d082d7a0b28a5d96f42d5097ee5",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/RISCV/xqcibm-extract.ll",
      "new_id": "920dd025d4625af5d909414cfc38bf0796b117c9",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/RISCV/xqcibm-extract.ll"
    }
  ]
}