llvm/test/CodeGen/MIR/X86/subregister-operands.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=x86-64 -run-pass none -o - %s | FileCheck %s
# This test ensures that the MIR parser parses subregisters in register operands
# correctly.

--- |

  define zeroext i1 @t(i1 %c) {
  entry:
    ret i1 %c
  }

...
---
name:            t
tracksRegLiveness: true
registers:
  - { id: 0, class: gr32 }
  - { id: 1, class: gr8 }
  - { id: 2, class: gr8 }
body: |
  bb.0.entry:
    liveins: $edi
    ; CHECK-LABEL: name: t
    ; CHECK: liveins: $edi
    ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
    ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY [[COPY]].sub_8bit
    ; CHECK: [[AND8ri:%[0-9]+]]:gr8 = AND8ri [[COPY1]], 1, implicit-def $eflags
    ; CHECK: $al = COPY [[AND8ri]]
    ; CHECK: RET64 $al
    %0 = COPY $edi
    %1 = COPY %0.sub_8bit
    %2 = AND8ri %1, 1, implicit-def $eflags
    $al = COPY %2
    RET64 $al
...