# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*'  -verify-machineinstrs %s -o - 2> %t  | FileCheck -check-prefixes=GCN %s
# RUN: FileCheck -check-prefix=ERR  %s < %t

# ERR-NOT: remark:
# ERR: remark: <unknown>:0:0: cannot select: G_BRCOND %1:sgpr(s1), %bb.1 (in function: brcond_sgpr)
# ERR-NEXT: remark: <unknown>:0:0: cannot select: G_BRCOND %1:vgpr(s1), %bb.1 (in function: brcond_vgpr)
# ERR-NOT: remark:

---

name:            brcond_scc
legalized:       true
regBankSelected: true

body: |
  ; GCN-LABEL: name: brcond_scc
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; GCN:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
  ; GCN:   S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
  ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
  ; GCN:   $scc = COPY [[COPY2]]
  ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
  ; GCN: bb.1:
  bb.0:
    liveins: $sgpr0, $sgpr1

    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr1
    %2:sgpr(s32) = G_ICMP intpred(eq), %0, %1
    G_BRCOND %2, %bb.1

  bb.1:

...

---

name:            brcond_scc_impdef
legalized:       true
regBankSelected: true

body: |
  ; GCN-LABEL: name: brcond_scc_impdef
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; GCN:   $scc = COPY [[DEF]]
  ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
  ; GCN: bb.1:
  bb.0:
    liveins: $sgpr0, $sgpr1

    %0:sgpr(s32) = G_IMPLICIT_DEF
    G_BRCOND %0, %bb.1

  bb.1:

...

---

name:            brcond_scc_br
legalized:       true
regBankSelected: true

body: |
  ; GCN-LABEL: name: brcond_scc_br
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; GCN:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
  ; GCN:   S_CMP_EQ_U32 [[COPY]], [[COPY1]], implicit-def $scc
  ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $scc
  ; GCN:   $scc = COPY [[COPY2]]
  ; GCN:   S_CBRANCH_SCC1 %bb.1, implicit $scc
  ; GCN:   S_BRANCH %bb.1
  ; GCN: bb.1:
  ; GCN:   successors: %bb.2(0x80000000)
  ; GCN: bb.2:
  bb.0:
    liveins: $sgpr0, $sgpr1

    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s32) = COPY $sgpr1
    %2:sgpr(s32) = G_ICMP intpred(eq), %0, %1
    G_BRCOND %2, %bb.1
    G_BR %bb.1

  bb.1:

  bb.2:

...

---

name:            brcond_vcc
legalized:       true
regBankSelected: true

body: |
  ; GCN-LABEL: name: brcond_vcc
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GCN:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
  ; GCN:   $vcc = COPY [[V_CMP_EQ_U32_e64_]]
  ; GCN:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; GCN: bb.1:
  bb.0:
    liveins: $vgpr0, $vgpr1

    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
    G_BRCOND %2, %bb.1

  bb.1:

...

# Don't try to select this.
---

name:            brcond_sgpr
legalized:       true
regBankSelected: true

body: |
  ; GCN-LABEL: name: brcond_sgpr
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
  ; GCN:   [[TRUNC:%[0-9]+]]:sgpr(s1) = G_TRUNC [[COPY]](s32)
  ; GCN:   G_BRCOND [[TRUNC]](s1), %bb.1
  ; GCN: bb.1:
  bb.0:
    liveins: $sgpr0, $sgpr1

    %0:sgpr(s32) = COPY $sgpr0
    %1:sgpr(s1) = G_TRUNC %0
    G_BRCOND %1, %bb.1

  bb.1:

...

# Don't try to select this.
---

name:            brcond_vgpr
legalized:       true
regBankSelected: true

body: |
  ; GCN-LABEL: name: brcond_vgpr
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
  ; GCN:   [[TRUNC:%[0-9]+]]:vgpr(s1) = G_TRUNC [[COPY]](s32)
  ; GCN:   G_BRCOND [[TRUNC]](s1), %bb.1
  ; GCN: bb.1:
  bb.0:
    liveins: $vgpr0, $vgpr1

    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s1) = G_TRUNC %0
    G_BRCOND %1, %bb.1

  bb.1:

...

---

name:            brcond_class_intrinsic
legalized:       true
regBankSelected: true

body:             |
  ; GCN-LABEL: name: brcond_class_intrinsic
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GCN:   [[V_CMP_CLASS_F32_e64_:%[0-9]+]]:sreg_64 = V_CMP_CLASS_F32_e64 0, [[COPY]], [[COPY1]], implicit $exec
  ; GCN:   $vcc = COPY [[V_CMP_CLASS_F32_e64_]]
  ; GCN:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; GCN: bb.1:
  bb.0:
    liveins: $vgpr0, $vgpr1

    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vcc(s1) = G_INTRINSIC intrinsic(@llvm.amdgcn.class), %0:vgpr(s32), %1:vgpr(s32)
    G_BRCOND %2(s1), %bb.1

  bb.1:

...

---

name:            brcond_cmp_logic
legalized:       true
regBankSelected: true

body: |
  ; GCN-LABEL: name: brcond_cmp_logic
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GCN:   [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2
  ; GCN:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3
  ; GCN:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
  ; GCN:   %5:sreg_64_xexec = nofpexcept V_CMP_EQ_F32_e64 0, [[COPY2]], 0, [[COPY3]], 0, implicit $mode, implicit $exec
  ; GCN:   [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[V_CMP_EQ_U32_e64_]], %5, implicit-def dead $scc
  ; GCN:   $vcc = COPY [[S_AND_B64_]]
  ; GCN:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; GCN: bb.1:
  bb.0:
    liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3

    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vgpr(s32) = COPY $vgpr2
    %3:vgpr(s32) = COPY $vgpr3
    %4:vcc(s1) = G_ICMP intpred(eq), %0, %1
    %5:vcc(s1) = G_FCMP floatpred(oeq), %2, %3
    %6:vcc(s1) = G_AND %4, %5
    G_BRCOND %6(s1), %bb.1

  bb.1:

...

---

name:            brcond_logic
legalized:       true
regBankSelected: true

body:             |
  ; GCN-LABEL: name: brcond_logic
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GCN:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; GCN:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 1, [[COPY2]], implicit-def $scc
  ; GCN:   [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 0, [[S_AND_B32_]], implicit $exec
  ; GCN:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
  ; GCN:   [[S_AND_B64_:%[0-9]+]]:sreg_64_xexec = S_AND_B64 [[V_CMP_EQ_U32_e64_]], [[V_CMP_NE_U32_e64_]], implicit-def dead $scc
  ; GCN:   [[S_AND_B64_1:%[0-9]+]]:sreg_64 = S_AND_B64 [[S_AND_B64_]], $exec, implicit-def $scc
  ; GCN:   $vcc = COPY [[S_AND_B64_1]]
  ; GCN:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; GCN: bb.1:
  bb.0:
    liveins: $sgpr0, $vgpr0, $vgpr1

    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:sgpr(s32) = COPY $sgpr0
    %3:sgpr(s1) = G_TRUNC %2(s32)
    %4:vcc(s1) = COPY %3(s1)
    %5:vcc(s1) = G_ICMP intpred(eq), %0, %1
    %6:vcc(s1) = G_AND %5, %4
    G_BRCOND %6(s1), %bb.1

  bb.1:

...

---

name:            brcond_logic_const
legalized:       true
regBankSelected: true

body:             |
  ; GCN-LABEL: name: brcond_logic_const
  ; GCN: bb.0:
  ; GCN:   successors: %bb.1(0x80000000)
  ; GCN:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GCN:   [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
  ; GCN:   [[V_CMP_EQ_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_EQ_U32_e64 [[COPY]], [[COPY1]], implicit $exec
  ; GCN:   [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1
  ; GCN:   [[S_XOR_B64_:%[0-9]+]]:sreg_64_xexec = S_XOR_B64 [[V_CMP_EQ_U32_e64_]], [[S_MOV_B64_]], implicit-def dead $scc
  ; GCN:   [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 [[S_XOR_B64_]], $exec, implicit-def $scc
  ; GCN:   $vcc = COPY [[S_AND_B64_]]
  ; GCN:   S_CBRANCH_VCCNZ %bb.1, implicit $vcc
  ; GCN: bb.1:
  bb.0:
    liveins: $vgpr0, $vgpr1

    %0:vgpr(s32) = COPY $vgpr0
    %1:vgpr(s32) = COPY $vgpr1
    %2:vcc(s1) = G_ICMP intpred(eq), %0, %1
    %3:sgpr(s1) = G_CONSTANT i1 true
    %4:vcc(s1) = COPY %3(s1)
    %5:vcc(s1) = G_XOR %2, %4
    G_BRCOND %5(s1), %bb.1

  bb.1:

...