)]}'
{
  "commit": "3264a50fe2b61e79572d1623d0cceb2fe88da533",
  "tree": "c91207ff92648f581b889322ad1d3316e0644c40",
  "parents": [
    "04b87e15e40f8857e29ade8321b8b67691545a50"
  ],
  "author": {
    "name": "Srinivasa Ravi",
    "email": "srinivasar@nvidia.com",
    "time": "Wed Apr 16 10:03:21 2025 +0530"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Apr 16 10:03:21 2025 +0530"
  },
  "message": "[clang][NVPTX] Add builtins and intrinsics for conversions of new FP types (#134345)\n\nThis change:\n- Adds NVVM intrinsics and clang builtins for the cvt instruction\nvariants of types (FP6) `.e2m3x2`, `.e3m2x2`, and (FP8) `.ue8m0x2`\nintroduced in PTX 8.6 for `sm_100a`, `sm_101a`, and `sm_120a`.\n- Adds clang builtins for cvt instruction variant of type tf32.\n\nTests are added in `NVPTX/convert-sm100a.ll` and\n`clang/test/CodeGen/builtins-nvptx.c` and verified through ptxas 12.8.0.\n\nPTX Spec Reference:\nhttps://docs.nvidia.com/cuda/parallel-thread-execution/#data-movement-and-conversion-instructions-cvt",
  "tree_diff": [
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