commit 30ebafaa56846dc0f1607a6a8d41c96fcdc717cb
author Matt Arsenault <Matthew.Arsenault@amd.com> Fri Apr 03 13:22:51 2020 -0400
committer Matt Arsenault <arsenm2@gmail.com> Fri Apr 03 14:52:54 2020 -0400
tree bd6fd1d04f78f357216bc552d9558b6bf6d51599
parent 178050c3ba119d13155ea6487332661a0eee3eb1

CodeGen: Convert some TII hooks to use Register

llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp

diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
index 5563b55..b45d871 100644
--- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
@@ -504,7 +504,7 @@
 
   // Get the registers on which the loop controlling compare instruction
   // depends.
-  unsigned CmpR1 = 0, CmpR2 = 0;
+  Register CmpR1, CmpR2;
   const MachineInstr *CmpI = MRI->getVRegDef(PR);
   while (CmpI->getOpcode() == Hexagon::C2_not)
     CmpI = MRI->getVRegDef(CmpI->getOperand(1).getReg());