[RISCV] Remove RISCVVectorPeephole::tryToReduceVL (#184297) Now that RISCVVLOptimizer has been extended to handle the remaining cases tryToReduceVL handles, we can remove tryToReduceVL to keep all the reduction logic in one place. Intended to be NFC but it looks like in test/CodeGen/RISCV/rvv/fixed-vectors-insert-subvector-shuffle.ll we were previously reducing the vl of a volatile load in insert_subvector_dag_loop, which RISCVVLOptimizer knows to avoid. On llvm-test-suite and SPEC CPU 2017 -march=rva23u64 -O3 there are no changes with this patch.
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