)]}'
{
  "commit": "2eb709b95d8f521aa15401e159fac0729d56a677",
  "tree": "0a28601f86458d958aa5ad1aed730b12a608e8e4",
  "parents": [
    "135744c0d7cfcebcfad75d7937e3973faf36e4da"
  ],
  "author": {
    "name": "Alexander Weinrauch",
    "email": "alexander.weinrauch@amd.com",
    "time": "Fri Jan 16 13:52:47 2026 +0000"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Fri Jan 16 13:52:47 2026 +0000"
  },
  "message": "[AMDGPU] Fix typo in `LowerVGPREncoding` to allow it to hoist past `waitcnt` instructions (#176355)\n\nFixes a typo which prevented `set_vgpr_msb` to be hoisted past `waitcnt`\ninstructions.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "518e39ffaf242f51b5c312fd32e58d956cef8c11",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp",
      "new_id": "7e946018c44921a010137bcdb2591e3e31782f79",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/AMDGPULowerVGPREncoding.cpp"
    },
    {
      "type": "modify",
      "old_id": "1624f787c1b4082bb64b73e5adbf987896866697",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir",
      "new_id": "60975d7a8d724af8ecc48a55d954f7c6f01df58d",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/AMDGPU/vgpr-set-msb-coissue.mir"
    },
    {
      "type": "modify",
      "old_id": "bfad131dc4413539541f44e2ecd3471d65456ede",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll",
      "new_id": "c4f8e332a429cc7b6cd568d7e5c83a5a017a28a7",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/AMDGPU/whole-wave-functions.ll"
    }
  ]
}