[test] Cover R_RISCV_ADD/SUB and R_RISCV_RVC_{BRANCH,JUMP} (#195555)
These were uncovered according to an LLVM_BUILD_INSTRUMENTED_COVERAGE
build.
llvm-mc resolves `.L1 - .L0` differences at assembly time, so
riscv-reloc-add.s doesn't emit the R_RISCV_ADD*/R_RISCV_SUB* pairs it
was meant to test.
Add riscv-reloc-rvc.s, modeled on riscv-branch.s/riscv-jal.s, to
exercise R_RISCV_RVC_BRANCH and R_RISCV_RVC_JUMP. Drive offsets via
-Ttext + --defsym to land precise values that isolate complementary
extractBits groups.Welcome to the LLVM project!
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