Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Register as started by r367614. NFC
llvm-svn: 367633
diff --git a/llvm/lib/Target/Hexagon/BitTracker.cpp b/llvm/lib/Target/Hexagon/BitTracker.cpp
index b7e95ca..a2dcad1 100644
--- a/llvm/lib/Target/Hexagon/BitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/BitTracker.cpp
@@ -84,7 +84,7 @@
raw_ostream &operator<< (raw_ostream &OS, const printv &PV) {
if (PV.R)
- OS << 'v' << TargetRegisterInfo::virtReg2Index(PV.R);
+ OS << 'v' << Register::virtReg2Index(PV.R);
else
OS << 's';
return OS;
@@ -201,7 +201,7 @@
bool BT::RegisterCell::meet(const RegisterCell &RC, unsigned SelfR) {
// An example when "meet" can be invoked with SelfR == 0 is a phi node
// with a physical register as an operand.
- assert(SelfR == 0 || TargetRegisterInfo::isVirtualRegister(SelfR));
+ assert(SelfR == 0 || Register::isVirtualRegister(SelfR));
bool Changed = false;
for (uint16_t i = 0, n = Bits.size(); i < n; ++i) {
const BitValue &RCV = RC[i];
@@ -335,11 +335,11 @@
// 1. find a physical register PhysR from the same class as RR.Reg,
// 2. find a physical register PhysS that corresponds to PhysR:RR.Sub,
// 3. find a register class that contains PhysS.
- if (TargetRegisterInfo::isVirtualRegister(RR.Reg)) {
+ if (Register::isVirtualRegister(RR.Reg)) {
const auto &VC = composeWithSubRegIndex(*MRI.getRegClass(RR.Reg), RR.Sub);
return TRI.getRegSizeInBits(VC);
}
- assert(TargetRegisterInfo::isPhysicalRegister(RR.Reg));
+ assert(Register::isPhysicalRegister(RR.Reg));
unsigned PhysR = (RR.Sub == 0) ? RR.Reg : TRI.getSubReg(RR.Reg, RR.Sub);
return getPhysRegBitWidth(PhysR);
}
@@ -350,10 +350,10 @@
// Physical registers are assumed to be present in the map with an unknown
// value. Don't actually insert anything in the map, just return the cell.
- if (TargetRegisterInfo::isPhysicalRegister(RR.Reg))
+ if (Register::isPhysicalRegister(RR.Reg))
return RegisterCell::self(0, BW);
- assert(TargetRegisterInfo::isVirtualRegister(RR.Reg));
+ assert(Register::isVirtualRegister(RR.Reg));
// For virtual registers that belong to a class that is not tracked,
// generate an "unknown" value as well.
const TargetRegisterClass *C = MRI.getRegClass(RR.Reg);
@@ -376,7 +376,7 @@
// While updating the cell map can be done in a meaningful way for
// a part of a register, it makes little sense to implement it as the
// SSA representation would never contain such "partial definitions".
- if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
+ if (!Register::isVirtualRegister(RR.Reg))
return;
assert(RR.Sub == 0 && "Unexpected sub-register in definition");
// Eliminate all ref-to-reg-0 bit values: replace them with "self".
@@ -711,7 +711,7 @@
}
uint16_t BT::MachineEvaluator::getPhysRegBitWidth(unsigned Reg) const {
- assert(TargetRegisterInfo::isPhysicalRegister(Reg));
+ assert(Register::isPhysicalRegister(Reg));
const TargetRegisterClass &PC = *TRI.getMinimalPhysRegClass(Reg);
return TRI.getRegSizeInBits(PC);
}
@@ -874,7 +874,7 @@
continue;
RegisterRef RD(MO);
assert(RD.Sub == 0 && "Unexpected sub-register in definition");
- if (!TargetRegisterInfo::isVirtualRegister(RD.Reg))
+ if (!Register::isVirtualRegister(RD.Reg))
continue;
bool Changed = false;
diff --git a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
index 7b75d25..d33d179 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitSimplify.cpp
@@ -147,11 +147,11 @@
}
static inline unsigned v2x(unsigned v) {
- return TargetRegisterInfo::virtReg2Index(v);
+ return Register::virtReg2Index(v);
}
static inline unsigned x2v(unsigned x) {
- return TargetRegisterInfo::index2VirtReg(x);
+ return Register::index2VirtReg(x);
}
};
@@ -291,7 +291,7 @@
if (!Op.isReg() || !Op.isDef())
continue;
unsigned R = Op.getReg();
- if (!TargetRegisterInfo::isVirtualRegister(R))
+ if (!Register::isVirtualRegister(R))
continue;
Defs.insert(R);
}
@@ -303,7 +303,7 @@
if (!Op.isReg() || !Op.isUse())
continue;
unsigned R = Op.getReg();
- if (!TargetRegisterInfo::isVirtualRegister(R))
+ if (!Register::isVirtualRegister(R))
continue;
Uses.insert(R);
}
@@ -353,8 +353,7 @@
bool HexagonBitSimplify::replaceReg(unsigned OldR, unsigned NewR,
MachineRegisterInfo &MRI) {
- if (!TargetRegisterInfo::isVirtualRegister(OldR) ||
- !TargetRegisterInfo::isVirtualRegister(NewR))
+ if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
return false;
auto Begin = MRI.use_begin(OldR), End = MRI.use_end();
decltype(End) NextI;
@@ -367,8 +366,7 @@
bool HexagonBitSimplify::replaceRegWithSub(unsigned OldR, unsigned NewR,
unsigned NewSR, MachineRegisterInfo &MRI) {
- if (!TargetRegisterInfo::isVirtualRegister(OldR) ||
- !TargetRegisterInfo::isVirtualRegister(NewR))
+ if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
return false;
if (hasTiedUse(OldR, MRI, NewSR))
return false;
@@ -384,8 +382,7 @@
bool HexagonBitSimplify::replaceSubWithSub(unsigned OldR, unsigned OldSR,
unsigned NewR, unsigned NewSR, MachineRegisterInfo &MRI) {
- if (!TargetRegisterInfo::isVirtualRegister(OldR) ||
- !TargetRegisterInfo::isVirtualRegister(NewR))
+ if (!Register::isVirtualRegister(OldR) || !Register::isVirtualRegister(NewR))
return false;
if (OldSR != NewSR && hasTiedUse(OldR, MRI, NewSR))
return false;
@@ -896,7 +893,7 @@
// register class.
const TargetRegisterClass *HexagonBitSimplify::getFinalVRegClass(
const BitTracker::RegisterRef &RR, MachineRegisterInfo &MRI) {
- if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
+ if (!Register::isVirtualRegister(RR.Reg))
return nullptr;
auto *RC = MRI.getRegClass(RR.Reg);
if (RR.Sub == 0)
@@ -927,8 +924,8 @@
// with a 32-bit register.
bool HexagonBitSimplify::isTransparentCopy(const BitTracker::RegisterRef &RD,
const BitTracker::RegisterRef &RS, MachineRegisterInfo &MRI) {
- if (!TargetRegisterInfo::isVirtualRegister(RD.Reg) ||
- !TargetRegisterInfo::isVirtualRegister(RS.Reg))
+ if (!Register::isVirtualRegister(RD.Reg) ||
+ !Register::isVirtualRegister(RS.Reg))
return false;
// Return false if one (or both) classes are nullptr.
auto *DRC = getFinalVRegClass(RD, MRI);
@@ -1019,7 +1016,7 @@
if (!Op.isReg() || !Op.isDef())
continue;
unsigned R = Op.getReg();
- if (!TargetRegisterInfo::isVirtualRegister(R) || !isDead(R)) {
+ if (!Register::isVirtualRegister(R) || !isDead(R)) {
AllDead = false;
break;
}
@@ -1221,7 +1218,7 @@
MachineInstr &UseI = *I->getParent();
if (UseI.isPHI() || UseI.isCopy()) {
unsigned DefR = UseI.getOperand(0).getReg();
- if (!TargetRegisterInfo::isVirtualRegister(DefR))
+ if (!Register::isVirtualRegister(DefR))
return false;
Pending.push_back(DefR);
} else {
@@ -1470,7 +1467,7 @@
if (Defs.count() != 1)
continue;
unsigned DR = Defs.find_first();
- if (!TargetRegisterInfo::isVirtualRegister(DR))
+ if (!Register::isVirtualRegister(DR))
continue;
uint64_t U;
const BitTracker::RegisterCell &DRC = BT.lookup(DR);
@@ -1819,7 +1816,7 @@
if (Reg == 0 || Reg == SelfR) // Don't match "self".
return false;
- if (!TargetRegisterInfo::isVirtualRegister(Reg))
+ if (!Register::isVirtualRegister(Reg))
return false;
if (!BT.has(Reg))
return false;
@@ -3162,7 +3159,7 @@
if (Defs.count() != 1)
continue;
unsigned DefR = Defs.find_first();
- if (!TargetRegisterInfo::isVirtualRegister(DefR))
+ if (!Register::isVirtualRegister(DefR))
continue;
if (!isBitShuffle(&*I, DefR))
continue;
diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
index ba50faa..80ef3c1 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
@@ -111,7 +111,7 @@
}
uint16_t HexagonEvaluator::getPhysRegBitWidth(unsigned Reg) const {
- assert(TargetRegisterInfo::isPhysicalRegister(Reg));
+ assert(Register::isPhysicalRegister(Reg));
using namespace Hexagon;
const auto &HST = MF.getSubtarget<HexagonSubtarget>();
@@ -1043,7 +1043,7 @@
if (!Op.isReg() || !Op.isDef())
continue;
unsigned R = Op.getReg();
- if (!TargetRegisterInfo::isVirtualRegister(R))
+ if (!Register::isVirtualRegister(R))
continue;
if (DefReg != 0)
return 0;
@@ -1220,7 +1220,7 @@
RegisterRef RD = MI.getOperand(0);
RegisterRef RS = MI.getOperand(1);
assert(RD.Sub == 0);
- if (!TargetRegisterInfo::isPhysicalRegister(RS.Reg))
+ if (!Register::isPhysicalRegister(RS.Reg))
return false;
RegExtMap::const_iterator F = VRX.find(RD.Reg);
if (F == VRX.end())
diff --git a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
index 999150f..d1d1b8e 100644
--- a/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBlockRanges.cpp
@@ -268,14 +268,14 @@
return SRs;
}
- if (TargetRegisterInfo::isPhysicalRegister(R.Reg)) {
+ if (Register::isPhysicalRegister(R.Reg)) {
MCSubRegIterator I(R.Reg, &TRI);
if (!I.isValid())
SRs.insert({R.Reg, 0});
for (; I.isValid(); ++I)
SRs.insert({*I, 0});
} else {
- assert(TargetRegisterInfo::isVirtualRegister(R.Reg));
+ assert(Register::isVirtualRegister(R.Reg));
auto &RC = *MRI.getRegClass(R.Reg);
unsigned PReg = *RC.begin();
MCSubRegIndexIterator I(PReg, &TRI);
@@ -321,7 +321,7 @@
if (!Op.isReg() || !Op.isUse() || Op.isUndef())
continue;
RegisterRef R = { Op.getReg(), Op.getSubReg() };
- if (TargetRegisterInfo::isPhysicalRegister(R.Reg) && Reserved[R.Reg])
+ if (Register::isPhysicalRegister(R.Reg) && Reserved[R.Reg])
continue;
bool IsKill = Op.isKill();
for (auto S : expandToSubRegs(R, MRI, TRI)) {
@@ -338,7 +338,7 @@
continue;
RegisterRef R = { Op.getReg(), Op.getSubReg() };
for (auto S : expandToSubRegs(R, MRI, TRI)) {
- if (TargetRegisterInfo::isPhysicalRegister(S.Reg) && Reserved[S.Reg])
+ if (Register::isPhysicalRegister(S.Reg) && Reserved[S.Reg])
continue;
if (Op.isDead())
Clobbers.insert(S);
@@ -374,7 +374,7 @@
// Update maps for defs.
for (RegisterRef S : Defs) {
// Defs should already be expanded into subregs.
- assert(!TargetRegisterInfo::isPhysicalRegister(S.Reg) ||
+ assert(!Register::isPhysicalRegister(S.Reg) ||
!MCSubRegIterator(S.Reg, &TRI, false).isValid());
if (LastDef[S] != IndexType::None || LastUse[S] != IndexType::None)
closeRange(S);
@@ -383,7 +383,7 @@
// Update maps for clobbers.
for (RegisterRef S : Clobbers) {
// Clobbers should already be expanded into subregs.
- assert(!TargetRegisterInfo::isPhysicalRegister(S.Reg) ||
+ assert(!Register::isPhysicalRegister(S.Reg) ||
!MCSubRegIterator(S.Reg, &TRI, false).isValid());
if (LastDef[S] != IndexType::None || LastUse[S] != IndexType::None)
closeRange(S);
@@ -482,7 +482,7 @@
}
}
for (auto &P : LiveMap)
- if (TargetRegisterInfo::isVirtualRegister(P.first.Reg))
+ if (Register::isVirtualRegister(P.first.Reg))
addDeadRanges(P.first);
LLVM_DEBUG(dbgs() << __func__ << ": dead map\n"
diff --git a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
index cfed0ece..c900851 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstExtenders.cpp
@@ -14,9 +14,10 @@
#include "llvm/CodeGen/MachineFunctionPass.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/Register.h"
+#include "llvm/Pass.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/raw_ostream.h"
-#include "llvm/Pass.h"
#include <map>
#include <set>
#include <utility>
@@ -235,24 +236,24 @@
Reg = Op.getReg();
Sub = Op.getSubReg();
} else if (Op.isFI()) {
- Reg = TargetRegisterInfo::index2StackSlot(Op.getIndex());
+ Reg = llvm::Register::index2StackSlot(Op.getIndex());
}
return *this;
}
bool isVReg() const {
- return Reg != 0 && !TargetRegisterInfo::isStackSlot(Reg) &&
- TargetRegisterInfo::isVirtualRegister(Reg);
+ return Reg != 0 && !llvm::Register::isStackSlot(Reg) &&
+ llvm::Register::isVirtualRegister(Reg);
}
bool isSlot() const {
- return Reg != 0 && TargetRegisterInfo::isStackSlot(Reg);
+ return Reg != 0 && llvm::Register::isStackSlot(Reg);
}
operator MachineOperand() const {
if (isVReg())
return MachineOperand::CreateReg(Reg, /*Def*/false, /*Imp*/false,
/*Kill*/false, /*Dead*/false, /*Undef*/false,
/*EarlyClobber*/false, Sub);
- if (TargetRegisterInfo::isStackSlot(Reg)) {
- int FI = TargetRegisterInfo::stackSlot2Index(Reg);
+ if (llvm::Register::isStackSlot(Reg)) {
+ int FI = llvm::Register::stackSlot2Index(Reg);
return MachineOperand::CreateFI(FI);
}
llvm_unreachable("Cannot create MachineOperand");
diff --git a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
index d1fde5d..6724093 100644
--- a/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonConstPropagation.cpp
@@ -208,14 +208,14 @@
bool has(unsigned R) const {
// All non-virtual registers are considered "bottom".
- if (!TargetRegisterInfo::isVirtualRegister(R))
+ if (!Register::isVirtualRegister(R))
return true;
MapType::const_iterator F = Map.find(R);
return F != Map.end();
}
const LatticeCell &get(unsigned R) const {
- if (!TargetRegisterInfo::isVirtualRegister(R))
+ if (!Register::isVirtualRegister(R))
return Bottom;
MapType::const_iterator F = Map.find(R);
if (F != Map.end())
@@ -623,7 +623,7 @@
const MachineOperand &MD = PN.getOperand(0);
RegisterSubReg DefR(MD);
- assert(TargetRegisterInfo::isVirtualRegister(DefR.Reg));
+ assert(Register::isVirtualRegister(DefR.Reg));
bool Changed = false;
@@ -652,7 +652,7 @@
RegisterSubReg UseR(SO);
// If the input is not a virtual register, we don't really know what
// value it holds.
- if (!TargetRegisterInfo::isVirtualRegister(UseR.Reg))
+ if (!Register::isVirtualRegister(UseR.Reg))
goto Bottomize;
// If there is no cell for an input register, it means top.
if (!Cells.has(UseR.Reg))
@@ -694,7 +694,7 @@
continue;
RegisterSubReg DefR(MO);
// Only track virtual registers.
- if (!TargetRegisterInfo::isVirtualRegister(DefR.Reg))
+ if (!Register::isVirtualRegister(DefR.Reg))
continue;
bool Changed = false;
// If the evaluation failed, set cells for all output registers to bottom.
@@ -1070,7 +1070,7 @@
bool MachineConstEvaluator::getCell(const RegisterSubReg &R, const CellMap &Inputs,
LatticeCell &RC) {
- if (!TargetRegisterInfo::isVirtualRegister(R.Reg))
+ if (!Register::isVirtualRegister(R.Reg))
return false;
const LatticeCell &L = Inputs.get(R.Reg);
if (!R.SubReg) {
@@ -1926,7 +1926,7 @@
unsigned Opc = MI.getOpcode();
RegisterSubReg DefR(MD);
assert(!DefR.SubReg);
- if (!TargetRegisterInfo::isVirtualRegister(DefR.Reg))
+ if (!Register::isVirtualRegister(DefR.Reg))
return false;
if (MI.isCopy()) {
@@ -2793,7 +2793,7 @@
if (!MO.isReg() || !MO.isUse() || MO.isImplicit())
continue;
RegisterSubReg R(MO);
- if (!TargetRegisterInfo::isVirtualRegister(R.Reg))
+ if (!Register::isVirtualRegister(R.Reg))
continue;
HasUse = true;
// PHIs can legitimately have "top" cells after propagation.
@@ -2832,7 +2832,7 @@
if (!MO.isReg() || !MO.isDef())
continue;
unsigned R = MO.getReg();
- if (!TargetRegisterInfo::isVirtualRegister(R))
+ if (!Register::isVirtualRegister(R))
continue;
assert(!MO.getSubReg());
assert(Inputs.has(R));
@@ -3111,8 +3111,8 @@
void HexagonConstEvaluator::replaceAllRegUsesWith(unsigned FromReg,
unsigned ToReg) {
- assert(TargetRegisterInfo::isVirtualRegister(FromReg));
- assert(TargetRegisterInfo::isVirtualRegister(ToReg));
+ assert(Register::isVirtualRegister(FromReg));
+ assert(Register::isVirtualRegister(ToReg));
for (auto I = MRI->use_begin(FromReg), E = MRI->use_end(); I != E;) {
MachineOperand &O = *I;
++I;
diff --git a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
index a09ccab..db0bd3b 100644
--- a/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonCopyToCombine.cpp
@@ -226,7 +226,7 @@
}
static bool isEvenReg(unsigned Reg) {
- assert(TargetRegisterInfo::isPhysicalRegister(Reg));
+ assert(Register::isPhysicalRegister(Reg));
if (Hexagon::IntRegsRegClass.contains(Reg))
return (Reg - Hexagon::R0) % 2 == 0;
if (Hexagon::HvxVRRegClass.contains(Reg))
diff --git a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
index c1f32e5..36a5fad 100644
--- a/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonEarlyIfConv.cpp
@@ -385,7 +385,7 @@
if (!MO.isReg() || !MO.isDef())
continue;
unsigned R = MO.getReg();
- if (!TargetRegisterInfo::isVirtualRegister(R))
+ if (!Register::isVirtualRegister(R))
continue;
if (!isPredicate(R))
continue;
@@ -402,7 +402,7 @@
if (!MO.isReg() || !MO.isUse())
continue;
unsigned R = MO.getReg();
- if (!TargetRegisterInfo::isVirtualRegister(R))
+ if (!Register::isVirtualRegister(R))
continue;
const MachineInstr *DefI = MRI->getVRegDef(R);
// "Undefined" virtual registers are actually defined via IMPLICIT_DEF.
@@ -492,7 +492,7 @@
if (!MO.isReg() || !MO.isDef())
continue;
unsigned R = MO.getReg();
- if (!TargetRegisterInfo::isVirtualRegister(R))
+ if (!Register::isVirtualRegister(R))
continue;
if (isPredicate(R))
PredDefs++;
diff --git a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
index c343e42..52e97ed 100644
--- a/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp
@@ -285,7 +285,7 @@
}
LaneBitmask HexagonExpandCondsets::getLaneMask(unsigned Reg, unsigned Sub) {
- assert(TargetRegisterInfo::isVirtualRegister(Reg));
+ assert(Register::isVirtualRegister(Reg));
return Sub != 0 ? TRI->getSubRegIndexLaneMask(Sub)
: MRI->getMaxLaneMaskForVReg(Reg);
}
@@ -364,7 +364,7 @@
void HexagonExpandCondsets::updateDeadsInRange(unsigned Reg, LaneBitmask LM,
LiveRange &Range) {
- assert(TargetRegisterInfo::isVirtualRegister(Reg));
+ assert(Register::isVirtualRegister(Reg));
if (Range.empty())
return;
@@ -373,7 +373,7 @@
if (!Op.isReg() || !Op.isDef())
return { false, false };
unsigned DR = Op.getReg(), DSR = Op.getSubReg();
- if (!TargetRegisterInfo::isVirtualRegister(DR) || DR != Reg)
+ if (!Register::isVirtualRegister(DR) || DR != Reg)
return { false, false };
LaneBitmask SLM = getLaneMask(DR, DSR);
LaneBitmask A = SLM & LM;
@@ -551,8 +551,8 @@
bool Recalc, bool UpdateKills, bool UpdateDeads) {
UpdateKills |= UpdateDeads;
for (unsigned R : RegSet) {
- if (!TargetRegisterInfo::isVirtualRegister(R)) {
- assert(TargetRegisterInfo::isPhysicalRegister(R));
+ if (!Register::isVirtualRegister(R)) {
+ assert(Register::isPhysicalRegister(R));
// There shouldn't be any physical registers as operands, except
// possibly reserved registers.
assert(MRI->isReserved(R));
@@ -581,12 +581,12 @@
if (SO.isReg()) {
unsigned PhysR;
RegisterRef RS = SO;
- if (TargetRegisterInfo::isVirtualRegister(RS.Reg)) {
+ if (Register::isVirtualRegister(RS.Reg)) {
const TargetRegisterClass *VC = MRI->getRegClass(RS.Reg);
assert(VC->begin() != VC->end() && "Empty register class");
PhysR = *VC->begin();
} else {
- assert(TargetRegisterInfo::isPhysicalRegister(RS.Reg));
+ assert(Register::isPhysicalRegister(RS.Reg));
PhysR = RS.Reg;
}
unsigned PhysS = (RS.Sub == 0) ? PhysR : TRI->getSubReg(PhysR, RS.Sub);
@@ -802,7 +802,7 @@
// For physical register we would need to check register aliases, etc.
// and we don't want to bother with that. It would be of little value
// before the actual register rewriting (from virtual to physical).
- if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
+ if (!Register::isVirtualRegister(RR.Reg))
return false;
// No redefs for any operand.
if (isRefInMap(RR, Defs, Exec_Then))
@@ -999,7 +999,7 @@
// subregisters are other physical registers, and we are not checking
// that.
RegisterRef RR = Op;
- if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
+ if (!Register::isVirtualRegister(RR.Reg))
return false;
ReferenceMap &Map = Op.isDef() ? Defs : Uses;
@@ -1091,7 +1091,7 @@
}
bool HexagonExpandCondsets::isIntReg(RegisterRef RR, unsigned &BW) {
- if (!TargetRegisterInfo::isVirtualRegister(RR.Reg))
+ if (!Register::isVirtualRegister(RR.Reg))
return false;
const TargetRegisterClass *RC = MRI->getRegClass(RR.Reg);
if (RC == &Hexagon::IntRegsRegClass) {
diff --git a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
index 3368ee4..5d2b5b6 100644
--- a/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonFrameLowering.cpp
@@ -306,7 +306,7 @@
unsigned R = MO.getReg();
// Virtual registers will need scavenging, which then may require
// a stack slot.
- if (TargetRegisterInfo::isVirtualRegister(R))
+ if (Register::isVirtualRegister(R))
return true;
for (MCSubRegIterator S(R, &HRI, true); S.isValid(); ++S)
if (CSR[*S])
diff --git a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
index 81025c1..6c996c0 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenInsert.cpp
@@ -163,11 +163,11 @@
}
static inline unsigned v2x(unsigned v) {
- return TargetRegisterInfo::virtReg2Index(v);
+ return Register::virtReg2Index(v);
}
static inline unsigned x2v(unsigned x) {
- return TargetRegisterInfo::index2VirtReg(x);
+ return Register::index2VirtReg(x);
}
};
@@ -267,7 +267,7 @@
CellMapShadow(const BitTracker &T) : BT(T) {}
const BitTracker::RegisterCell &lookup(unsigned VR) {
- unsigned RInd = TargetRegisterInfo::virtReg2Index(VR);
+ unsigned RInd = Register::virtReg2Index(VR);
// Grow the vector to at least 32 elements.
if (RInd >= CVect.size())
CVect.resize(std::max(RInd+16, 32U), nullptr);
@@ -608,7 +608,7 @@
if (MO.isReg() && MO.isDef()) {
unsigned R = MO.getReg();
assert(MO.getSubReg() == 0 && "Unexpected subregister in definition");
- if (TargetRegisterInfo::isVirtualRegister(R))
+ if (Register::isVirtualRegister(R))
RO.insert(std::make_pair(R, Index++));
}
}
@@ -725,7 +725,7 @@
if (!MO.isReg() || !MO.isDef())
continue;
unsigned R = MO.getReg();
- if (!TargetRegisterInfo::isVirtualRegister(R))
+ if (!Register::isVirtualRegister(R))
continue;
Defs.insert(R);
}
@@ -738,7 +738,7 @@
if (!MO.isReg() || !MO.isUse())
continue;
unsigned R = MO.getReg();
- if (!TargetRegisterInfo::isVirtualRegister(R))
+ if (!Register::isVirtualRegister(R))
continue;
Uses.insert(R);
}
@@ -1478,8 +1478,7 @@
if (!MO.isReg() || !MO.isDef())
continue;
unsigned R = MO.getReg();
- if (!TargetRegisterInfo::isVirtualRegister(R) ||
- !MRI->use_nodbg_empty(R)) {
+ if (!Register::isVirtualRegister(R) || !MRI->use_nodbg_empty(R)) {
AllDead = false;
break;
}
@@ -1598,7 +1597,7 @@
IterListType Out;
for (IFMapType::iterator I = IFMap.begin(), E = IFMap.end(); I != E; ++I) {
- unsigned Idx = TargetRegisterInfo::virtReg2Index(I->first);
+ unsigned Idx = Register::virtReg2Index(I->first);
if (Idx >= Cutoff)
Out.push_back(I);
}
diff --git a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
index e991fa8..cd4b5fd 100644
--- a/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonGenPredicate.cpp
@@ -133,7 +133,7 @@
"Hexagon generate predicate operations", false, false)
bool HexagonGenPredicate::isPredReg(unsigned R) {
- if (!TargetRegisterInfo::isVirtualRegister(R))
+ if (!Register::isVirtualRegister(R))
return false;
const TargetRegisterClass *RC = MRI->getRegClass(R);
return RC == &Hexagon::PredRegsRegClass;
@@ -213,7 +213,7 @@
case TargetOpcode::COPY:
if (isPredReg(MI->getOperand(1).getReg())) {
RegisterSubReg RD = MI->getOperand(0);
- if (TargetRegisterInfo::isVirtualRegister(RD.R))
+ if (Register::isVirtualRegister(RD.R))
PredGPRs.insert(RD);
}
break;
@@ -245,7 +245,7 @@
// Create a predicate register for a given Reg. The newly created register
// will have its value copied from Reg, so that it can be later used as
// an operand in other instructions.
- assert(TargetRegisterInfo::isVirtualRegister(Reg.R));
+ assert(Register::isVirtualRegister(Reg.R));
RegToRegMap::iterator F = G2P.find(Reg);
if (F != G2P.end())
return F->second;
@@ -471,9 +471,9 @@
continue;
RegisterSubReg DR = MI.getOperand(0);
RegisterSubReg SR = MI.getOperand(1);
- if (!TargetRegisterInfo::isVirtualRegister(DR.R))
+ if (!Register::isVirtualRegister(DR.R))
continue;
- if (!TargetRegisterInfo::isVirtualRegister(SR.R))
+ if (!Register::isVirtualRegister(SR.R))
continue;
if (MRI->getRegClass(DR.R) != PredRC)
continue;
diff --git a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
index cecbaed..5c68d22 100644
--- a/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonHardwareLoops.cpp
@@ -1431,7 +1431,7 @@
unsigned Reg = InitVal->getReg();
// We don't know the value of a physical register.
- if (!TargetRegisterInfo::isVirtualRegister(Reg))
+ if (!Register::isVirtualRegister(Reg))
return true;
MachineInstr *Def = MRI->getVRegDef(Reg);
@@ -1509,7 +1509,7 @@
int64_t TV;
unsigned R = MO.getReg();
- if (!TargetRegisterInfo::isVirtualRegister(R))
+ if (!Register::isVirtualRegister(R))
return false;
MachineInstr *DI = MRI->getVRegDef(R);
unsigned DOpc = DI->getOpcode();
diff --git a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
index a156de5..135fb8e 100644
--- a/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonInstrInfo.cpp
@@ -2094,12 +2094,12 @@
if (RegA == RegB)
return true;
- if (TargetRegisterInfo::isPhysicalRegister(RegA))
+ if (Register::isPhysicalRegister(RegA))
for (MCSubRegIterator SubRegs(RegA, &HRI); SubRegs.isValid(); ++SubRegs)
if (RegB == *SubRegs)
return true;
- if (TargetRegisterInfo::isPhysicalRegister(RegB))
+ if (Register::isPhysicalRegister(RegB))
for (MCSubRegIterator SubRegs(RegB, &HRI); SubRegs.isValid(); ++SubRegs)
if (RegA == *SubRegs)
return true;
@@ -4091,7 +4091,7 @@
// Get DefIdx and UseIdx for super registers.
const MachineOperand &DefMO = DefMI.getOperand(DefIdx);
- if (DefMO.isReg() && HRI.isPhysicalRegister(DefMO.getReg())) {
+ if (DefMO.isReg() && Register::isPhysicalRegister(DefMO.getReg())) {
if (DefMO.isImplicit()) {
for (MCSuperRegIterator SR(DefMO.getReg(), &HRI); SR.isValid(); ++SR) {
int Idx = DefMI.findRegisterDefOperandIdx(*SR, false, false, &HRI);
diff --git a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
index db44901..1c038e3 100644
--- a/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonNewValueJump.cpp
@@ -290,7 +290,7 @@
// at machine code level, we don't need this, but if we decide
// to move new value jump prior to RA, we would be needing this.
MachineRegisterInfo &MRI = MF.getRegInfo();
- if (secondReg && !TargetRegisterInfo::isPhysicalRegister(cmpOp2)) {
+ if (secondReg && !Register::isPhysicalRegister(cmpOp2)) {
MachineInstr *def = MRI.getVRegDef(cmpOp2);
if (def->getOpcode() == TargetOpcode::COPY)
return false;
@@ -516,7 +516,7 @@
jmpPos = MII;
jmpInstr = &MI;
predReg = MI.getOperand(0).getReg();
- afterRA = TargetRegisterInfo::isPhysicalRegister(predReg);
+ afterRA = Register::isPhysicalRegister(predReg);
// If ifconverter had not messed up with the kill flags of the
// operands, the following check on the kill flag would suffice.
diff --git a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
index 8f761d2..2748e45 100644
--- a/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonPeephole.cpp
@@ -139,8 +139,8 @@
unsigned DstReg = Dst.getReg();
unsigned SrcReg = Src.getReg();
// Just handle virtual registers.
- if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
- TargetRegisterInfo::isVirtualRegister(SrcReg)) {
+ if (Register::isVirtualRegister(DstReg) &&
+ Register::isVirtualRegister(SrcReg)) {
// Map the following:
// %170 = SXTW %166
// PeepholeMap[170] = %166
@@ -188,8 +188,8 @@
unsigned DstReg = Dst.getReg();
unsigned SrcReg = Src.getReg();
// Just handle virtual registers.
- if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
- TargetRegisterInfo::isVirtualRegister(SrcReg)) {
+ if (Register::isVirtualRegister(DstReg) &&
+ Register::isVirtualRegister(SrcReg)) {
// Map the following:
// %170 = NOT_xx %166
// PeepholeMap[170] = %166
@@ -210,8 +210,8 @@
unsigned DstReg = Dst.getReg();
unsigned SrcReg = Src.getReg();
- if (TargetRegisterInfo::isVirtualRegister(DstReg) &&
- TargetRegisterInfo::isVirtualRegister(SrcReg)) {
+ if (Register::isVirtualRegister(DstReg) &&
+ Register::isVirtualRegister(SrcReg)) {
// Try to find in the map.
if (unsigned PeepholeSrc = PeepholeMap.lookup(SrcReg)) {
// Change the 1st operand.
@@ -242,7 +242,7 @@
if (RC0->getID() == Hexagon::PredRegsRegClassID) {
// Handle instructions that have a prediate register in op0
// (most cases of predicable instructions).
- if (TargetRegisterInfo::isVirtualRegister(Reg0)) {
+ if (Register::isVirtualRegister(Reg0)) {
// Try to find in the map.
if (unsigned PeepholeSrc = PeepholeMap.lookup(Reg0)) {
// Change the 1st operand and, flip the opcode.
diff --git a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
index 013eede..ec9d0b0 100644
--- a/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSplitDouble.cpp
@@ -211,7 +211,7 @@
if (!Op.isReg())
continue;
unsigned R = Op.getReg();
- if (!TargetRegisterInfo::isVirtualRegister(R))
+ if (!Register::isVirtualRegister(R))
return true;
}
return false;
@@ -224,14 +224,14 @@
unsigned NumRegs = MRI->getNumVirtRegs();
BitVector DoubleRegs(NumRegs);
for (unsigned i = 0; i < NumRegs; ++i) {
- unsigned R = TargetRegisterInfo::index2VirtReg(i);
+ unsigned R = Register::index2VirtReg(i);
if (MRI->getRegClass(R) == DoubleRC)
DoubleRegs.set(i);
}
BitVector FixedRegs(NumRegs);
for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) {
- unsigned R = TargetRegisterInfo::index2VirtReg(x);
+ unsigned R = Register::index2VirtReg(x);
MachineInstr *DefI = MRI->getVRegDef(R);
// In some cases a register may exist, but never be defined or used.
// It should never appear anywhere, but mark it as "fixed", just to be
@@ -244,7 +244,7 @@
for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) {
if (FixedRegs[x])
continue;
- unsigned R = TargetRegisterInfo::index2VirtReg(x);
+ unsigned R = Register::index2VirtReg(x);
LLVM_DEBUG(dbgs() << printReg(R, TRI) << " ~~");
USet &Asc = AssocMap[R];
for (auto U = MRI->use_nodbg_begin(R), Z = MRI->use_nodbg_end();
@@ -259,13 +259,13 @@
if (&MO == &Op || !MO.isReg() || MO.getSubReg())
continue;
unsigned T = MO.getReg();
- if (!TargetRegisterInfo::isVirtualRegister(T)) {
+ if (!Register::isVirtualRegister(T)) {
FixedRegs.set(x);
continue;
}
if (MRI->getRegClass(T) != DoubleRC)
continue;
- unsigned u = TargetRegisterInfo::virtReg2Index(T);
+ unsigned u = Register::virtReg2Index(T);
if (FixedRegs[u])
continue;
LLVM_DEBUG(dbgs() << ' ' << printReg(T, TRI));
@@ -281,7 +281,7 @@
unsigned NextP = 1;
USet Visited;
for (int x = DoubleRegs.find_first(); x >= 0; x = DoubleRegs.find_next(x)) {
- unsigned R = TargetRegisterInfo::index2VirtReg(x);
+ unsigned R = Register::index2VirtReg(x);
if (Visited.count(R))
continue;
// Create a new partition for R.
@@ -400,7 +400,7 @@
}
int32_t HexagonSplitDoubleRegs::profit(unsigned Reg) const {
- assert(TargetRegisterInfo::isVirtualRegister(Reg));
+ assert(Register::isVirtualRegister(Reg));
const MachineInstr *DefI = MRI->getVRegDef(Reg);
switch (DefI->getOpcode()) {
@@ -605,7 +605,7 @@
// For register operands, set the subregister.
unsigned R = Op.getReg();
unsigned SR = Op.getSubReg();
- bool isVirtReg = TargetRegisterInfo::isVirtualRegister(R);
+ bool isVirtReg = Register::isVirtualRegister(R);
bool isKill = Op.isKill();
if (isVirtReg && MRI->getRegClass(R) == DoubleRC) {
isKill = false;
@@ -1105,7 +1105,7 @@
if (!Op.isReg() || !Op.isUse())
continue;
unsigned R = Op.getReg();
- if (!TargetRegisterInfo::isVirtualRegister(R))
+ if (!Register::isVirtualRegister(R))
continue;
if (MRI->getRegClass(R) != DoubleRC || Op.getSubReg())
continue;
diff --git a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
index 7ec63a64..31dac55 100644
--- a/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonSubtarget.cpp
@@ -230,7 +230,7 @@
else if (SchedRetvalOptimization) {
const MachineInstr *MI = DAG->SUnits[su].getInstr();
if (MI->isCopy() &&
- TargetRegisterInfo::isPhysicalRegister(MI->getOperand(1).getReg())) {
+ Register::isPhysicalRegister(MI->getOperand(1).getReg())) {
// %vregX = COPY %r0
VRegHoldingReg[MI->getOperand(0).getReg()] = MI->getOperand(1).getReg();
LastVRegUse.erase(MI->getOperand(1).getReg());
@@ -243,8 +243,7 @@
VRegHoldingReg.count(MO.getReg())) {
// <use of %vregX>
LastVRegUse[VRegHoldingReg[MO.getReg()]] = &DAG->SUnits[su];
- } else if (MO.isDef() &&
- TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
+ } else if (MO.isDef() && Register::isPhysicalRegister(MO.getReg())) {
for (MCRegAliasIterator AI(MO.getReg(), &TRI, true); AI.isValid();
++AI) {
if (LastVRegUse.count(*AI) &&
diff --git a/llvm/lib/Target/Hexagon/RDFCopy.cpp b/llvm/lib/Target/Hexagon/RDFCopy.cpp
index 7702024..a9d39fd 100644
--- a/llvm/lib/Target/Hexagon/RDFCopy.cpp
+++ b/llvm/lib/Target/Hexagon/RDFCopy.cpp
@@ -45,8 +45,8 @@
const MachineOperand &Src = MI->getOperand(1);
RegisterRef DstR = DFG.makeRegRef(Dst.getReg(), Dst.getSubReg());
RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg());
- assert(TargetRegisterInfo::isPhysicalRegister(DstR.Reg));
- assert(TargetRegisterInfo::isPhysicalRegister(SrcR.Reg));
+ assert(Register::isPhysicalRegister(DstR.Reg));
+ assert(Register::isPhysicalRegister(SrcR.Reg));
const TargetRegisterInfo &TRI = DFG.getTRI();
if (TRI.getMinimalPhysRegClass(DstR.Reg) !=
TRI.getMinimalPhysRegClass(SrcR.Reg))
diff --git a/llvm/lib/Target/Hexagon/RDFGraph.cpp b/llvm/lib/Target/Hexagon/RDFGraph.cpp
index 9d8f706..7b1a400 100644
--- a/llvm/lib/Target/Hexagon/RDFGraph.cpp
+++ b/llvm/lib/Target/Hexagon/RDFGraph.cpp
@@ -963,7 +963,7 @@
RegisterRef DataFlowGraph::makeRegRef(unsigned Reg, unsigned Sub) const {
assert(PhysicalRegisterInfo::isRegMaskId(Reg) ||
- TargetRegisterInfo::isPhysicalRegister(Reg));
+ Register::isPhysicalRegister(Reg));
assert(Reg != 0);
if (Sub != 0)
Reg = TRI.getSubReg(Reg, Sub);
@@ -1292,7 +1292,7 @@
if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
continue;
unsigned R = Op.getReg();
- if (!R || !TargetRegisterInfo::isPhysicalRegister(R))
+ if (!R || !Register::isPhysicalRegister(R))
continue;
uint16_t Flags = NodeAttrs::None;
if (TOI.isPreserving(In, OpN)) {
@@ -1337,7 +1337,7 @@
if (!Op.isReg() || !Op.isDef() || !Op.isImplicit())
continue;
unsigned R = Op.getReg();
- if (!R || !TargetRegisterInfo::isPhysicalRegister(R) || DoneDefs.test(R))
+ if (!R || !Register::isPhysicalRegister(R) || DoneDefs.test(R))
continue;
RegisterRef RR = makeRegRef(Op);
uint16_t Flags = NodeAttrs::None;
@@ -1366,7 +1366,7 @@
if (!Op.isReg() || !Op.isUse())
continue;
unsigned R = Op.getReg();
- if (!R || !TargetRegisterInfo::isPhysicalRegister(R))
+ if (!R || !Register::isPhysicalRegister(R))
continue;
uint16_t Flags = NodeAttrs::None;
if (Op.isUndef())
diff --git a/llvm/lib/Target/Hexagon/RDFLiveness.cpp b/llvm/lib/Target/Hexagon/RDFLiveness.cpp
index 9cd304aa..ed8f08f 100644
--- a/llvm/lib/Target/Hexagon/RDFLiveness.cpp
+++ b/llvm/lib/Target/Hexagon/RDFLiveness.cpp
@@ -890,7 +890,7 @@
if (!Op.isReg() || !Op.isDef() || Op.isImplicit())
continue;
unsigned R = Op.getReg();
- if (!TargetRegisterInfo::isPhysicalRegister(R))
+ if (!Register::isPhysicalRegister(R))
continue;
for (MCSubRegIterator SR(R, &TRI, true); SR.isValid(); ++SR)
Live.reset(*SR);
@@ -899,7 +899,7 @@
if (!Op.isReg() || !Op.isUse() || Op.isUndef())
continue;
unsigned R = Op.getReg();
- if (!TargetRegisterInfo::isPhysicalRegister(R))
+ if (!Register::isPhysicalRegister(R))
continue;
bool IsLive = false;
for (MCRegAliasIterator AR(R, &TRI, true); AR.isValid(); ++AR) {
diff --git a/llvm/lib/Target/Hexagon/RDFRegisters.cpp b/llvm/lib/Target/Hexagon/RDFRegisters.cpp
index 6e0f336..b567578 100644
--- a/llvm/lib/Target/Hexagon/RDFRegisters.cpp
+++ b/llvm/lib/Target/Hexagon/RDFRegisters.cpp
@@ -101,7 +101,7 @@
std::set<RegisterId> PhysicalRegisterInfo::getAliasSet(RegisterId Reg) const {
// Do not include RR in the alias set.
std::set<RegisterId> AS;
- assert(isRegMaskId(Reg) || TargetRegisterInfo::isPhysicalRegister(Reg));
+ assert(isRegMaskId(Reg) || Register::isPhysicalRegister(Reg));
if (isRegMaskId(Reg)) {
// XXX SLOW
const uint32_t *MB = getRegMaskBits(Reg);
@@ -129,8 +129,8 @@
}
bool PhysicalRegisterInfo::aliasRR(RegisterRef RA, RegisterRef RB) const {
- assert(TargetRegisterInfo::isPhysicalRegister(RA.Reg));
- assert(TargetRegisterInfo::isPhysicalRegister(RB.Reg));
+ assert(Register::isPhysicalRegister(RA.Reg));
+ assert(Register::isPhysicalRegister(RB.Reg));
MCRegUnitMaskIterator UMA(RA.Reg, &TRI);
MCRegUnitMaskIterator UMB(RB.Reg, &TRI);
@@ -160,7 +160,7 @@
}
bool PhysicalRegisterInfo::aliasRM(RegisterRef RR, RegisterRef RM) const {
- assert(TargetRegisterInfo::isPhysicalRegister(RR.Reg) && isRegMaskId(RM.Reg));
+ assert(Register::isPhysicalRegister(RR.Reg) && isRegMaskId(RM.Reg));
const uint32_t *MB = getRegMaskBits(RM.Reg);
bool Preserved = MB[RR.Reg/32] & (1u << (RR.Reg%32));
// If the lane mask information is "full", e.g. when the given lane mask
diff --git a/llvm/lib/Target/Hexagon/RDFRegisters.h b/llvm/lib/Target/Hexagon/RDFRegisters.h
index 646233b..4afaf80 100644
--- a/llvm/lib/Target/Hexagon/RDFRegisters.h
+++ b/llvm/lib/Target/Hexagon/RDFRegisters.h
@@ -99,15 +99,15 @@
const MachineFunction &mf);
static bool isRegMaskId(RegisterId R) {
- return TargetRegisterInfo::isStackSlot(R);
+ return Register::isStackSlot(R);
}
RegisterId getRegMaskId(const uint32_t *RM) const {
- return TargetRegisterInfo::index2StackSlot(RegMasks.find(RM));
+ return Register::index2StackSlot(RegMasks.find(RM));
}
const uint32_t *getRegMaskBits(RegisterId R) const {
- return RegMasks.get(TargetRegisterInfo::stackSlot2Index(R));
+ return RegMasks.get(Register::stackSlot2Index(R));
}
RegisterRef normalize(RegisterRef RR) const;
@@ -125,7 +125,7 @@
}
const BitVector &getMaskUnits(RegisterId MaskId) const {
- return MaskInfos[TargetRegisterInfo::stackSlot2Index(MaskId)].Units;
+ return MaskInfos[Register::stackSlot2Index(MaskId)].Units;
}
RegisterRef mapTo(RegisterRef RR, unsigned R) const;
