tree e514177e5c660e11d1d4ad73e838635aef60e43c
parent 338c1b701f23888eed67ca7e3214db175940df21
author Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> 1620239167 -0700
committer Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> 1620315626 -0700

[AMDGPU] Fix 64 bit DPP validation

AMDGPUAsmParser::isSupportedDPPCtrl() was failing to correctly
find a DPP register operand, regadless of the position it is
always src0. Moved this check into a new validateDPP() method
where we have full instruction already. In particular it was
failing to reject this case:

v_cvt_u32_f64 v5, v[0:1] quad_perm:[0,2,1,1] row_mask:0xf bank_mask:0xf

Essentially it was broken for any case where size of dst and
src0 differ.

It also improves the diagnostics with a proper error message.

The check in the InstPrinter also drops verification of the dst
register as it does not have anything to do with the dpp operand.

Differential Revision: https://reviews.llvm.org/D101930