)]}'
{
  "commit": "256a4e03b7f4fb2b3a6865ff75385305e4cc8e73",
  "tree": "181a7712cdbeb820dd22cc81239620ed6da76263",
  "parents": [
    "20fe74ebe19c844079f7093eeb945994274737a1"
  ],
  "author": {
    "name": "Anshil Gandhi",
    "email": "95053726+gandhi56@users.noreply.github.com",
    "time": "Mon Mar 23 10:06:51 2026 -0400"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Mon Mar 23 10:06:51 2026 -0400"
  },
  "message": "[AMDGPU][GlobalISel] Add RegBankLegalize rules for permlane16_swap/permlane32_swap (#187810)\n\nAdd register bank legalize rules for the amdgcn_permlane16_swap and\namdgcn_permlane32_swap intrinsics. Both results and both source register\noperands map to VGPR since these are VALU lane swap operations.\n\nEnable -new-reg-bank-select in the permlane16.swap and permlane32.swap\ntests.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "2e87460844e3cbff1b0eab6aaa950d92645f0035",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp",
      "new_id": "329fb88adac7af8b37631cabc90fcae368f3363c",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp"
    },
    {
      "type": "modify",
      "old_id": "ed6a02b62ae9a120a355a837da3459d19eaf2aba",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll",
      "new_id": "9ec3314847fe1d82c00acac09097066fffe33844",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane16.swap.ll"
    },
    {
      "type": "modify",
      "old_id": "1ad90013b68d4f4781c9855a31239f4723b9c59e",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll",
      "new_id": "cbfcf7d937e0d7d166b7ef5363aad1bd43ad7f64",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/AMDGPU/llvm.amdgcn.permlane32.swap.ll"
    }
  ]
}