[AArch64] Correct SCVTF/UCVTF instructions for vector input (#152974) This pull request improves support for scalar floating-point conversions from integer vectors on AArch64, specifically for the `scvtf` and `ucvtf` instructions. It fixes pattern matching so that single-element conversions from vectors now generate the expected scalar instructions and adds a new test to verify correct behavior for extracting a lane from a widened vector. **Pattern matching and code generation improvements:** * Added new patterns in `AArch64InstrInfo.td` to correctly match conversions from `v2i32` to `v1f64` using `scvtf` and `ucvtf`, ensuring the scalar instructions (`scvtf d0, s0` and `ucvtf d0, s0`) are generated when extracting a single lane. **Test updates and additions:** * Updated `scvtf_f64i32_simple` and `ucvtf_f64i32_simple` tests in `fprcvt-cvtf.ll` to reflect the correct generation of scalar instructions, removing previous comments about incorrect codegen and showing the expected output. * Added a new test `uitofp_sext_v2i32_extract_lane0` to verify correct code generation when extracting a lane from a widened vector and converting to double.
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