[FPEnv][X86] Constrained FCmp intrinsics enabling on X86
Summary: This is a follow up of D69281, it enables the X86 backend support for the FP comparision.
Reviewers: uweigand, kpn, craig.topper, RKSimon, cameron.mcinally, andrew.w.kaylor
Subscribers: hiraditya, llvm-commits, annita.zhang, LuoYuanke, LiuChen3
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D70582
diff --git a/llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll b/llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll
new file mode 100644
index 0000000..df214c5
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fp-strict-scalar-cmp.ll
@@ -0,0 +1,3063 @@
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+sse2 -O3 | FileCheck %s --check-prefixes=CHECK-32
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 -O3 | FileCheck %s --check-prefixes=CHECK-64
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK-32
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK-64
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+avx512f -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=CHECK-32
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=CHECK-64
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=-sse -O3 | FileCheck %s --check-prefixes=X87
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=-sse,+cmov -O3 | FileCheck %s --check-prefixes=X87-CMOV
+
+define i32 @test_f32_oeq_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_oeq_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_oeq_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %esi, %eax
+; CHECK-64-NEXT: cmovpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_oeq_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: jne .LBB0_3
+; X87-NEXT: # %bb.1:
+; X87-NEXT: jp .LBB0_3
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: .LBB0_3:
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_oeq_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ogt_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ogt_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmoval %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ogt_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovbel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ogt_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: ja .LBB1_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB1_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ogt_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmoval %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_oge_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_oge_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovael %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_oge_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovbl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_oge_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jae .LBB2_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB2_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_oge_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovael %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_olt_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_olt_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmoval %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_olt_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm0, %xmm1
+; CHECK-64-NEXT: cmovbel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_olt_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: ja .LBB3_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB3_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_olt_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmoval %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ole_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ole_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovael %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ole_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm0, %xmm1
+; CHECK-64-NEXT: cmovbl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ole_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jae .LBB4_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB4_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ole_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovael %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_one_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_one_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_one_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_one_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jne .LBB5_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB5_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_one_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ord_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ord_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ord_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ord_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jnp .LBB6_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB6_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ord_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ueq_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ueq_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ueq_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ueq_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: je .LBB7_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB7_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ueq_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ugt_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ugt_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ugt_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm0, %xmm1
+; CHECK-64-NEXT: cmovael %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ugt_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jb .LBB8_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB8_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ugt_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_uge_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_uge_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_uge_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm0, %xmm1
+; CHECK-64-NEXT: cmoval %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_uge_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jbe .LBB9_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB9_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_uge_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ult_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ult_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ult_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovael %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ult_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jb .LBB10_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB10_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ult_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ule_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ule_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ule_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmoval %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ule_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jbe .LBB11_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB11_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ule_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_une_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_une_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_une_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %esi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %edi, %eax
+; CHECK-64-NEXT: cmovpl %edi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_une_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: jne .LBB12_3
+; X87-NEXT: # %bb.1:
+; X87-NEXT: jp .LBB12_3
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: .LBB12_3:
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_une_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_uno_q(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_uno_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}ucomiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_uno_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_uno_q:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jp .LBB13_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB13_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_uno_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(
+ float %f1, float %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_oeq_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_oeq_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_oeq_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %esi, %eax
+; CHECK-64-NEXT: cmovpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_oeq_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: jne .LBB14_3
+; X87-NEXT: # %bb.1:
+; X87-NEXT: jp .LBB14_3
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: .LBB14_3:
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_oeq_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ogt_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ogt_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmoval %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ogt_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovbel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ogt_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: ja .LBB15_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB15_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ogt_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmoval %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_oge_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_oge_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovael %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_oge_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovbl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_oge_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jae .LBB16_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB16_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_oge_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovael %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_olt_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_olt_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmoval %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_olt_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm0, %xmm1
+; CHECK-64-NEXT: cmovbel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_olt_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: ja .LBB17_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB17_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_olt_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmoval %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ole_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ole_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovael %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ole_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm0, %xmm1
+; CHECK-64-NEXT: cmovbl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ole_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jae .LBB18_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB18_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ole_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovael %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_one_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_one_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_one_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_one_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jne .LBB19_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB19_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_one_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ord_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ord_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ord_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ord_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jnp .LBB20_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB20_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ord_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ueq_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ueq_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ueq_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ueq_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: je .LBB21_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB21_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ueq_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ugt_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ugt_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ugt_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm0, %xmm1
+; CHECK-64-NEXT: cmovael %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ugt_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jb .LBB22_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB22_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ugt_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_uge_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_uge_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_uge_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm0, %xmm1
+; CHECK-64-NEXT: cmoval %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_uge_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jbe .LBB23_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB23_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_uge_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ult_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ult_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ult_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovael %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ult_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jb .LBB24_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB24_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ult_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ule_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ule_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ule_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmoval %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ule_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jbe .LBB25_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB25_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ule_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_une_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_une_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_une_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %esi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %edi, %eax
+; CHECK-64-NEXT: cmovpl %edi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_une_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: jne .LBB26_3
+; X87-NEXT: # %bb.1:
+; X87-NEXT: jp .LBB26_3
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: .LBB26_3:
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_une_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_uno_q(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_uno_q:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}ucomisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_uno_q:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}ucomisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_uno_q:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fucompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jp .LBB27_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB27_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_uno_q:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fucompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmp.f64(
+ double %f1, double %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_oeq_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_oeq_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_oeq_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %esi, %eax
+; CHECK-64-NEXT: cmovpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_oeq_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: jne .LBB28_3
+; X87-NEXT: # %bb.1:
+; X87-NEXT: jp .LBB28_3
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: .LBB28_3:
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_oeq_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ogt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ogt_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmoval %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ogt_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovbel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ogt_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: ja .LBB29_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB29_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ogt_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmoval %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_oge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_oge_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovael %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_oge_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovbl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_oge_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jae .LBB30_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB30_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_oge_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovael %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_olt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_olt_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmoval %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_olt_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm0, %xmm1
+; CHECK-64-NEXT: cmovbel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_olt_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: ja .LBB31_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB31_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_olt_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmoval %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ole_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ole_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovael %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ole_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm0, %xmm1
+; CHECK-64-NEXT: cmovbl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ole_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jae .LBB32_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB32_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ole_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovael %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_one_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_one_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_one_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_one_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jne .LBB33_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB33_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_one_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ord_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ord_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ord_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ord_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jnp .LBB34_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB34_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ord_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ueq_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ueq_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ueq_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ueq_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: je .LBB35_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB35_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ueq_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ugt_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ugt_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ugt_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm0, %xmm1
+; CHECK-64-NEXT: cmovael %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ugt_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jb .LBB36_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB36_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ugt_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_uge_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_uge_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_uge_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm0, %xmm1
+; CHECK-64-NEXT: cmoval %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_uge_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jbe .LBB37_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB37_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_uge_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ult_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ult_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ult_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovael %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ult_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jb .LBB38_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB38_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ult_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_ule_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_ule_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_ule_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmoval %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_ule_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jbe .LBB39_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB39_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_ule_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_une_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_une_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_une_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %esi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %edi, %eax
+; CHECK-64-NEXT: cmovpl %edi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_une_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: jne .LBB40_3
+; X87-NEXT: # %bb.1:
+; X87-NEXT: jp .LBB40_3
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: .LBB40_3:
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_une_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f32_uno_s(i32 %a, i32 %b, float %f1, float %f2) #0 {
+; CHECK-32-LABEL: test_f32_uno_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; CHECK-32-NEXT: {{v?}}comiss {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f32_uno_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comiss %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f32_uno_s:
+; X87: # %bb.0:
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: flds {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jp .LBB41_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB41_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f32_uno_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: flds {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(
+ float %f1, float %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_oeq_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_oeq_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_oeq_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %esi, %eax
+; CHECK-64-NEXT: cmovpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_oeq_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: jne .LBB42_3
+; X87-NEXT: # %bb.1:
+; X87-NEXT: jp .LBB42_3
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: .LBB42_3:
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_oeq_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ogt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ogt_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmoval %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ogt_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovbel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ogt_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: ja .LBB43_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB43_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ogt_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmoval %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_oge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_oge_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovael %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_oge_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovbl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_oge_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jae .LBB44_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB44_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_oge_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovael %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_olt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_olt_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmoval %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_olt_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm0, %xmm1
+; CHECK-64-NEXT: cmovbel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_olt_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: ja .LBB45_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB45_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_olt_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmoval %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ole_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ole_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovael %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ole_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm0, %xmm1
+; CHECK-64-NEXT: cmovbl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ole_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jae .LBB46_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB46_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ole_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovael %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_one_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_one_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_one_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_one_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jne .LBB47_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB47_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_one_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ord_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ord_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ord_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ord_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jnp .LBB48_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB48_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ord_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ueq_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ueq_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ueq_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ueq_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: je .LBB49_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB49_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ueq_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ugt_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ugt_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ugt_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm0, %xmm1
+; CHECK-64-NEXT: cmovael %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ugt_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jb .LBB50_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB50_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ugt_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_uge_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_uge_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_uge_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm0, %xmm1
+; CHECK-64-NEXT: cmoval %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_uge_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jbe .LBB51_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB51_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_uge_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ult_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ult_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ult_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovael %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ult_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jb .LBB52_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB52_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ult_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_ule_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_ule_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovbel %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_ule_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmoval %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_ule_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jbe .LBB53_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB53_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_ule_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovbel %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_une_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_une_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovnel %eax, %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_une_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %esi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnel %edi, %eax
+; CHECK-64-NEXT: cmovpl %edi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_une_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: jne .LBB54_3
+; X87-NEXT: # %bb.1:
+; X87-NEXT: jp .LBB54_3
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: .LBB54_3:
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_une_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovnel %eax, %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_f64_uno_s(i32 %a, i32 %b, double %f1, double %f2) #0 {
+; CHECK-32-LABEL: test_f64_uno_s:
+; CHECK-32: # %bb.0:
+; CHECK-32-NEXT: {{v?}}movsd {{.*#+}} xmm0 = mem[0],zero
+; CHECK-32-NEXT: {{v?}}comisd {{[0-9]+}}(%esp), %xmm0
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; CHECK-32-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; CHECK-32-NEXT: cmovpl %eax, %ecx
+; CHECK-32-NEXT: movl (%ecx), %eax
+; CHECK-32-NEXT: retl
+;
+; CHECK-64-LABEL: test_f64_uno_s:
+; CHECK-64: # %bb.0:
+; CHECK-64-NEXT: movl %edi, %eax
+; CHECK-64-NEXT: {{v?}}comisd %xmm1, %xmm0
+; CHECK-64-NEXT: cmovnpl %esi, %eax
+; CHECK-64-NEXT: retq
+;
+; X87-LABEL: test_f64_uno_s:
+; X87: # %bb.0:
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-NEXT: fcompp
+; X87-NEXT: fnstsw %ax
+; X87-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-NEXT: sahf
+; X87-NEXT: jp .LBB55_1
+; X87-NEXT: # %bb.2:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+; X87-NEXT: .LBB55_1:
+; X87-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-NEXT: movl (%eax), %eax
+; X87-NEXT: retl
+;
+; X87-CMOV-LABEL: test_f64_uno_s:
+; X87-CMOV: # %bb.0:
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fldl {{[0-9]+}}(%esp)
+; X87-CMOV-NEXT: fcompi %st(1), %st
+; X87-CMOV-NEXT: fstp %st(0)
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-CMOV-NEXT: leal {{[0-9]+}}(%esp), %ecx
+; X87-CMOV-NEXT: cmovpl %eax, %ecx
+; X87-CMOV-NEXT: movl (%ecx), %eax
+; X87-CMOV-NEXT: retl
+ %cond = call i1 @llvm.experimental.constrained.fcmps.f64(
+ double %f1, double %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+attributes #0 = { strictfp }
+
+declare i1 @llvm.experimental.constrained.fcmp.test_f32_olt_s(float, float, metadata, metadata)
+declare i1 @llvm.experimental.constrained.fcmp.f64(double, double, metadata, metadata)
+declare i1 @llvm.experimental.constrained.fcmps.test_f32_olt_s(float, float, metadata, metadata)
+declare i1 @llvm.experimental.constrained.fcmps.f64(double, double, metadata, metadata)
diff --git a/llvm/test/CodeGen/X86/fp80-strict-scalar-cmp.ll b/llvm/test/CodeGen/X86/fp80-strict-scalar-cmp.ll
new file mode 100644
index 0000000..6d53aff
--- /dev/null
+++ b/llvm/test/CodeGen/X86/fp80-strict-scalar-cmp.ll
@@ -0,0 +1,992 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=-sse -O3 | FileCheck %s --check-prefixes=CHECK,X87-32
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -O3 | FileCheck %s --check-prefixes=CHECK,X87-64
+
+define i32 @test_oeq_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_oeq_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: jne .LBB0_3
+; X87-32-NEXT: # %bb.1:
+; X87-32-NEXT: jp .LBB0_3
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: .LBB0_3:
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_oeq_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovnel %esi, %eax
+; X87-64-NEXT: cmovpl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ogt_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ogt_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: ja .LBB1_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB1_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ogt_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovbel %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_oge_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_oge_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jae .LBB2_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB2_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_oge_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovbl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_olt_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_olt_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: ja .LBB3_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB3_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_olt_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovbel %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ole_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ole_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jae .LBB4_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB4_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ole_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovbl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_one_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_one_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jne .LBB5_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB5_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_one_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovel %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ord_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ord_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jnp .LBB6_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB6_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ord_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovpl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ueq_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ueq_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: je .LBB7_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB7_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ueq_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovnel %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ugt_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ugt_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jb .LBB8_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB8_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ugt_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovael %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_uge_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_uge_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jbe .LBB9_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB9_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_uge_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmoval %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ult_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ult_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jb .LBB10_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB10_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ult_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovael %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ule_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ule_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jbe .LBB11_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB11_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ule_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmoval %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_une_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_une_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: jne .LBB12_3
+; X87-32-NEXT: # %bb.1:
+; X87-32-NEXT: jp .LBB12_3
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: .LBB12_3:
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_une_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %esi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovnel %edi, %eax
+; X87-64-NEXT: cmovpl %edi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_uno_q(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_uno_q:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fucompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jp .LBB13_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB13_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_uno_q:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fucompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovnpl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmp.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_oeq_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_oeq_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: jne .LBB14_3
+; X87-32-NEXT: # %bb.1:
+; X87-32-NEXT: jp .LBB14_3
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: .LBB14_3:
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_oeq_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovnel %esi, %eax
+; X87-64-NEXT: cmovpl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ogt_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ogt_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: ja .LBB15_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB15_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ogt_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovbel %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_oge_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_oge_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jae .LBB16_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB16_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_oge_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovbl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_olt_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_olt_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: ja .LBB17_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB17_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_olt_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovbel %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ole_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ole_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jae .LBB18_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB18_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ole_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovbl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_one_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_one_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jne .LBB19_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB19_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_one_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovel %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ord_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ord_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jnp .LBB20_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB20_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ord_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovpl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ueq_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ueq_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: je .LBB21_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB21_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ueq_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovnel %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ugt_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ugt_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jb .LBB22_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB22_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ugt_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovael %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_uge_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_uge_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jbe .LBB23_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB23_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_uge_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmoval %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ult_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ult_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jb .LBB24_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB24_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ult_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovael %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_ule_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_ule_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jbe .LBB25_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB25_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_ule_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmoval %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_une_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_une_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: jne .LBB26_3
+; X87-32-NEXT: # %bb.1:
+; X87-32-NEXT: jp .LBB26_3
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: .LBB26_3:
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_une_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %esi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovnel %edi, %eax
+; X87-64-NEXT: cmovpl %edi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+define i32 @test_uno_s(i32 %a, i32 %b, x86_fp80 %f1, x86_fp80 %f2) #0 {
+; X87-32-LABEL: test_uno_s:
+; X87-32: # %bb.0:
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fldt {{[0-9]+}}(%esp)
+; X87-32-NEXT: fcompp
+; X87-32-NEXT: fnstsw %ax
+; X87-32-NEXT: # kill: def $ah killed $ah killed $ax
+; X87-32-NEXT: sahf
+; X87-32-NEXT: jp .LBB27_1
+; X87-32-NEXT: # %bb.2:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+; X87-32-NEXT: .LBB27_1:
+; X87-32-NEXT: leal {{[0-9]+}}(%esp), %eax
+; X87-32-NEXT: movl (%eax), %eax
+; X87-32-NEXT: retl
+;
+; X87-64-LABEL: test_uno_s:
+; X87-64: # %bb.0:
+; X87-64-NEXT: movl %edi, %eax
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fldt {{[0-9]+}}(%rsp)
+; X87-64-NEXT: fcompi %st(1), %st
+; X87-64-NEXT: fstp %st(0)
+; X87-64-NEXT: cmovnpl %esi, %eax
+; X87-64-NEXT: retq
+ %cond = call i1 @llvm.experimental.constrained.fcmps.x86_fp80(
+ x86_fp80 %f1, x86_fp80 %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select i1 %cond, i32 %a, i32 %b
+ ret i32 %res
+}
+
+attributes #0 = { strictfp }
+
+declare i1 @llvm.experimental.constrained.fcmp.x86_fp80(x86_fp80, x86_fp80, metadata, metadata)
+declare i1 @llvm.experimental.constrained.fcmps.x86_fp80(x86_fp80, x86_fp80, metadata, metadata)
diff --git a/llvm/test/CodeGen/X86/vec-strict-128-cmp.ll b/llvm/test/CodeGen/X86/vec-strict-128-cmp.ll
new file mode 100644
index 0000000..56320ab
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vec-strict-128-cmp.ll
@@ -0,0 +1,1681 @@
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+sse2 -O3 | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+sse2 -O3 | FileCheck %s --check-prefixes=CHECK,SSE
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+avx512f -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=CHECK,AVX512-32
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=CHECK,AVX512-64
+
+define <4 x i32> @test_v4f32_oeq_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_oeq_q:
+; SSE: # %bb.0:
+; SSE: cmpeqps {{.*}}, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_oeq_q:
+; AVX: # %bb.0:
+; AVX: vcmpeqps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_oeq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_oeq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeqps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ogt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ogt_q:
+; SSE: # %bb.0:
+; SSE: ucomiss %xmm4, %xmm5
+; SSE: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm3[1]
+; SSE: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm2[1]
+; SSE: ucomiss %xmm5, %xmm6
+; SSE: ucomiss %xmm3, %xmm2
+; SSE: ucomiss %xmm3, %xmm2
+;
+; AVX-LABEL: test_v4f32_ogt_q:
+; AVX: # %bb.0:
+; AVX: vcmplt_oqps {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ogt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgt_oqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ogt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqps %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_oge_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_oge_q:
+; SSE: # %bb.0:
+; SSE: ucomiss %xmm4, %xmm5
+; SSE: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm3[1]
+; SSE: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm2[1]
+; SSE: ucomiss %xmm5, %xmm6
+; SSE: ucomiss %xmm3, %xmm2
+; SSE: ucomiss %xmm3, %xmm2
+;
+; AVX-LABEL: test_v4f32_oge_q:
+; AVX: # %bb.0:
+; AVX: vcmple_oqps {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_oge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpge_oqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_oge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqps %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_olt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_olt_q:
+; SSE: # %bb.0:
+; SSE: ucomiss %xmm4, %xmm5
+; SSE: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm2[1]
+; SSE: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm3[1]
+; SSE: ucomiss %xmm5, %xmm6
+; SSE: ucomiss %xmm2, %xmm3
+; SSE: ucomiss %xmm2, %xmm3
+;
+; AVX-LABEL: test_v4f32_olt_q:
+; AVX: # %bb.0:
+; AVX: vcmplt_oqps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_olt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplt_oqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_olt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ole_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ole_q:
+; SSE: # %bb.0:
+; SSE: ucomiss %xmm4, %xmm5
+; SSE: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm2[1]
+; SSE: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm3[1]
+; SSE: ucomiss %xmm5, %xmm6
+; SSE: ucomiss %xmm2, %xmm3
+; SSE: ucomiss %xmm2, %xmm3
+;
+; AVX-LABEL: test_v4f32_ole_q:
+; AVX: # %bb.0:
+; AVX: vcmple_oqps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ole_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmple_oqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ole_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_one_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_one_q:
+; SSE: # %bb.0:
+; SSE: cmpneqps %xmm3, %xmm4
+; SSE-NEXT: cmpordps %xmm3, %xmm2
+; SSE-NEXT: andps %xmm4, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_one_q:
+; AVX: # %bb.0:
+; AVX: vcmpneq_oqps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_one_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_oqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_one_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_oqps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ord_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ord_q:
+; SSE: # %bb.0:
+; SSE: cmpordps {{.*}}, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_ord_q:
+; AVX: # %bb.0:
+; AVX: vcmpordps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ord_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpordps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ord_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpordps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ueq_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ueq_q:
+; SSE: # %bb.0:
+; SSE: cmpeqps %xmm3, %xmm4
+; SSE-NEXT: cmpunordps %xmm3, %xmm2
+; SSE-NEXT: orps %xmm4, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_ueq_q:
+; AVX: # %bb.0:
+; AVX: vcmpeq_uqps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ueq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ueq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uqps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ugt_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ugt_q:
+; SSE: # %bb.0:
+; SSE: ucomiss %xmm4, %xmm5
+; SSE: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm2[1]
+; SSE: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm3[1]
+; SSE: ucomiss %xmm5, %xmm6
+; SSE: ucomiss %xmm2, %xmm3
+; SSE: ucomiss %xmm2, %xmm3
+;
+; AVX-LABEL: test_v4f32_ugt_q:
+; AVX: # %bb.0:
+; AVX: vcmpnle_uqps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ugt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnle_uqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ugt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_uge_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_uge_q:
+; SSE: # %bb.0:
+; SSE: ucomiss %xmm4, %xmm5
+; SSE: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm2[1]
+; SSE: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm3[1]
+; SSE: ucomiss %xmm5, %xmm6
+; SSE: ucomiss %xmm2, %xmm3
+; SSE: ucomiss %xmm2, %xmm3
+;
+; AVX-LABEL: test_v4f32_uge_q:
+; AVX: # %bb.0:
+; AVX: vcmpnlt_uqps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_uge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlt_uqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_uge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ult_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ult_q:
+; SSE: # %bb.0:
+; SSE: ucomiss %xmm4, %xmm5
+; SSE: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm3[1]
+; SSE: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm2[1]
+; SSE: ucomiss %xmm5, %xmm6
+; SSE: ucomiss %xmm3, %xmm2
+; SSE: ucomiss %xmm3, %xmm2
+;
+; AVX-LABEL: test_v4f32_ult_q:
+; AVX: # %bb.0:
+; AVX: vcmpnle_uqps {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ult_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnge_uqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ult_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqps %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ule_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ule_q:
+; SSE: # %bb.0:
+; SSE: ucomiss %xmm4, %xmm5
+; SSE: unpckhpd {{.*#+}} xmm5 = xmm5[1],xmm3[1]
+; SSE: unpckhpd {{.*#+}} xmm6 = xmm6[1],xmm2[1]
+; SSE: ucomiss %xmm5, %xmm6
+; SSE: ucomiss %xmm3, %xmm2
+; SSE: ucomiss %xmm3, %xmm2
+;
+; AVX-LABEL: test_v4f32_ule_q:
+; AVX: # %bb.0:
+; AVX: vcmpnlt_uqps {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ule_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngt_uqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ule_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqps %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_une_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_une_q:
+; SSE: # %bb.0:
+; SSE: cmpneqps {{.*}}, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_une_q:
+; AVX: # %bb.0:
+; AVX: vcmpneqps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_une_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneqps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_une_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneqps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_uno_q(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_uno_q:
+; SSE: # %bb.0:
+; SSE: cmpunordps {{.*}}, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_uno_q:
+; AVX: # %bb.0:
+; AVX: vcmpunordps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_uno_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunordps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_uno_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunordps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <2 x i64> @test_v2f64_oeq_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_oeq_q:
+; SSE: # %bb.0:
+; SSE: cmpeqpd {{.*}}, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_oeq_q:
+; AVX: # %bb.0:
+; AVX: vcmpeqpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_oeq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_oeq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeqpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ogt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ogt_q:
+; SSE: # %bb.0:
+; SSE: ucomisd %xmm3, %xmm2
+; SSE: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
+; SSE: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
+; SSE: ucomisd %xmm3, %xmm2
+;
+; AVX-LABEL: test_v2f64_ogt_q:
+; AVX: # %bb.0:
+; AVX: vcmplt_oqpd {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ogt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgt_oqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ogt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqpd %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_oge_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_oge_q:
+; SSE: # %bb.0:
+; SSE: ucomisd %xmm3, %xmm2
+; SSE: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
+; SSE: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
+; SSE: ucomisd %xmm3, %xmm2
+;
+; AVX-LABEL: test_v2f64_oge_q:
+; AVX: # %bb.0:
+; AVX: vcmple_oqpd {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_oge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpge_oqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_oge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqpd %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_olt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_olt_q:
+; SSE: # %bb.0:
+; SSE: ucomisd %xmm2, %xmm3
+; SSE: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
+; SSE: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
+; SSE: ucomisd %xmm2, %xmm3
+;
+; AVX-LABEL: test_v2f64_olt_q:
+; AVX: # %bb.0:
+; AVX: vcmplt_oqpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_olt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplt_oqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_olt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ole_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ole_q:
+; SSE: # %bb.0:
+; SSE: ucomisd %xmm2, %xmm3
+; SSE: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
+; SSE: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
+; SSE: ucomisd %xmm2, %xmm3
+;
+; AVX-LABEL: test_v2f64_ole_q:
+; AVX: # %bb.0:
+; AVX: vcmple_oqpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ole_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmple_oqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ole_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_one_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_one_q:
+; SSE: # %bb.0:
+; SSE: cmpneqpd %xmm3, %xmm4
+; SSE-NEXT: cmpordpd %xmm3, %xmm2
+; SSE-NEXT: andpd %xmm4, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_one_q:
+; AVX: # %bb.0:
+; AVX: vcmpneq_oqpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_one_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_oqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_one_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_oqpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ord_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ord_q:
+; SSE: # %bb.0:
+; SSE: cmpordpd {{.*}}, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_ord_q:
+; AVX: # %bb.0:
+; AVX: vcmpordpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ord_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpordpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ord_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpordpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ueq_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ueq_q:
+; SSE: # %bb.0:
+; SSE: cmpeqpd %xmm3, %xmm4
+; SSE-NEXT: cmpunordpd %xmm3, %xmm2
+; SSE-NEXT: orpd %xmm4, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_ueq_q:
+; AVX: # %bb.0:
+; AVX: vcmpeq_uqpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ueq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ueq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uqpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ugt_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ugt_q:
+; SSE: # %bb.0:
+; SSE: ucomisd %xmm2, %xmm3
+; SSE: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
+; SSE: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
+; SSE: ucomisd %xmm2, %xmm3
+;
+; AVX-LABEL: test_v2f64_ugt_q:
+; AVX: # %bb.0:
+; AVX: vcmpnle_uqpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ugt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnle_uqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ugt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_uge_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_uge_q:
+; SSE: # %bb.0:
+; SSE: ucomisd %xmm2, %xmm3
+; SSE: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
+; SSE: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
+; SSE: ucomisd %xmm2, %xmm3
+;
+; AVX-LABEL: test_v2f64_uge_q:
+; AVX: # %bb.0:
+; AVX: vcmpnlt_uqpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_uge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlt_uqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_uge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ult_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ult_q:
+; SSE: # %bb.0:
+; SSE: ucomisd %xmm3, %xmm2
+; SSE: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
+; SSE: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
+; SSE: ucomisd %xmm3, %xmm2
+;
+; AVX-LABEL: test_v2f64_ult_q:
+; AVX: # %bb.0:
+; AVX: vcmpnle_uqpd {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ult_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnge_uqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ult_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqpd %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ule_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ule_q:
+; SSE: # %bb.0:
+; SSE: ucomisd %xmm3, %xmm2
+; SSE: unpckhpd {{.*#+}} xmm3 = xmm3[1,1]
+; SSE: unpckhpd {{.*#+}} xmm2 = xmm2[1,1]
+; SSE: ucomisd %xmm3, %xmm2
+;
+; AVX-LABEL: test_v2f64_ule_q:
+; AVX: # %bb.0:
+; AVX: vcmpnlt_uqpd {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ule_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngt_uqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ule_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqpd %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_une_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_une_q:
+; SSE: # %bb.0:
+; SSE: cmpneqpd {{.*}}, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_une_q:
+; AVX: # %bb.0:
+; AVX: vcmpneqpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_une_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneqpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_une_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneqpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_uno_q(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_uno_q:
+; SSE: # %bb.0:
+; SSE: cmpunordpd {{.*}}, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_uno_q:
+; AVX: # %bb.0:
+; AVX: vcmpunordpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_uno_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunordpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_uno_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunordpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <4 x i32> @test_v4f32_oeq_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_oeq_s:
+; SSE: # %bb.0:
+; SSE: cmpltps %xmm3, %xmm4
+; SSE-NEXT: cmpeqps %xmm3, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_oeq_s:
+; AVX: # %bb.0:
+; AVX: vcmpeq_osps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_oeq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_osps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_oeq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_osps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ogt_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ogt_s:
+; SSE: # %bb.0:
+; SSE: cmpltps {{.*}}, %xmm3
+; SSE-NEXT: andps %xmm3, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm3
+; SSE-NEXT: orps %xmm3, %xmm0
+;
+; AVX-LABEL: test_v4f32_ogt_s:
+; AVX: # %bb.0:
+; AVX: vcmpltps {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ogt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgtps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ogt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltps %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_oge_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_oge_s:
+; SSE: # %bb.0:
+; SSE: cmpleps {{.*}}, %xmm3
+; SSE-NEXT: andps %xmm3, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm3
+; SSE-NEXT: orps %xmm3, %xmm0
+;
+; AVX-LABEL: test_v4f32_oge_s:
+; AVX: # %bb.0:
+; AVX: vcmpleps {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_oge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgeps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_oge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpleps %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_olt_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_olt_s:
+; SSE: # %bb.0:
+; SSE: cmpltps {{.*}}, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_olt_s:
+; AVX: # %bb.0:
+; AVX: vcmpltps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_olt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpltps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_olt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ole_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ole_s:
+; SSE: # %bb.0:
+; SSE: cmpleps {{.*}}, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_ole_s:
+; AVX: # %bb.0:
+; AVX: vcmpleps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ole_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpleps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ole_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpleps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_one_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_one_s:
+; SSE: # %bb.0:
+; SSE: cmpltps %xmm3, %xmm4
+; SSE: cmpneqps %xmm3, %xmm4
+; SSE-NEXT: cmpordps %xmm3, %xmm2
+; SSE-NEXT: andps %xmm4, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_one_s:
+; AVX: # %bb.0:
+; AVX: vcmpneq_osps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_one_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_osps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_one_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_osps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ord_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ord_s:
+; SSE: # %bb.0:
+; SSE: cmpltps %xmm3, %xmm4
+; SSE-NEXT: cmpordps %xmm3, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_ord_s:
+; AVX: # %bb.0:
+; AVX: vcmpord_sps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ord_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpord_sps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ord_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpord_sps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ueq_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ueq_s:
+; SSE: # %bb.0:
+; SSE: cmpltps %xmm3, %xmm4
+; SSE: cmpeqps %xmm3, %xmm4
+; SSE-NEXT: cmpunordps %xmm3, %xmm2
+; SSE-NEXT: orps %xmm4, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_ueq_s:
+; AVX: # %bb.0:
+; AVX: vcmpeq_usps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ueq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_usps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ueq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_usps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ugt_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ugt_s:
+; SSE: # %bb.0:
+; SSE: cmpnleps {{.*}}, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_ugt_s:
+; AVX: # %bb.0:
+; AVX: vcmpnleps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ugt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnleps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ugt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnleps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_uge_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_uge_s:
+; SSE: # %bb.0:
+; SSE: cmpnltps {{.*}}, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_uge_s:
+; AVX: # %bb.0:
+; AVX: vcmpnltps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_uge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnltps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_uge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ult_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ult_s:
+; SSE: # %bb.0:
+; SSE: cmpnleps {{.*}}, %xmm3
+; SSE-NEXT: andps %xmm3, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm3
+; SSE-NEXT: orps %xmm3, %xmm0
+;
+; AVX-LABEL: test_v4f32_ult_s:
+; AVX: # %bb.0:
+; AVX: vcmpnleps {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ult_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngeps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ult_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnleps %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_ule_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_ule_s:
+; SSE: # %bb.0:
+; SSE: cmpnltps {{.*}}, %xmm3
+; SSE-NEXT: andps %xmm3, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm3
+; SSE-NEXT: orps %xmm3, %xmm0
+;
+; AVX-LABEL: test_v4f32_ule_s:
+; AVX: # %bb.0:
+; AVX: vcmpnltps {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_ule_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngtps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_ule_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltps %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_une_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_une_s:
+; SSE: # %bb.0:
+; SSE: cmpltps %xmm3, %xmm4
+; SSE-NEXT: cmpneqps %xmm3, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_une_s:
+; AVX: # %bb.0:
+; AVX: vcmpneq_usps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_une_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_usps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_une_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_usps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <4 x i32> @test_v4f32_uno_s(<4 x i32> %a, <4 x i32> %b, <4 x float> %f1, <4 x float> %f2) #0 {
+; SSE-LABEL: test_v4f32_uno_s:
+; SSE: # %bb.0:
+; SSE: cmpltps %xmm3, %xmm4
+; SSE-NEXT: cmpunordps %xmm3, %xmm2
+; SSE-NEXT: andps %xmm2, %xmm0
+; SSE-NEXT: andnps %xmm1, %xmm2
+; SSE-NEXT: orps %xmm2, %xmm0
+;
+; AVX-LABEL: test_v4f32_uno_s:
+; AVX: # %bb.0:
+; AVX: vcmpunord_sps {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvps %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v4f32_uno_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunord_sps 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f32_uno_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunord_sps %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmd %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(
+ <4 x float> %f1, <4 x float> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i32> %a, <4 x i32> %b
+ ret <4 x i32> %res
+}
+
+define <2 x i64> @test_v2f64_oeq_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_oeq_s:
+; SSE: # %bb.0:
+; SSE: cmpltpd %xmm3, %xmm4
+; SSE-NEXT: cmpeqpd %xmm3, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_oeq_s:
+; AVX: # %bb.0:
+; AVX: vcmpeq_ospd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_oeq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_ospd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_oeq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_ospd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ogt_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ogt_s:
+; SSE: # %bb.0:
+; SSE: cmpltpd {{.*}}, %xmm3
+; SSE-NEXT: andpd %xmm3, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm3
+; SSE-NEXT: orpd %xmm3, %xmm0
+;
+; AVX-LABEL: test_v2f64_ogt_s:
+; AVX: # %bb.0:
+; AVX: vcmpltpd {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ogt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgtpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ogt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltpd %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_oge_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_oge_s:
+; SSE: # %bb.0:
+; SSE: cmplepd {{.*}}, %xmm3
+; SSE-NEXT: andpd %xmm3, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm3
+; SSE-NEXT: orpd %xmm3, %xmm0
+;
+; AVX-LABEL: test_v2f64_oge_s:
+; AVX: # %bb.0:
+; AVX: vcmplepd {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_oge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgepd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_oge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplepd %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_olt_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_olt_s:
+; SSE: # %bb.0:
+; SSE: cmpltpd {{.*}}, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_olt_s:
+; AVX: # %bb.0:
+; AVX: vcmpltpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_olt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpltpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_olt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ole_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ole_s:
+; SSE: # %bb.0:
+; SSE: cmplepd {{.*}}, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_ole_s:
+; AVX: # %bb.0:
+; AVX: vcmplepd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ole_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplepd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ole_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplepd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_one_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_one_s:
+; SSE: # %bb.0:
+; SSE: cmpltpd %xmm3, %xmm4
+; SSE: cmpneqpd %xmm3, %xmm4
+; SSE-NEXT: cmpordpd %xmm3, %xmm2
+; SSE-NEXT: andpd %xmm4, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_one_s:
+; AVX: # %bb.0:
+; AVX: vcmpneq_ospd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_one_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_ospd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_one_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_ospd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ord_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ord_s:
+; SSE: # %bb.0:
+; SSE: cmpltpd %xmm3, %xmm4
+; SSE-NEXT: cmpordpd %xmm3, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_ord_s:
+; AVX: # %bb.0:
+; AVX: vcmpord_spd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ord_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpord_spd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ord_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpord_spd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ueq_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ueq_s:
+; SSE: # %bb.0:
+; SSE: cmpltpd %xmm3, %xmm4
+; SSE: cmpeqpd %xmm3, %xmm4
+; SSE-NEXT: cmpunordpd %xmm3, %xmm2
+; SSE-NEXT: orpd %xmm4, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_ueq_s:
+; AVX: # %bb.0:
+; AVX: vcmpeq_uspd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ueq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uspd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ueq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uspd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ugt_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ugt_s:
+; SSE: # %bb.0:
+; SSE: cmpnlepd {{.*}}, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_ugt_s:
+; AVX: # %bb.0:
+; AVX: vcmpnlepd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ugt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlepd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ugt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlepd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_uge_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_uge_s:
+; SSE: # %bb.0:
+; SSE: cmpnltpd {{.*}}, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_uge_s:
+; AVX: # %bb.0:
+; AVX: vcmpnltpd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_uge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnltpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_uge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltpd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ult_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ult_s:
+; SSE: # %bb.0:
+; SSE: cmpnlepd {{.*}}, %xmm3
+; SSE-NEXT: andpd %xmm3, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm3
+; SSE-NEXT: orpd %xmm3, %xmm0
+;
+; AVX-LABEL: test_v2f64_ult_s:
+; AVX: # %bb.0:
+; AVX: vcmpnlepd {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ult_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngepd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ult_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlepd %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_ule_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_ule_s:
+; SSE: # %bb.0:
+; SSE: cmpnltpd {{.*}}, %xmm3
+; SSE-NEXT: andpd %xmm3, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm3
+; SSE-NEXT: orpd %xmm3, %xmm0
+;
+; AVX-LABEL: test_v2f64_ule_s:
+; AVX: # %bb.0:
+; AVX: vcmpnltpd {{.*}}, %xmm3, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_ule_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngtpd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_ule_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltpd %xmm2, %xmm3, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_une_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_une_s:
+; SSE: # %bb.0:
+; SSE: cmpltpd %xmm3, %xmm4
+; SSE-NEXT: cmpneqpd %xmm3, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_une_s:
+; AVX: # %bb.0:
+; AVX: vcmpneq_uspd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_une_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_uspd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_une_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_uspd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+define <2 x i64> @test_v2f64_uno_s(<2 x i64> %a, <2 x i64> %b, <2 x double> %f1, <2 x double> %f2) #0 {
+; SSE-LABEL: test_v2f64_uno_s:
+; SSE: # %bb.0:
+; SSE: cmpltpd %xmm3, %xmm4
+; SSE-NEXT: cmpunordpd %xmm3, %xmm2
+; SSE-NEXT: andpd %xmm2, %xmm0
+; SSE-NEXT: andnpd %xmm1, %xmm2
+; SSE-NEXT: orpd %xmm2, %xmm0
+;
+; AVX-LABEL: test_v2f64_uno_s:
+; AVX: # %bb.0:
+; AVX: vcmpunord_spd {{.*}}, %xmm2, %xmm2
+; AVX-NEXT: vblendvpd %xmm2, %xmm0, %xmm1, %xmm0
+;
+; AVX512-32-LABEL: test_v2f64_uno_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunord_spd 8(%ebp), %xmm2, %k1
+; AVX512-32-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v2f64_uno_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunord_spd %xmm3, %xmm2, %k1
+; AVX512-64-NEXT: vpblendmq %xmm0, %xmm1, %xmm0 {%k1}
+ %cond = call <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(
+ <2 x double> %f1, <2 x double> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <2 x i1> %cond, <2 x i64> %a, <2 x i64> %b
+ ret <2 x i64> %res
+}
+
+attributes #0 = { strictfp }
+
+declare <4 x i1> @llvm.experimental.constrained.fcmp.v4f32(<4 x float>, <4 x float>, metadata, metadata)
+declare <2 x i1> @llvm.experimental.constrained.fcmp.v2f64(<2 x double>, <2 x double>, metadata, metadata)
+declare <4 x i1> @llvm.experimental.constrained.fcmps.v4f32(<4 x float>, <4 x float>, metadata, metadata)
+declare <2 x i1> @llvm.experimental.constrained.fcmps.v2f64(<2 x double>, <2 x double>, metadata, metadata)
diff --git a/llvm/test/CodeGen/X86/vec-strict-256-cmp.ll b/llvm/test/CodeGen/X86/vec-strict-256-cmp.ll
new file mode 100644
index 0000000..c8aaa6a
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vec-strict-256-cmp.ll
@@ -0,0 +1,1243 @@
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+avx -O3 | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+avx512f -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=CHECK,AVX512-32
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f -mattr=+avx512vl -O3 | FileCheck %s --check-prefixes=CHECK,AVX512-64
+
+define <8 x i32> @test_v8f32_oeq_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_oeq_q:
+; AVX: # %bb.0:
+; AVX: vcmpeqps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_oeq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_oeq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeqps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ogt_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ogt_q:
+; AVX: # %bb.0:
+; AVX: vcmplt_oqps {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ogt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgt_oqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ogt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqps %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_oge_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_oge_q:
+; AVX: # %bb.0:
+; AVX: vcmple_oqps {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_oge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpge_oqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_oge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqps %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_olt_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_olt_q:
+; AVX: # %bb.0:
+; AVX: vcmplt_oqps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_olt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplt_oqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_olt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ole_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ole_q:
+; AVX: # %bb.0:
+; AVX: vcmple_oqps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ole_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmple_oqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ole_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_one_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_one_q:
+; AVX: # %bb.0:
+; AVX: vcmpneq_oqps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_one_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_oqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_one_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_oqps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ord_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ord_q:
+; AVX: # %bb.0:
+; AVX: vcmpordps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ord_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpordps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ord_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpordps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ueq_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ueq_q:
+; AVX: # %bb.0:
+; AVX: vcmpeq_uqps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ueq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ueq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uqps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ugt_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ugt_q:
+; AVX: # %bb.0:
+; AVX: vcmpnle_uqps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ugt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnle_uqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ugt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_uge_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_uge_q:
+; AVX: # %bb.0:
+; AVX: vcmpnlt_uqps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_uge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlt_uqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_uge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ult_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ult_q:
+; AVX: # %bb.0:
+; AVX: vcmpnle_uqps {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ult_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnge_uqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ult_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqps %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ule_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ule_q:
+; AVX: # %bb.0:
+; AVX: vcmpnlt_uqps {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ule_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngt_uqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ule_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqps %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_une_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_une_q:
+; AVX: # %bb.0:
+; AVX: vcmpneqps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_une_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneqps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_une_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneqps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_uno_q(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_uno_q:
+; AVX: # %bb.0:
+; AVX: vcmpunordps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_uno_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunordps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_uno_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunordps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <4 x i64> @test_v4f64_oeq_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_oeq_q:
+; AVX: # %bb.0:
+; AVX: vcmpeqpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_oeq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_oeq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeqpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ogt_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ogt_q:
+; AVX: # %bb.0:
+; AVX: vcmplt_oqpd {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ogt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgt_oqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ogt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqpd %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_oge_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_oge_q:
+; AVX: # %bb.0:
+; AVX: vcmple_oqpd {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_oge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpge_oqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_oge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqpd %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_olt_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_olt_q:
+; AVX: # %bb.0:
+; AVX: vcmplt_oqpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_olt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplt_oqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_olt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ole_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ole_q:
+; AVX: # %bb.0:
+; AVX: vcmple_oqpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ole_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmple_oqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ole_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_one_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_one_q:
+; AVX: # %bb.0:
+; AVX: vcmpneq_oqpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_one_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_oqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_one_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_oqpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ord_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ord_q:
+; AVX: # %bb.0:
+; AVX: vcmpordpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ord_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpordpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ord_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpordpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ueq_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ueq_q:
+; AVX: # %bb.0:
+; AVX: vcmpeq_uqpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ueq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ueq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uqpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ugt_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ugt_q:
+; AVX: # %bb.0:
+; AVX: vcmpnle_uqpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ugt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnle_uqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ugt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_uge_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_uge_q:
+; AVX: # %bb.0:
+; AVX: vcmpnlt_uqpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_uge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlt_uqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_uge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ult_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ult_q:
+; AVX: # %bb.0:
+; AVX: vcmpnle_uqpd {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ult_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnge_uqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ult_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqpd %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ule_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ule_q:
+; AVX: # %bb.0:
+; AVX: vcmpnlt_uqpd {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ule_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngt_uqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ule_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqpd %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_une_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_une_q:
+; AVX: # %bb.0:
+; AVX: vcmpneqpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_une_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneqpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_une_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneqpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_uno_q(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_uno_q:
+; AVX: # %bb.0:
+; AVX: vcmpunordpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_uno_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunordpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_uno_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunordpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <8 x i32> @test_v8f32_oeq_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_oeq_s:
+; AVX: # %bb.0:
+; AVX: vcmpeq_osps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_oeq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_osps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_oeq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_osps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ogt_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ogt_s:
+; AVX: # %bb.0:
+; AVX: vcmpltps {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ogt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgtps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ogt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltps %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_oge_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_oge_s:
+; AVX: # %bb.0:
+; AVX: vcmpleps {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_oge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgeps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_oge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpleps %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_olt_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_olt_s:
+; AVX: # %bb.0:
+; AVX: vcmpltps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_olt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpltps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_olt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ole_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ole_s:
+; AVX: # %bb.0:
+; AVX: vcmpleps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ole_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpleps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ole_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpleps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_one_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_one_s:
+; AVX: # %bb.0:
+; AVX: vcmpneq_osps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_one_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_osps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_one_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_osps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ord_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ord_s:
+; AVX: # %bb.0:
+; AVX: vcmpord_sps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ord_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpord_sps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ord_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpord_sps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ueq_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ueq_s:
+; AVX: # %bb.0:
+; AVX: vcmpeq_usps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ueq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_usps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ueq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_usps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ugt_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ugt_s:
+; AVX: # %bb.0:
+; AVX: vcmpnleps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ugt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnleps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ugt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnleps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_uge_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_uge_s:
+; AVX: # %bb.0:
+; AVX: vcmpnltps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_uge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnltps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_uge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ult_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ult_s:
+; AVX: # %bb.0:
+; AVX: vcmpnleps {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ult_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngeps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ult_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnleps %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_ule_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_ule_s:
+; AVX: # %bb.0:
+; AVX: vcmpnltps {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_ule_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngtps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_ule_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltps %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_une_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_une_s:
+; AVX: # %bb.0:
+; AVX: vcmpneq_usps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_une_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_usps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_une_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_usps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <8 x i32> @test_v8f32_uno_s(<8 x i32> %a, <8 x i32> %b, <8 x float> %f1, <8 x float> %f2) #0 {
+; AVX-LABEL: test_v8f32_uno_s:
+; AVX: # %bb.0:
+; AVX: vcmpunord_sps {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvps %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v8f32_uno_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunord_sps 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f32_uno_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunord_sps %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmd %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(
+ <8 x float> %f1, <8 x float> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i32> %a, <8 x i32> %b
+ ret <8 x i32> %res
+}
+
+define <4 x i64> @test_v4f64_oeq_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_oeq_s:
+; AVX: # %bb.0:
+; AVX: vcmpeq_ospd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_oeq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_ospd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_oeq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_ospd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ogt_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ogt_s:
+; AVX: # %bb.0:
+; AVX: vcmpltpd {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ogt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgtpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ogt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltpd %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_oge_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_oge_s:
+; AVX: # %bb.0:
+; AVX: vcmplepd {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_oge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgepd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_oge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplepd %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_olt_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_olt_s:
+; AVX: # %bb.0:
+; AVX: vcmpltpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_olt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpltpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_olt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ole_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ole_s:
+; AVX: # %bb.0:
+; AVX: vcmplepd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ole_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplepd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ole_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplepd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_one_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_one_s:
+; AVX: # %bb.0:
+; AVX: vcmpneq_ospd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_one_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_ospd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_one_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_ospd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ord_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ord_s:
+; AVX: # %bb.0:
+; AVX: vcmpord_spd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ord_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpord_spd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ord_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpord_spd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ueq_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ueq_s:
+; AVX: # %bb.0:
+; AVX: vcmpeq_uspd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ueq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uspd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ueq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uspd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ugt_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ugt_s:
+; AVX: # %bb.0:
+; AVX: vcmpnlepd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ugt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlepd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ugt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlepd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_uge_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_uge_s:
+; AVX: # %bb.0:
+; AVX: vcmpnltpd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_uge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnltpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_uge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltpd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ult_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ult_s:
+; AVX: # %bb.0:
+; AVX: vcmpnlepd {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ult_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngepd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ult_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlepd %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_ule_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_ule_s:
+; AVX: # %bb.0:
+; AVX: vcmpnltpd {{.*}}, %ymm3, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_ule_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngtpd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_ule_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltpd %ymm2, %ymm3, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_une_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_une_s:
+; AVX: # %bb.0:
+; AVX: vcmpneq_uspd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_une_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_uspd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_une_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_uspd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+define <4 x i64> @test_v4f64_uno_s(<4 x i64> %a, <4 x i64> %b, <4 x double> %f1, <4 x double> %f2) #0 {
+; AVX-LABEL: test_v4f64_uno_s:
+; AVX: # %bb.0:
+; AVX: vcmpunord_spd {{.*}}, %ymm2, %ymm2
+; AVX-NEXT: vblendvpd %ymm2, %ymm0, %ymm1, %ymm0
+;
+; AVX512-32-LABEL: test_v4f64_uno_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunord_spd 8(%ebp), %ymm2, %k1
+; AVX512-32-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+;
+; AVX512-64-LABEL: test_v4f64_uno_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunord_spd %ymm3, %ymm2, %k1
+; AVX512-64-NEXT: vpblendmq %ymm0, %ymm1, %ymm0 {%k1}
+ %cond = call <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(
+ <4 x double> %f1, <4 x double> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <4 x i1> %cond, <4 x i64> %a, <4 x i64> %b
+ ret <4 x i64> %res
+}
+
+attributes #0 = { strictfp }
+
+declare <8 x i1> @llvm.experimental.constrained.fcmp.v8f32(<8 x float>, <8 x float>, metadata, metadata)
+declare <4 x i1> @llvm.experimental.constrained.fcmp.v4f64(<4 x double>, <4 x double>, metadata, metadata)
+declare <8 x i1> @llvm.experimental.constrained.fcmps.v8f32(<8 x float>, <8 x float>, metadata, metadata)
+declare <4 x i1> @llvm.experimental.constrained.fcmps.v4f64(<4 x double>, <4 x double>, metadata, metadata)
diff --git a/llvm/test/CodeGen/X86/vec-strict-512-cmp.ll b/llvm/test/CodeGen/X86/vec-strict-512-cmp.ll
new file mode 100644
index 0000000..3671d1b
--- /dev/null
+++ b/llvm/test/CodeGen/X86/vec-strict-512-cmp.ll
@@ -0,0 +1,961 @@
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=i686-unknown-unknown -mattr=+avx512f -O3 | FileCheck %s --check-prefixes=CHECK,AVX512-32
+; RUN: llc -disable-strictnode-mutation < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f -O3 | FileCheck %s --check-prefixes=CHECK,AVX512-64
+
+define <16 x i32> @test_v16f32_oeq_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_oeq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_oeq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeqps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ogt_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ogt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgt_oqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ogt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqps %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_oge_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_oge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpge_oqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_oge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqps %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_olt_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_olt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplt_oqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_olt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ole_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ole_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmple_oqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ole_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_one_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_one_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_oqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_one_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_oqps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ord_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ord_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpordps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ord_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpordps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ueq_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ueq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ueq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uqps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ugt_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ugt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnle_uqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ugt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_uge_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_uge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlt_uqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_uge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ult_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ult_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnge_uqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ult_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqps %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ule_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ule_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngt_uqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ule_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqps %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_une_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_une_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneqps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_une_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneqps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_uno_q(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_uno_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunordps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_uno_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunordps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <8 x i64> @test_v8f64_oeq_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_oeq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_oeq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeqpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ogt_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ogt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgt_oqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ogt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqpd %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_oge_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_oge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpge_oqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_oge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqpd %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_olt_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_olt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplt_oqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_olt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplt_oqpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ole_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ole_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmple_oqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ole_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmple_oqpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_one_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_one_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_oqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_one_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_oqpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ord_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ord_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpordpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ord_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpordpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ueq_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ueq_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ueq_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uqpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ugt_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ugt_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnle_uqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ugt_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_uge_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_uge_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlt_uqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_uge_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ult_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ult_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnge_uqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ult_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnle_uqpd %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ule_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ule_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngt_uqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ule_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlt_uqpd %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_une_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_une_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneqpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_une_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneqpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_uno_q(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_uno_q:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunordpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_uno_q:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunordpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <16 x i32> @test_v16f32_oeq_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_oeq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_osps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_oeq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_osps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ogt_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ogt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgtps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ogt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltps %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_oge_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_oge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgeps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_oge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpleps %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_olt_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_olt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpltps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_olt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ole_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ole_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpleps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ole_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpleps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_one_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_one_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_osps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_one_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_osps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ord_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ord_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpord_sps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ord_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpord_sps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ueq_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ueq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_usps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ueq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_usps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ugt_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ugt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnleps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ugt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnleps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_uge_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_uge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnltps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_uge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ult_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ult_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngeps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ult_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnleps %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_ule_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_ule_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngtps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_ule_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltps %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_une_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_une_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_usps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_une_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_usps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <16 x i32> @test_v16f32_uno_s(<16 x i32> %a, <16 x i32> %b, <16 x float> %f1, <16 x float> %f2) #0 {
+; AVX512-32-LABEL: test_v16f32_uno_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunord_sps 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v16f32_uno_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunord_sps %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmd %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(
+ <16 x float> %f1, <16 x float> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <16 x i1> %cond, <16 x i32> %a, <16 x i32> %b
+ ret <16 x i32> %res
+}
+
+define <8 x i64> @test_v8f64_oeq_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_oeq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_ospd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_oeq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_ospd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"oeq",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ogt_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ogt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgtpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ogt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltpd %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ogt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_oge_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_oge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpgepd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_oge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplepd %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"oge",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_olt_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_olt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpltpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_olt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpltpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"olt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ole_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ole_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmplepd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ole_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmplepd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ole",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_one_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_one_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_ospd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_one_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_ospd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"one",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ord_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ord_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpord_spd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ord_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpord_spd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ord",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ueq_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ueq_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpeq_uspd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ueq_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpeq_uspd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ueq",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ugt_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ugt_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnlepd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ugt_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlepd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ugt",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_uge_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_uge_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpnltpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_uge_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltpd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"uge",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ult_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ult_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngepd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ult_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnlepd %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ult",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_ule_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_ule_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpngtpd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_ule_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpnltpd %zmm2, %zmm3, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"ule",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_une_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_une_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpneq_uspd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_une_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpneq_uspd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"une",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+define <8 x i64> @test_v8f64_uno_s(<8 x i64> %a, <8 x i64> %b, <8 x double> %f1, <8 x double> %f2) #0 {
+; AVX512-32-LABEL: test_v8f64_uno_s:
+; AVX512-32: # %bb.0:
+; AVX512-32: vcmpunord_spd 8(%ebp), %zmm2, %k1
+; AVX512-32-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+;
+; AVX512-64-LABEL: test_v8f64_uno_s:
+; AVX512-64: # %bb.0:
+; AVX512-64-NEXT: vcmpunord_spd %zmm3, %zmm2, %k1
+; AVX512-64-NEXT: vpblendmq %zmm0, %zmm1, %zmm0 {%k1}
+ %cond = call <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(
+ <8 x double> %f1, <8 x double> %f2, metadata !"uno",
+ metadata !"fpexcept.strict") #0
+ %res = select <8 x i1> %cond, <8 x i64> %a, <8 x i64> %b
+ ret <8 x i64> %res
+}
+
+attributes #0 = { strictfp }
+
+declare <16 x i1> @llvm.experimental.constrained.fcmp.v16f32(<16 x float>, <16 x float>, metadata, metadata)
+declare <8 x i1> @llvm.experimental.constrained.fcmp.v8f64(<8 x double>, <8 x double>, metadata, metadata)
+declare <16 x i1> @llvm.experimental.constrained.fcmps.v16f32(<16 x float>, <16 x float>, metadata, metadata)
+declare <8 x i1> @llvm.experimental.constrained.fcmps.v8f64(<8 x double>, <8 x double>, metadata, metadata)
