commit 1fe1299a93e1001455cb5088ed2cac87967f0029
author Matt Arsenault <Matthew.Arsenault@amd.com> Thu Nov 17 23:03:23 2022 -0800
committer Matt Arsenault <Matthew.Arsenault@amd.com> Fri Nov 18 15:21:41 2022 -0800
tree 1cde31478548444501ae262db10b5258367a6c41
parent ea1826ee57984d4f44fdb4b35a47169d393618ed

GlobalISel: Legalize strict_fsub

In the future should probably have a more convenient
way to switch between building strict and non-strict ops.

llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp

diff --git a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
index b8460f1..6ea4f6c 100644
--- a/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/LegalizerHelper.cpp
@@ -3319,7 +3319,8 @@
     MI.eraseFromParent();
     return Legalized;
   }
-  case TargetOpcode::G_FSUB: {
+  case TargetOpcode::G_FSUB:
+  case TargetOpcode::G_STRICT_FSUB: {
     Register Res = MI.getOperand(0).getReg();
     LLT Ty = MRI.getType(Res);
 
@@ -3330,9 +3331,13 @@
       return UnableToLegalize;
     Register LHS = MI.getOperand(1).getReg();
     Register RHS = MI.getOperand(2).getReg();
-    Register Neg = MRI.createGenericVirtualRegister(Ty);
-    MIRBuilder.buildFNeg(Neg, RHS);
-    MIRBuilder.buildFAdd(Res, LHS, Neg, MI.getFlags());
+    auto Neg = MIRBuilder.buildFNeg(Ty, RHS);
+
+    if (MI.getOpcode() == TargetOpcode::G_STRICT_FSUB)
+      MIRBuilder.buildStrictFAdd(Res, LHS, Neg, MI.getFlags());
+    else
+      MIRBuilder.buildFAdd(Res, LHS, Neg, MI.getFlags());
+
     MI.eraseFromParent();
     return Legalized;
   }
@@ -4219,6 +4224,7 @@
   case G_SADDE:
   case G_SSUBE:
   case G_STRICT_FADD:
+  case G_STRICT_FSUB:
   case G_STRICT_FMUL:
   case G_STRICT_FMA:
     return fewerElementsVectorMultiEltType(GMI, NumElts);