| commit | 1dbb932fd8681930ed98fe621bbe4bdaa5aeaa5c | [log] [tgz] |
|---|---|---|
| author | Matt Arsenault <Matthew.Arsenault@amd.com> | Wed Sep 17 19:43:50 2025 +0900 |
| committer | GitHub <noreply@github.com> | Wed Sep 17 19:43:50 2025 +0900 |
| tree | fb378b3a7e2e0738de5dc16e644e576634dd93a6 | |
| parent | 9690a718b8d5344583eadfbc5bf2249d7d39b777 [diff] |
GlobalISel: Relax verifier between physreg and typed vreg (#159281) Accept mismatched register size and type size if the type is legal for the register class. For AMDGPU boolean registers have 2 possible interpretations depending on the use context type. e.g., these are both equally valid: %0:_(s1) = COPY $vcc %1:_(s64) = COPY $vcc vcc is a 64-bit register, which can be interpreted as a 1-bit or 64-bit value depending on the use context. SelectionDAG has never required exact match between the register size and the used value type. You can assign a type with a smaller size to a larger register class. Relax the verifier to match. There are several hacks holding together these copies in various places, and this is preparation to remove one of them. The x86 test change is from what I would consider an X86 usage bug. X86 defines an FR32 register class and F16 register class, but the F16 register class is functionally an alias of F32 with the same members and size. There's no need to have the F16 class.
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