)]}'
{
  "commit": "1d616cdca3aba9d22f120888bb6b09b75ca90b92",
  "tree": "8db918ccce937884df8f8b7d864cbb3a94fda2b9",
  "parents": [
    "444adbe53472582f3f077fa1a16e52df97caddb8"
  ],
  "author": {
    "name": "Sam Elliott",
    "email": "aelliott@qti.qualcomm.com",
    "time": "Thu Jan 15 07:47:05 2026 -0800"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Thu Jan 15 07:47:05 2026 -0800"
  },
  "message": "[NFC][MI] Tidy Up RegState enum use (1/2) (#176091)\n\nThis Change is to prepare to make RegState into an enum class. It:\n- Updates documentation to match the order in the code.\n- Brings the `get\u003c\u003eRegState` functions together and makes them\n`constexpr`.\n- Adopts the `get\u003c\u003eRegState` where RegStates were being chosen with\nternary operators in backend code.\n- Introduces `hasRegState` to make querying RegState easier once it is\nan enum class.\n- Adopts `hasRegState` where equivalent was done with bitwise\narithmetic.\n- Introduces `RegState::NoFlags`, which will be used for the lack of\nflags.\n- Documents that `0x1` is a reserved flag value used to detect if\nsomeone is passing `true` instead of flags (due to implicit bool to\nunsigned conversions).\n- Updates two calls to `MachineInstrBuilder::addReg` which were passing\n`false` to the flags operand, to no longer pass a value.\n- Documents that `getRegState` seems to have forgotten a call to\n`getEarlyClobberRegState`.",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "32c96d197a027bd40a69ca10421103349ef25c6b",
      "old_mode": 33188,
      "old_path": "llvm/docs/MIRLangRef.rst",
      "new_id": "efb20520db1b12e954f60867c6b6c091dbf717ff",
      "new_mode": 33188,
      "new_path": "llvm/docs/MIRLangRef.rst"
    },
    {
      "type": "modify",
      "old_id": "060f0c41de73a129ee7fc12203038c4783501f00",
      "old_mode": 33188,
      "old_path": "llvm/include/llvm/CodeGen/MachineInstrBuilder.h",
      "new_id": "8269dc9221153c76ebc81f9efe8c68059875dc78",
      "new_mode": 33188,
      "new_path": "llvm/include/llvm/CodeGen/MachineInstrBuilder.h"
    },
    {
      "type": "modify",
      "old_id": "2927b075fc36056f60624d8728dfc92c35378392",
      "old_mode": 33188,
      "old_path": "llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp",
      "new_id": "f16a175af2357f142a9e69fb3e1e2e52de4e4cea",
      "new_mode": 33188,
      "new_path": "llvm/lib/CodeGen/GlobalISel/InlineAsmLowering.cpp"
    },
    {
      "type": "modify",
      "old_id": "baac77fbd2dc022bfa71822250d675a553e02bf9",
      "old_mode": 33188,
      "old_path": "llvm/lib/CodeGen/MIRParser/MIParser.cpp",
      "new_id": "1071cf00aa84345410ae2ed3821e0f1798a662cf",
      "new_mode": 33188,
      "new_path": "llvm/lib/CodeGen/MIRParser/MIParser.cpp"
    },
    {
      "type": "modify",
      "old_id": "473aaa94242eb4a48e9a11bee7c2e6c208e85a9f",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp",
      "new_id": "173bcebf5d3ca6a98165bfb32458f707cc078f87",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp"
    },
    {
      "type": "modify",
      "old_id": "2e96abfce72dfdc288bb94fbe49bb3995354818f",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AArch64/AArch64ISelLowering.cpp",
      "new_id": "273823f028e25519e6bb2a68155a0c49060cdb6b",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AArch64/AArch64ISelLowering.cpp"
    },
    {
      "type": "modify",
      "old_id": "f07211325393d929191bd0040e4ed83eff577fbd",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AArch64/AArch64InstrInfo.cpp",
      "new_id": "6b4e4c720e7dcfe07e691ea91b8ecc3f7b3bae82",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AArch64/AArch64InstrInfo.cpp"
    },
    {
      "type": "modify",
      "old_id": "464cbec6c46bcd8eb968f45f0d7cf332272abd5f",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp",
      "new_id": "1d6f2ec3b3aa5fda10ae1f60fafadfca5eb4a221",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp"
    },
    {
      "type": "modify",
      "old_id": "44a4058525851a71f1b3f70510d99a50b7d599dc",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp",
      "new_id": "9838f1b1ef32aff9f20bb96be54f47516d255931",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/GCNHazardRecognizer.cpp"
    },
    {
      "type": "modify",
      "old_id": "0ee5f082aeeefa263b74e30613e28cdf0b16131f",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp",
      "new_id": "56d1a194b7384bea4cf296906a15e6da4e9f2cea",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/R600MachineCFGStructurizer.cpp"
    },
    {
      "type": "modify",
      "old_id": "829817c9a027d4beda16345fbf27dfd357d16aa7",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/SIInstrInfo.cpp",
      "new_id": "be6087c76bd9a87105e27034cf942589ac07c483",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/SIInstrInfo.cpp"
    },
    {
      "type": "modify",
      "old_id": "acc4b3f0a68b4f99a5ec3300817fe417d920c40d",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp",
      "new_id": "926c52fa027b71bbc1e3530460d97ea9b3086f7e",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/SIPeepholeSDWA.cpp"
    },
    {
      "type": "modify",
      "old_id": "3657e0a4dc93615d97805ad9ca37faa65e605765",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp",
      "new_id": "409509120c32de80275f00ecdcaf2c77bc99f2e3",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp"
    },
    {
      "type": "modify",
      "old_id": "d69c09fcb39db1865cac5b92bb51ebcd3d533615",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp",
      "new_id": "f4f07b4c195604973377453ac9f8b261c33c84c6",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp"
    },
    {
      "type": "modify",
      "old_id": "3f9ea3757a5ee5f98b33b51b0120bed84852a044",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp",
      "new_id": "0bb637edbae96d0a6241fe7fb614abe72a7badcd",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/ARM/ARMFixCortexA57AES1742098Pass.cpp"
    },
    {
      "type": "modify",
      "old_id": "18e41297b1734070c018b9052c7e1e3c37a92533",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/ARM/Thumb2SizeReduction.cpp",
      "new_id": "500c7b5ef67ca657d073bc7f8bf9c41a364dc13c",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/ARM/Thumb2SizeReduction.cpp"
    },
    {
      "type": "modify",
      "old_id": "35153c7b16c0f24f108c9f9f344d4de1684dd03a",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp",
      "new_id": "b8c764a0d3af010578097a907c1d08c286fdfe27",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/Hexagon/HexagonExpandCondsets.cpp"
    },
    {
      "type": "modify",
      "old_id": "8de6eea10e56213730d63a7bf642f156b5341c09",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp",
      "new_id": "bb20f79fd6fd5c89544cb033971a797d0309326b",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/LoongArch/LoongArchInstrInfo.cpp"
    },
    {
      "type": "modify",
      "old_id": "ef211bf8c898282399a0ebcb2b10e8ed160ee5cd",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/PowerPC/PPCISelLowering.cpp",
      "new_id": "494cd327716486e1908696f87df892f5e3318309",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/PowerPC/PPCISelLowering.cpp"
    },
    {
      "type": "modify",
      "old_id": "9467c15ec6f64dda0898265474e1c3ada038050e",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/PowerPC/PPCInstrInfo.cpp",
      "new_id": "7a4f3d51172455f7354b01ee82cdb5e94543e686",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/PowerPC/PPCInstrInfo.cpp"
    },
    {
      "type": "modify",
      "old_id": "cf679d786ab616eec24a7044d6c145857aae7923",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/RISCV/RISCVInstrInfo.cpp",
      "new_id": "421134fb45d7ce79b6f3f56f3ca4836b335759c3",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/RISCV/RISCVInstrInfo.cpp"
    },
    {
      "type": "modify",
      "old_id": "8b4e4fbbbd1e5ab2ad850841e1d863f6619c56e0",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp",
      "new_id": "bd3e282ba944fc60acc59afe27ef94b87e7d1b71",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.cpp"
    },
    {
      "type": "modify",
      "old_id": "6a92866f315750961891ea104eab81ea588d398d",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/X86/X86FixupLEAs.cpp",
      "new_id": "07f656fc5ccfd3ed32b66e4a90cee378b0b2cb2a",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/X86/X86FixupLEAs.cpp"
    }
  ]
}
