tree 41aecc02cb5a426e3a289e4618c0946be01d893d
parent 3e39820ecf2cf5b8a44d57e075a6156a032ab167
author Sang Ik Lee <sang.ik.lee@intel.com> 1755896987 -0700
committer GitHub <noreply@github.com> 1755896987 -0700
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[MLIR][XeGPU] Update XeGPU create_tdesc, update_offset, load, store and prefetch. (#154653)

This PR tightens some loose ends in some XeGPU op definitions.
Changes are backward compatible except for

- Enforcing previous implicit assumption of load/store/prefetch offsets
is required if source/dest is not a scatter tensor descriptor.
- Likewise, enforce offsets is not allowed if source/dest is a scatter
tensor descriptor.
- Additionally, allow i64, i32 and ui32 as source/dest for
load/store/prefetch. This matches behavior of tensor descriptor which
allows i64, i32 and ui32 base address in addition to ui64
- Explicitly state that create_tdesc and update_offset ops are not valid
in SIMT mode. create_tdesc and update_offset ops are still available for
subgroup level non SIMT mode.
- prefetch op adds attribute offset_align_byte to be used with integer
 pointer source to enable address calculation with offsets.

New test cases are added for the new enforced checks.

Other minor implementation change:
XeGPU scatter tensor descriptor only allows 1D base memref. This was
check in op verify() method. Now moved to tablegen - ODS - definition.