; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a < %s | FileCheck %s

define protected amdgpu_kernel void @foo(ptr addrspace(1) %arg, ptr addrspace(1) %arg1) {
; CHECK-LABEL: foo:
; CHECK:       ; %bb.0: ; %bb
; CHECK-NEXT:    s_add_u32 flat_scratch_lo, s12, s17
; CHECK-NEXT:    s_addc_u32 flat_scratch_hi, s13, 0
; CHECK-NEXT:    s_add_u32 s0, s0, s17
; CHECK-NEXT:    s_addc_u32 s1, s1, 0
; CHECK-NEXT:    s_add_u32 s8, s8, 16
; CHECK-NEXT:    s_addc_u32 s9, s9, 0
; CHECK-NEXT:    s_mov_b32 s13, s15
; CHECK-NEXT:    s_mov_b32 s12, s14
; CHECK-NEXT:    s_getpc_b64 s[18:19]
; CHECK-NEXT:    s_add_u32 s18, s18, eggs@rel32@lo+4
; CHECK-NEXT:    s_addc_u32 s19, s19, eggs@rel32@hi+12
; CHECK-NEXT:    s_mov_b32 s14, s16
; CHECK-NEXT:    v_mov_b32_e32 v31, v0
; CHECK-NEXT:    v_mov_b32_e32 v1, 0
; CHECK-NEXT:    s_mov_b32 s32, 0
; CHECK-NEXT:    s_swappc_b64 s[30:31], s[18:19]
; CHECK-NEXT:    s_mov_b64 s[4:5], src_private_base
; CHECK-NEXT:    v_mov_b32_e32 v2, 0
; CHECK-NEXT:    v_mov_b32_e32 v3, s5
; CHECK-NEXT:    flat_load_dwordx2 v[2:3], v[2:3]
; CHECK-NEXT:    s_waitcnt vmcnt(0) lgkmcnt(0)
; CHECK-NEXT:    flat_store_dwordx2 v[2:3], v[0:1]
; CHECK-NEXT:    s_endpgm
bb:
  %tmp = addrspacecast ptr addrspace(5) null to ptr
  %tmp2 = call i64 @eggs(ptr poison) #1
  %tmp3 = load ptr, ptr %tmp, align 8
  %tmp4 = getelementptr inbounds i64, ptr %tmp3, i64 0
  store i64 %tmp2, ptr %tmp4, align 8
  ret void
}

declare hidden i64 @eggs(ptr)