tree 82defe12fa67519fb307f5a727d84eb06a2c6d60
parent b9d6cbd4dc1def3f15b7d5ebb8cb4714bdad22bf
author Philip Reames <preames@rivosinc.com> 1746630944 -0700
committer GitHub <noreply@github.com> 1746630944 -0700
gpgsig -----BEGIN PGP SIGNATURE-----
 
 wsFcBAABCAAQBQJoG3kgCRC1aQ7uu5UhlAAA9dYQAEIzVVNKNahmbi9/5vYGrNCf
 rb5IiMDf1tjytDGwv61QIm9bxgp0MgEx0nkX0seAgjV3qQU2rrLOJaZ8JfeTXJg4
 /J9GntIx2C0UwZDl3YhsJkDBcLPvuYLdM3wOd0xOEMUZAif9EPNBZftg+gy5lYQp
 T68JDfqBMtU6OuCbn4BFL/HgEhu/slvtk0+MmFprT7lV7YFblMewbEpwKyKL6tsn
 di7AFIDy+syzZ+Hfqs6/X/dh9qI58ocpRZQswOdomX9YmD0n4asb56vnOe7bH1Ka
 GiuuXlSo55HSIwAFTB4TdDDx4HgG7304zbA3Jbaq9cgnQTQG/6SuS2l/e44+9ePR
 qURG2BaiBBm/Tm7eZbmLq/fWU27WXxBVe+GxmpuFWlQXLtqxy8tOr6zxOpIA+0O2
 vMLfLgeyrvnFAKnCmoWNqpdOBKEOBr98CCcO8KgwFyPohwr1Ovz6ZXy0McN79rqG
 QVufxRcXXWwT0Gio/4RaI/9dRE+J8maSsx2f5yO/XyBLvkuUHGnUWosW4b+K+ho3
 +5BEQuefsUZ8ZU2lA+vVvyVEAZEbR9VUoiy4fZfvU+QnyXWENYRxc5P3sO8Gesnd
 VDFZ2gtysP10FpCbS94UrG3fkt8lFyNdaJqm6F5m8yK3HtlMUnnchO7SmZGsozsN
 E15YQP5RqytETEFcl6yd
 =pQMf
 -----END PGP SIGNATURE-----
 

[RISCV] Initial codegen support for zvqdotq extension (#137039)

This patch adds pattern matching for the basic usages of the dot product
instructions introduced by the experimental zvqdotq extension. It
specifically only handles the case where the pattern is feeding a i32
sum reduction as we need to reassociate the reduction tree to use these
instructions.

The vecreduce_add (sext) and vecreduce_add (zext) cases are included
mostly to exercise the VX matchers. For the generic matching, we fail to
match due to an order of combine issue which results in the bitcast
being separated from the splat.

I chose to do this lowering as an early combine so as to avoid having to
integrate the entire logic into the reduction lowering flow. In
particular, that would get a lot more complicated as we extend this to
handle add-trees feeding the reductions.